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[/] [djpeg/] [trunk/] [src/] [jpeg_regdata.v] - Blame information for rev 3

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1 3 hidemi 
//---------------------------------------------------------------------------
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// File Name   : jpeg_regdata.v
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// Module Name : jpeg_regdata
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// Description : get Data
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// Project     : JPEG Decoder
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// Belong to   :
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// Author      : H.Ishihara
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// E-Mail      : hidemi@sweetcafe.jp
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// HomePage    : http://www.sweetcafe.jp/
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// Date        : 2006/10/01
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// Rev.        : 1.1
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//---------------------------------------------------------------------------
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// Rev. Date       Description
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//---------------------------------------------------------------------------
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// 1.01 2006/10/01 1st Release
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// 1.02 2006/10/04 Remove a RegEnd register.
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//                 When reset, clear on OutEnable,PreEnable,DataOut registers.
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//                 Remove some comments.
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//---------------------------------------------------------------------------
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// $Id:
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//---------------------------------------------------------------------------
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`timescale 1ps / 1ps
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module jpeg_regdata
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  (
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   rst,
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   clk,
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   // Read Data
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   DataInStart,
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   DataIn,       //
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   DataInEnable, // Data Enable
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   DataInRead,   // Data Read
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   // DataOut
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   DataOut,       // Data Out
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   DataOutEnable, // Data Out Enable
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   DataOutEnd,    // Data Out End
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   //
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   ImageEnable,
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   // UseData
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   UseBit,   // Used data bit
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   UseWidth, // Used data bit width
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   UseByte,  // Used data byte
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   UseWord   // Used data word
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   );
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   input         rst;
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   input         clk;
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   input         DataInStart;
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   input [31:0]  DataIn;
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   input         DataInEnable;
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   output        DataInRead;
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   output [31:0] DataOut;
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   output        DataOutEnable;
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   output        DataOutEnd;
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   input         ImageEnable;
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   input         UseBit;
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   input [6:0]   UseWidth;
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   input         UseByte;
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   input         UseWord;
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   wire          RegValid;
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   reg [95:0]    RegData;
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   reg [7:0]     RegWidth;
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   assign        RegValid   = RegWidth > 64;
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   assign        DataInRead = RegValid == 1'b0 & DataInEnable == 1'b1;
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   always @(posedge clk or negedge rst) begin
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      if(!rst) begin
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         RegData  <= 96'd0;
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         RegWidth <= 8'h00;
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      end else begin
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         if(DataInStart == 1'b1) begin
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            RegData  <= 96'd0;
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            RegWidth <= 8'h00;
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         end else if(RegValid == 1'b0 & DataInEnable == 1'b1) begin
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            if(ImageEnable == 1'b1) begin
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               if(RegData[39: 8] == 32'hFF00FF00) begin
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                  RegWidth       <= RegWidth + 16;
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                  RegData[95:64] <= {8'h00,RegData[71:48]};
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                  RegData[63:32] <= {RegData[47:40],16'hFFFF,RegData[7:0]};
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               end else if(RegData[39:24] == 16'hFF00 &
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                           RegData[15: 0] == 16'hFF00) begin
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                  RegWidth       <= RegWidth + 16;
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                  RegData[95:64] <= {8'h00,RegData[71:48]};
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                  RegData[63:32] <= {RegData[47:40],8'hFF,RegData[23:16],8'hFF};
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               end else if(RegData[31: 0] == 32'hFF00FF00) begin
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                  RegWidth       <= RegWidth + 16;
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                  RegData[95:64] <= {16'h0000,RegData[71:56]};
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                  RegData[63:32] <= {RegData[55:40],16'hFFFF};
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               end else if(RegData[39:24] == 16'hFF00) begin
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                  RegWidth       <= RegWidth + 24;
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                  RegData[95:64] <= {RegData[71:40]};
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                  RegData[63:32] <= {8'hFF,RegData[23:0]};
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               end else if(RegData[31:16] == 16'hFF00) begin
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                  RegWidth       <= RegWidth + 24;
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                  RegData[95:64] <= {RegData[71:40]};
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                  RegData[63:32] <= {RegData[39:32],8'hFF,RegData[15:0]};
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               end else if(RegData[23: 8] == 16'hFF00) begin
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                  RegWidth       <= RegWidth + 24;
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                  RegData[95:64] <= {RegData[71:40]};
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                  RegData[63:32] <= {RegData[39:32],RegData[31:24],8'hFF,RegData[7:0]};
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               end else if(RegData[15: 0] == 16'hFF00) begin
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                  RegWidth       <= RegWidth + 24;
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                  RegData[95:64] <= {RegData[71:40]};
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                  RegData[63:32] <= {RegData[39:32],RegData[31:16],8'hFF};
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               end else begin
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                  RegWidth       <= RegWidth + 32;
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                  RegData[95:64] <= RegData[63:32];
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                  RegData[63:32] <= RegData[31:0];
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               end
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            end else begin // if (ImageEnable == 1'b1)
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               RegWidth       <= RegWidth + 32;
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               RegData[95:64] <= RegData[63:32];
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               RegData[63:32] <= RegData[31:0];
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            end // else: !if(ImageEnable == 1'b1)
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            RegData[31: 0] <= {DataIn[7:0],DataIn[15:8],DataIn[23:16],DataIn[31:24]};
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         end else if(UseBit == 1'b1) begin // if (RegValid == 1'b0 & DataInEnable == 1'b1)
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            RegWidth <= RegWidth - UseWidth;
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         end else if(UseByte == 1'b1) begin
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            RegWidth <= RegWidth - 8;
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         end else if(UseWord == 1'b1) begin
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            RegWidth <= RegWidth - 16;
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         end
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      end // else: !if(!rst)
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   end // always @ (posedge clk or negedge rst)
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   assign DataOutEnd = (//RegData[39:24] == 16'hFFD9 |
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                        RegData[31:16] == 16'hFFD9 |
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                        RegData[23: 8] == 16'hFFD9 |
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                        RegData[15: 0] == 16'hFFD9
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                        );
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   function [31:0] SliceData;
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      input [95:0] RegData;
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      input [7:0]  RegWidth;
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      case(RegWidth)
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        8'd65: SliceData = RegData[64:33];
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        8'd66: SliceData = RegData[65:34];
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        8'd67: SliceData = RegData[66:35];
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        8'd68: SliceData = RegData[67:36];
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        8'd69: SliceData = RegData[68:37];
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        8'd70: SliceData = RegData[69:38];
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        8'd71: SliceData = RegData[70:39];
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        8'd72: SliceData = RegData[71:40];
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        8'd73: SliceData = RegData[72:41];
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        8'd74: SliceData = RegData[73:42];
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        8'd75: SliceData = RegData[74:43];
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        8'd76: SliceData = RegData[75:44];
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        8'd77: SliceData = RegData[76:45];
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        8'd78: SliceData = RegData[77:46];
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        8'd79: SliceData = RegData[78:47];
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        8'd80: SliceData = RegData[79:48];
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        8'd81: SliceData = RegData[80:49];
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        8'd82: SliceData = RegData[81:50];
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        8'd83: SliceData = RegData[82:51];
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        8'd84: SliceData = RegData[83:52];
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        8'd85: SliceData = RegData[84:53];
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        8'd86: SliceData = RegData[85:54];
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        8'd87: SliceData = RegData[86:55];
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        8'd88: SliceData = RegData[87:56];
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        8'd89: SliceData = RegData[88:57];
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        8'd90: SliceData = RegData[89:58];
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        8'd91: SliceData = RegData[90:59];
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        8'd92: SliceData = RegData[91:60];
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        8'd93: SliceData = RegData[92:61];
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        8'd94: SliceData = RegData[93:62];
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        8'd95: SliceData = RegData[94:63];
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        8'd96: SliceData = RegData[95:64];
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        default: SliceData = 32'h00000000;
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      endcase // case(RegWidth)
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   endfunction // SliceData
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   reg             OutEnable;
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   reg             PreEnable;
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   reg [31:0]       DataOut;
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   always @(posedge clk or negedge rst) begin
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      if(!rst) begin
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         OutEnable <= 1'b0;
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         PreEnable <= 1'b0;
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         DataOut   <= 32'h00000000;
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      end else begin
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         OutEnable <= RegWidth >64;
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         PreEnable <= (UseBit == 1'b1 | UseByte == 1'b1 | UseWord == 1'b1);
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         DataOut   <= SliceData(RegData,RegWidth);
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      end
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   end
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   assign DataOutEnable = (PreEnable == 1'b0)?OutEnable:1'b0;
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endmodule // jpeg_regdata
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