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[/] [djpeg/] [trunk/] [src/] [jpeg_regdata.v] - Blame information for rev 6

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//---------------------------------------------------------------------------
// File Name    : jpeg_regdata.v
// Module Name  : jpeg_regdata
// Description  : get Data
// Project              : JPEG Decoder
// Belong to    : 
// Author               : H.Ishihara
// E-Mail               : hidemi@sweetcafe.jp
// HomePage             : http://www.sweetcafe.jp/
// Date                 : 2007/04/11
// Rev.                 : 1.03
//---------------------------------------------------------------------------
// Rev. Date             Description
//---------------------------------------------------------------------------
// 1.01 2006/10/01 1st Release
// 1.02 2006/10/04 Remove a RegEnd register.
//                                        When reset, clear on OutEnable,PreEnable,DataOut registers.
//                                        Remove some comments.
// 1.03 2007/04/11 Don't OutEnable, ImageEnable == 1 and DataOut == 0xFFD9XXXX
//                 Stop ReadEnable with DataEnd(after 0xFFD9 of ImageData)
//---------------------------------------------------------------------------
// $Id: 
//---------------------------------------------------------------------------
`timescale 1ps / 1ps
 
module jpeg_regdata(
        rst,
        clk,
 
        // Read Data
        DataIn,                 // 
        DataInEnable,   // Data Enable
        DataInRead,             // Data Read
 
        // DataOut
        DataOut,                // Data Out
        DataOutEnable,  // Data Out Enable
 
        // 
        ImageEnable,
        ProcessIdle,
 
        // UseData
        UseBit,         // Used data bit
        UseWidth,       // Used data bit width
        UseByte,        // Used data byte
        UseWord         // Used data word
        );
 
        input                   rst;
        input                   clk;
 
        input [31:0]    DataIn;
        input                   DataInEnable;
        output                  DataInRead;
 
        output [31:0]   DataOut;
        output                  DataOutEnable;
 
        input                   ImageEnable;
        input                   ProcessIdle;
 
        input                   UseBit;
        input [6:0]             UseWidth;
        input                   UseByte;
        input                   UseWord;
 
        wire                    RegValid;
        reg [95:0]              RegData;
        reg [7:0]               RegWidth;
 
        reg                             DataEnd;
 
        assign                  RegValid        = RegWidth > 64;
        assign                  DataInRead      = RegValid == 1'b0 & DataInEnable == 1'b1;
 
        always @(posedge clk or negedge rst) begin
                if(!rst) begin
                        RegData  <= 96'd0;
                        RegWidth <= 8'h00;
                end else begin
                        if(RegValid == 1'b0 & (DataInEnable == 1'b1 | DataEnd == 1'b1)) begin
                                if(ImageEnable == 1'b1) begin
                                        if(RegData[39: 8] == 32'hFF00FF00) begin
                                                RegWidth                <= RegWidth + 16;
                                                RegData[95:64]  <= {8'h00,RegData[71:48]};
                                                RegData[63:32]  <= {RegData[47:40],16'hFFFF,RegData[7:0]};
                                        end else if(RegData[39:24] == 16'hFF00 &
                                                RegData[15: 0] == 16'hFF00) begin
                                                RegWidth                <= RegWidth + 16;
                                                RegData[95:64]  <= {8'h00,RegData[71:48]};
                                                RegData[63:32]  <= {RegData[47:40],8'hFF,RegData[23:16],8'hFF};
                                        end else if(RegData[31: 0] == 32'hFF00FF00) begin
                                                RegWidth                <= RegWidth + 16;
                                                RegData[95:64]  <= {16'h0000,RegData[71:56]};
                                                RegData[63:32]  <= {RegData[55:40],16'hFFFF};
                                        end else if(RegData[39:24] == 16'hFF00) begin
                                                RegWidth                <= RegWidth + 24;
                                                RegData[95:64]  <= {RegData[71:40]};
                                                RegData[63:32]  <= {8'hFF,RegData[23:0]};
                                        end else if(RegData[31:16] == 16'hFF00) begin
                                                RegWidth                <= RegWidth + 24;
                                                RegData[95:64]  <= {RegData[71:40]};
                                                RegData[63:32]  <= {RegData[39:32],8'hFF,RegData[15:0]};
                                        end else if(RegData[23: 8] == 16'hFF00) begin
                                                RegWidth                <= RegWidth + 24;
                                                RegData[95:64]  <= {RegData[71:40]};
                                                RegData[63:32]  <= {RegData[39:32],RegData[31:24],8'hFF,RegData[7:0]};
                                        end else if(RegData[15: 0] == 16'hFF00) begin
                                                RegWidth                <= RegWidth + 24;
                                                RegData[95:64]  <= {RegData[71:40]};
                                                RegData[63:32]  <= {RegData[39:32],RegData[31:16],8'hFF};
                                        end else begin
                                                RegWidth                <= RegWidth + 32;
                                                RegData[95:64]  <= RegData[63:32];
                                                RegData[63:32]  <= RegData[31:0];
                                        end
                                end else begin
                                        RegWidth                <= RegWidth + 32;
                                        RegData[95:64]  <= RegData[63:32];
                                        RegData[63:32]  <= RegData[31:0];
                                end
                                RegData[31: 0] <= {DataIn[7:0],DataIn[15:8],DataIn[23:16],DataIn[31:24]};
                        end else if(UseBit == 1'b1) begin
                                RegWidth <= RegWidth - UseWidth;
                        end else if(UseByte == 1'b1) begin
                                RegWidth <= RegWidth - 8;
                        end else if(UseWord == 1'b1) begin
                                RegWidth <= RegWidth - 16;
                        end
                end
        end
 
        always @(posedge clk or negedge rst) begin
                if(!rst) begin
                        DataEnd <= 1'b0;
                end else begin
                        if(ProcessIdle) begin
                                DataEnd <= 1'b0;
                        end else if(ImageEnable == 1'b1 & (RegData[39:24] == 16'hFFD9 | RegData[31:16] == 16'hFFD9 | RegData[23: 8] == 16'hFFD9 | RegData[15: 0] == 16'hFFD9)) begin
                                DataEnd <= 1'b1;
                        end
                end
        end
 
        function [31:0] SliceData;
                input [95:0] RegData;
                input [7:0]  RegWidth;
 
                case(RegWidth)
                        8'd65: SliceData = RegData[64:33];
                        8'd66: SliceData = RegData[65:34];
                        8'd67: SliceData = RegData[66:35];
                        8'd68: SliceData = RegData[67:36];
                        8'd69: SliceData = RegData[68:37];
                        8'd70: SliceData = RegData[69:38];
                        8'd71: SliceData = RegData[70:39];
                        8'd72: SliceData = RegData[71:40];
                        8'd73: SliceData = RegData[72:41];
                        8'd74: SliceData = RegData[73:42];
                        8'd75: SliceData = RegData[74:43];
                        8'd76: SliceData = RegData[75:44];
                        8'd77: SliceData = RegData[76:45];
                        8'd78: SliceData = RegData[77:46];
                        8'd79: SliceData = RegData[78:47];
                        8'd80: SliceData = RegData[79:48];
                        8'd81: SliceData = RegData[80:49];
                        8'd82: SliceData = RegData[81:50];
                        8'd83: SliceData = RegData[82:51];
                        8'd84: SliceData = RegData[83:52];
                        8'd85: SliceData = RegData[84:53];
                        8'd86: SliceData = RegData[85:54];
                        8'd87: SliceData = RegData[86:55];
                        8'd88: SliceData = RegData[87:56];
                        8'd89: SliceData = RegData[88:57];
                        8'd90: SliceData = RegData[89:58];
                        8'd91: SliceData = RegData[90:59];
                        8'd92: SliceData = RegData[91:60];
                        8'd93: SliceData = RegData[92:61];
                        8'd94: SliceData = RegData[93:62];
                        8'd95: SliceData = RegData[94:63];
                        8'd96: SliceData = RegData[95:64];
                        default: SliceData = 32'h00000000;
                endcase
        endfunction
 
        reg                     OutEnable;
        reg                     PreEnable;
 
        reg [31:0]              DataOut;
 
        always @(posedge clk or negedge rst) begin
                if(!rst) begin
                        OutEnable       <= 1'b0;
                        PreEnable       <= 1'b0;
                        DataOut         <= 32'h00000000;
                end else begin
                        OutEnable       <= RegWidth >64;
                        PreEnable       <= (UseBit == 1'b1 | UseByte == 1'b1 | UseWord == 1'b1);
                        DataOut         <= SliceData(RegData,RegWidth);
                end
        end
 
        assign DataOutEnable = (PreEnable == 1'b0)?OutEnable:1'b0;
 
endmodule
 
 
 

Line No.	Rev	Author	Line
1	3	hidemi	`//---------------------------------------------------------------------------`
2	5	hidemi	`// File Name : jpeg_regdata.v`
3			`// Module Name : jpeg_regdata`
4			`// Description : get Data`
5			`// Project : JPEG Decoder`
6			`// Belong to :`
7			`// Author : H.Ishihara`
8			`// E-Mail : hidemi@sweetcafe.jp`
9			`// HomePage : http://www.sweetcafe.jp/`
10			`// Date : 2007/04/11`
11			`// Rev. : 1.03`
12	3	hidemi	`//---------------------------------------------------------------------------`
13	5	hidemi	`// Rev. Date Description`
14	3	hidemi	`//---------------------------------------------------------------------------`
15			`// 1.01 2006/10/01 1st Release`
16			`// 1.02 2006/10/04 Remove a RegEnd register.`
17	5	hidemi	`// When reset, clear on OutEnable,PreEnable,DataOut registers.`
18			`// Remove some comments.`
19			`// 1.03 2007/04/11 Don't OutEnable, ImageEnable == 1 and DataOut == 0xFFD9XXXX`
20			`// Stop ReadEnable with DataEnd(after 0xFFD9 of ImageData)`
21	3	hidemi	`//---------------------------------------------------------------------------`
22			`// $Id:`
23			`//---------------------------------------------------------------------------`
24			`timescale 1ps / 1ps
25	5	hidemi
26			`module jpeg_regdata(`
27			`rst,`
28			`clk,`
29	3	hidemi
30	5	hidemi	`// Read Data`
31			`DataIn, //`
32			`DataInEnable, // Data Enable`
33			`DataInRead, // Data Read`
34	3	hidemi
35	5	hidemi	`// DataOut`
36			`DataOut, // Data Out`
37			`DataOutEnable, // Data Out Enable`
38	3	hidemi
39	5	hidemi	`//`
40			`ImageEnable,`
41			`ProcessIdle,`
42
43			`// UseData`
44			`UseBit, // Used data bit`
45			`UseWidth, // Used data bit width`
46			`UseByte, // Used data byte`
47			`UseWord // Used data word`
48			`);`
49	3	hidemi
50	5	hidemi	`input rst;`
51			`input clk;`
52	3	hidemi
53	5	hidemi	`input [31:0] DataIn;`
54			`input DataInEnable;`
55			`output DataInRead;`
56	3	hidemi
57	5	hidemi	`output [31:0] DataOut;`
58			`output DataOutEnable;`
59	3	hidemi
60	5	hidemi	`input ImageEnable;`
61			`input ProcessIdle;`
62
63			`input UseBit;`
64			`input [6:0] UseWidth;`
65			`input UseByte;`
66			`input UseWord;`
67	3	hidemi
68	5	hidemi	`wire RegValid;`
69			`reg [95:0] RegData;`
70			`reg [7:0] RegWidth;`
71	3	hidemi
72	5	hidemi	`reg DataEnd;`
73	3	hidemi
74	5	hidemi	`assign RegValid = RegWidth > 64;`
75			`assign DataInRead = RegValid == 1'b0 & DataInEnable == 1'b1;`
76
77			`always @(posedge clk or negedge rst) begin`
78			`if(!rst) begin`
79			`RegData <= 96'd0;`
80			`RegWidth <= 8'h00;`
81			`end else begin`
82			`if(RegValid == 1'b0 & (DataInEnable == 1'b1 \| DataEnd == 1'b1)) begin`
83			`if(ImageEnable == 1'b1) begin`
84			`if(RegData[39: 8] == 32'hFF00FF00) begin`
85			`RegWidth <= RegWidth + 16;`
86			`RegData[95:64] <= {8'h00,RegData[71:48]};`
87			`RegData[63:32] <= {RegData[47:40],16'hFFFF,RegData[7:0]};`
88			`end else if(RegData[39:24] == 16'hFF00 &`
89			`RegData[15: 0] == 16'hFF00) begin`
90			`RegWidth <= RegWidth + 16;`
91			`RegData[95:64] <= {8'h00,RegData[71:48]};`
92			`RegData[63:32] <= {RegData[47:40],8'hFF,RegData[23:16],8'hFF};`
93			`end else if(RegData[31: 0] == 32'hFF00FF00) begin`
94			`RegWidth <= RegWidth + 16;`
95			`RegData[95:64] <= {16'h0000,RegData[71:56]};`
96			`RegData[63:32] <= {RegData[55:40],16'hFFFF};`
97			`end else if(RegData[39:24] == 16'hFF00) begin`
98			`RegWidth <= RegWidth + 24;`
99			`RegData[95:64] <= {RegData[71:40]};`
100			`RegData[63:32] <= {8'hFF,RegData[23:0]};`
101			`end else if(RegData[31:16] == 16'hFF00) begin`
102			`RegWidth <= RegWidth + 24;`
103			`RegData[95:64] <= {RegData[71:40]};`
104			`RegData[63:32] <= {RegData[39:32],8'hFF,RegData[15:0]};`
105			`end else if(RegData[23: 8] == 16'hFF00) begin`
106			`RegWidth <= RegWidth + 24;`
107			`RegData[95:64] <= {RegData[71:40]};`
108			`RegData[63:32] <= {RegData[39:32],RegData[31:24],8'hFF,RegData[7:0]};`
109			`end else if(RegData[15: 0] == 16'hFF00) begin`
110			`RegWidth <= RegWidth + 24;`
111			`RegData[95:64] <= {RegData[71:40]};`
112			`RegData[63:32] <= {RegData[39:32],RegData[31:16],8'hFF};`
113			`end else begin`
114			`RegWidth <= RegWidth + 32;`
115			`RegData[95:64] <= RegData[63:32];`
116			`RegData[63:32] <= RegData[31:0];`
117			`end`
118			`end else begin`
119			`RegWidth <= RegWidth + 32;`
120			`RegData[95:64] <= RegData[63:32];`
121			`RegData[63:32] <= RegData[31:0];`
122			`end`
123			`RegData[31: 0] <= {DataIn[7:0],DataIn[15:8],DataIn[23:16],DataIn[31:24]};`
124			`end else if(UseBit == 1'b1) begin`
125			`RegWidth <= RegWidth - UseWidth;`
126			`end else if(UseByte == 1'b1) begin`
127			`RegWidth <= RegWidth - 8;`
128			`end else if(UseWord == 1'b1) begin`
129			`RegWidth <= RegWidth - 16;`
130			`end`
131			`end`
132			`end`
133	3	hidemi
134	5	hidemi	`always @(posedge clk or negedge rst) begin`
135			`if(!rst) begin`
136			`DataEnd <= 1'b0;`
137			`end else begin`
138			`if(ProcessIdle) begin`
139			`DataEnd <= 1'b0;`
140			`end else if(ImageEnable == 1'b1 & (RegData[39:24] == 16'hFFD9 \| RegData[31:16] == 16'hFFD9 \| RegData[23: 8] == 16'hFFD9 \| RegData[15: 0] == 16'hFFD9)) begin`
141			`DataEnd <= 1'b1;`
142			`end`
143			`end`
144			`end`
145	3	hidemi
146	5	hidemi	`function [31:0] SliceData;`
147			`input [95:0] RegData;`
148			`input [7:0] RegWidth;`
149	3	hidemi
150	5	hidemi	`case(RegWidth)`
151			`8'd65: SliceData = RegData[64:33];`
152			`8'd66: SliceData = RegData[65:34];`
153			`8'd67: SliceData = RegData[66:35];`
154			`8'd68: SliceData = RegData[67:36];`
155			`8'd69: SliceData = RegData[68:37];`
156			`8'd70: SliceData = RegData[69:38];`
157			`8'd71: SliceData = RegData[70:39];`
158			`8'd72: SliceData = RegData[71:40];`
159			`8'd73: SliceData = RegData[72:41];`
160			`8'd74: SliceData = RegData[73:42];`
161			`8'd75: SliceData = RegData[74:43];`
162			`8'd76: SliceData = RegData[75:44];`
163			`8'd77: SliceData = RegData[76:45];`
164			`8'd78: SliceData = RegData[77:46];`
165			`8'd79: SliceData = RegData[78:47];`
166			`8'd80: SliceData = RegData[79:48];`
167			`8'd81: SliceData = RegData[80:49];`
168			`8'd82: SliceData = RegData[81:50];`
169			`8'd83: SliceData = RegData[82:51];`
170			`8'd84: SliceData = RegData[83:52];`
171			`8'd85: SliceData = RegData[84:53];`
172			`8'd86: SliceData = RegData[85:54];`
173			`8'd87: SliceData = RegData[86:55];`
174			`8'd88: SliceData = RegData[87:56];`
175			`8'd89: SliceData = RegData[88:57];`
176			`8'd90: SliceData = RegData[89:58];`
177			`8'd91: SliceData = RegData[90:59];`
178			`8'd92: SliceData = RegData[91:60];`
179			`8'd93: SliceData = RegData[92:61];`
180			`8'd94: SliceData = RegData[93:62];`
181			`8'd95: SliceData = RegData[94:63];`
182			`8'd96: SliceData = RegData[95:64];`
183			`default: SliceData = 32'h00000000;`
184			`endcase`
185			`endfunction`
186	3	hidemi
187	5	hidemi	`reg OutEnable;`
188			`reg PreEnable;`
189
190			`reg [31:0] DataOut;`
191	3	hidemi
192	5	hidemi	`always @(posedge clk or negedge rst) begin`
193			`if(!rst) begin`
194			`OutEnable <= 1'b0;`
195			`PreEnable <= 1'b0;`
196			`DataOut <= 32'h00000000;`
197			`end else begin`
198			`OutEnable <= RegWidth >64;`
199			`PreEnable <= (UseBit == 1'b1 \| UseByte == 1'b1 \| UseWord == 1'b1);`
200			`DataOut <= SliceData(RegData,RegWidth);`
201			`end`
202			`end`
203	3	hidemi
204	5	hidemi	`assign DataOutEnable = (PreEnable == 1'b0)?OutEnable:1'b0;`
205
206			`endmodule`
207	3	hidemi
208
209

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[/] [djpeg/] [trunk/] [src/] [jpeg_regdata.v] - Blame information for rev 6