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[/] [djpeg/] [trunk/] [src/] [jpeg_ycbcr2rgb.v] - Blame information for rev 6

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//---------------------------------------------------------------------------
// File Name   : jpeg_ycbcr2rgb.v
// Module Name : jpeg_ycbcr2rgb
// Description : YCbCr2RGB
// Project     : JPEG Decoder
// Belong to   : 
// Author      : H.Ishihara
// E-Mail      : hidemi@sweetcafe.jp
// HomePage    : http://www.sweetcafe.jp/
// Date        : 2006/10/01
// Rev.        : 1.1
//---------------------------------------------------------------------------
// Rev. Date       Description
//---------------------------------------------------------------------------
// 1.01 2006/10/01 1st Release
//---------------------------------------------------------------------------
// $Id: 
//---------------------------------------------------------------------------
`timescale 1ps / 1ps
 
//----------------------------------------------------------------------------
// JPEG YCbCr -> RGB Conveter
//----------------------------------------------------------------------------
module jpeg_ycbcbr2rgb
  (
   rst,
   clk,
 
   InEnable,
   InBlockX,
   InBlockY,
   InIdle,
   InBank,
   InAddress,
   InY,
   InCb,
   InCr,
 
   OutEnable,
   OutPixelX,
   OutPixelY,
   OutR,
   OutG,
   OutB
   );
 
   input          clk;
   input          rst;
 
   input          InEnable;
   input [11:0]   InBlockX;
   input [11:0]   InBlockY;
   output         InIdle;
   output         InBank;
   output [7:0]   InAddress;
   input [8:0]    InY;
   input [8:0]    InCb;
   input [8:0]    InCr;
 
   output         OutEnable;
   output [15:0]  OutPixelX;
   output [15:0]  OutPixelY;
   output [7:0]   OutR;
   output [7:0]   OutG;
   output [7:0]   OutB;
 
   reg            RunActive;
   reg [7:0]      RunCount;
   reg [11:0]     RunBlockX;
   reg [11:0]     RunBlockY;
   reg            RunBank;
 
   always @(posedge clk or negedge rst) begin
      if(!rst) begin
         RunActive <= 1'b0;
         RunBank   <= 1'b0;
         RunCount  <= 8'h00;
         RunBlockX <= 12'h000;
         RunBlockY <= 12'h000;
      end else begin
         if(RunActive == 1'b0) begin
            if(InEnable == 1'b1) begin
               RunActive <= 1'b1;
               RunBlockX <= InBlockX;
               RunBlockY <= InBlockY;
            end
            RunCount  <= 8'h00;
         end else begin
            if(RunCount == 8'hFF) begin
               RunActive <= 1'b0;
               RunBank   <= ~RunBank;
               RunCount  <= 8'h00;
            end else begin
               RunCount <= RunCount +1;
            end
         end // else: !if(RunActive == 1'b0)
      end // else: !if(!rst)
   end // always @ (posedge clk or negedge rst)
 
   assign InIdle    = RunActive == 1'b0 | (RunActive == 1'b1 & RunCount == 8'hFF);
   assign InAddress = RunCount;
   assign InBank    = RunBank;
 
   reg          PreEnable;
   reg [15:0]   PreCountX;
   reg [15:0]   PreCountY;
   reg          Phase0Enable;
   reg [15:0]   Phase0CountX;
   reg [15:0]   Phase0CountY;
   reg          Phase1Enable;
   reg [15:0]   Phase1CountX;
   reg [15:0]   Phase1CountY;
   reg          Phase2Enable;
   reg [15:0]   Phase2CountX;
   reg [15:0]   Phase2CountY;
   reg          Phase3Enable;
   reg [15:0]   Phase3CountX;
   reg [15:0]   Phase3CountY;
 
   reg signed [31:0] rgb00r;
   reg signed [31:0] r00r;
   reg signed [31:0] g00r;
   reg signed [31:0] g01r;
   reg signed [31:0] b00r;
   reg signed [31:0] r10r;
   reg signed [31:0] g10r;
   reg signed [31:0] g11r;
   reg signed [31:0] b10r;
   reg signed [31:0] r20r;
   reg signed [31:0] g20r;
   reg signed [31:0] b20r;
 
   wire signed [8:0] DataY;
   wire signed [8:0] DataCb;
   wire signed [8:0] DataCr;
 
   reg signed [8:0]  Phase0Y;
   reg signed [8:0]  Phase0Cb;
   reg signed [8:0]  Phase0Cr;
 
   wire signed [19:0] C_RR = 20'h59BA5; // R_Cr: 1.402   * 0x4000
   wire signed [19:0] C_GB = 20'h16066; // G_Cb: 0.34414 * 0x4000
   wire signed [19:0] C_GR = 20'h2DB47; // G_Cr: 0.71414 * 0x4000
   wire signed [19:0] C_BB = 20'h71687; // B_Cb: 1.772   * 0x4000
 
   assign             DataY  = InY;
   assign             DataCb = InCb;
   assign             DataCr = InCr;
 
   reg signed [8:0]   Phase1Y,Phase1Cb,Phase1Cr;
   reg signed [8:0]   Phase2Y,Phase2Cb,Phase2Cr;
   reg signed [8:0]   Phase3Y,Phase3Cb,Phase3Cr;
 
   always @(posedge clk or negedge rst) begin
      if(!rst) begin
         rgb00r <= 0;
         r00r   <= 0;
         g00r   <= 0;
         g01r   <= 0;
         b00r   <= 0;
 
         r10r   <= 0;
         g10r   <= 0;
         g11r   <= 0;
         b10r   <= 0;
 
         r20r   <= 0;
         g20r   <= 0;
         b20r   <= 0;
 
         Phase0Enable <= 1'b0;
         Phase0CountX <= 16'h0000;
         Phase0CountY <= 16'h0000;
         Phase1Enable <= 1'b0;
         Phase1CountX <= 16'h0000;
         Phase1CountY <= 16'h0000;
         Phase2Enable <= 1'b0;
         Phase2CountX <= 16'h0000;
         Phase2CountY <= 16'h0000;
         Phase3Enable <= 1'b0;
         Phase3CountX <= 16'h0000;
         Phase3CountY <= 16'h0000;
      end else begin // if (!rst)
         // Pre
         PreEnable <= RunActive;
         PreCountX <= {RunBlockX,RunCount[3:0]};
         PreCountY <= {RunBlockY,RunCount[7:4]};
         // Phase0
         Phase0Enable <= PreEnable;
         Phase0CountX <= PreCountX;
         Phase0CountY <= PreCountY;
         Phase0Y      <= DataY;
         Phase0Cb     <= DataCb;
         Phase0Cr     <= DataCr;
         // Phase1
         Phase1Enable <= Phase0Enable;
         Phase1CountX <= Phase0CountX;
         Phase1CountY <= Phase0CountY;
         rgb00r <= 32'h02000000 + {Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8:0],18'h0000};
         r00r   <= Phase0Cr * C_RR;
         g00r   <= Phase0Cb * C_GB;
         g01r   <= Phase0Cr * C_GR;
         b00r   <= Phase0Cb * C_BB;
 
         Phase1Y  <= Phase0Y;
         Phase1Cb <= Phase0Cb;
         Phase1Cr <= Phase0Cr;
 
 
         // Phase2
         Phase2Enable <= Phase1Enable;
         Phase2CountX <= Phase1CountX;
         Phase2CountY <= Phase1CountY;
         r10r   <= rgb00r + r00r;
         g10r   <= rgb00r - g00r;
         g11r   <= g01r;
         b10r   <= rgb00r + b00r;
 
         Phase2Y  <= Phase1Y;
         Phase2Cb <= Phase1Cb;
         Phase2Cr <= Phase1Cr;
 
         // Phase3
         Phase3Enable <= Phase2Enable;
         Phase3CountX <= Phase2CountX;
         Phase3CountY <= Phase2CountY;
         r20r   <= r10r;
         g20r   <= g10r - g11r;
         b20r   <= b10r;
 
         Phase3Y  <= Phase2Y;
         Phase3Cb <= Phase2Cb;
         Phase3Cr <= Phase2Cr;
 
      end // else: !if(!rst)
   end // always @ (posedge clk or negedge rst)
 
   assign OutEnable = Phase3Enable;
   assign OutPixelX = Phase3CountX;
   assign OutPixelY = Phase3CountY;
   assign OutR      = (r20r[31])?8'h00:(r20r[26])?8'hFF:r20r[25:18];
   assign OutG      = (g20r[31])?8'h00:(g20r[26])?8'hFF:g20r[25:18];
   assign OutB      = (b20r[31])?8'h00:(b20r[26])?8'hFF:b20r[25:18];
 
endmodule // jpeg_ycbcbr2rgb

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Subversion Repositories djpeg

[/] [djpeg/] [trunk/] [src/] [jpeg_ycbcr2rgb.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	3	hidemi	`//---------------------------------------------------------------------------`
2			`// File Name : jpeg_ycbcr2rgb.v`
3			`// Module Name : jpeg_ycbcr2rgb`
4			`// Description : YCbCr2RGB`
5			`// Project : JPEG Decoder`
6			`// Belong to :`
7			`// Author : H.Ishihara`
8			`// E-Mail : hidemi@sweetcafe.jp`
9			`// HomePage : http://www.sweetcafe.jp/`
10			`// Date : 2006/10/01`
11			`// Rev. : 1.1`
12			`//---------------------------------------------------------------------------`
13			`// Rev. Date Description`
14			`//---------------------------------------------------------------------------`
15			`// 1.01 2006/10/01 1st Release`
16			`//---------------------------------------------------------------------------`
17			`// $Id:`
18			`//---------------------------------------------------------------------------`
19			`timescale 1ps / 1ps
20
21			`//----------------------------------------------------------------------------`
22			`// JPEG YCbCr -> RGB Conveter`
23			`//----------------------------------------------------------------------------`
24			`module jpeg_ycbcbr2rgb`
25			`(`
26			`rst,`
27			`clk,`
28
29			`InEnable,`
30			`InBlockX,`
31			`InBlockY,`
32			`InIdle,`
33			`InBank,`
34			`InAddress,`
35			`InY,`
36			`InCb,`
37			`InCr,`
38
39			`OutEnable,`
40			`OutPixelX,`
41			`OutPixelY,`
42			`OutR,`
43			`OutG,`
44			`OutB`
45			`);`
46
47			`input clk;`
48			`input rst;`
49
50			`input InEnable;`
51			`input [11:0] InBlockX;`
52			`input [11:0] InBlockY;`
53			`output InIdle;`
54			`output InBank;`
55			`output [7:0] InAddress;`
56			`input [8:0] InY;`
57			`input [8:0] InCb;`
58			`input [8:0] InCr;`
59
60			`output OutEnable;`
61			`output [15:0] OutPixelX;`
62			`output [15:0] OutPixelY;`
63			`output [7:0] OutR;`
64			`output [7:0] OutG;`
65			`output [7:0] OutB;`
66
67			`reg RunActive;`
68			`reg [7:0] RunCount;`
69			`reg [11:0] RunBlockX;`
70			`reg [11:0] RunBlockY;`
71			`reg RunBank;`
72
73			`always @(posedge clk or negedge rst) begin`
74			`if(!rst) begin`
75			`RunActive <= 1'b0;`
76			`RunBank <= 1'b0;`
77			`RunCount <= 8'h00;`
78			`RunBlockX <= 12'h000;`
79			`RunBlockY <= 12'h000;`
80			`end else begin`
81			`if(RunActive == 1'b0) begin`
82			`if(InEnable == 1'b1) begin`
83			`RunActive <= 1'b1;`
84			`RunBlockX <= InBlockX;`
85			`RunBlockY <= InBlockY;`
86			`end`
87			`RunCount <= 8'h00;`
88			`end else begin`
89			`if(RunCount == 8'hFF) begin`
90			`RunActive <= 1'b0;`
91			`RunBank <= ~RunBank;`
92			`RunCount <= 8'h00;`
93			`end else begin`
94			`RunCount <= RunCount +1;`
95			`end`
96			`end // else: !if(RunActive == 1'b0)`
97			`end // else: !if(!rst)`
98			`end // always @ (posedge clk or negedge rst)`
99
100			`assign InIdle = RunActive == 1'b0 \| (RunActive == 1'b1 & RunCount == 8'hFF);`
101			`assign InAddress = RunCount;`
102			`assign InBank = RunBank;`
103
104			`reg PreEnable;`
105			`reg [15:0] PreCountX;`
106			`reg [15:0] PreCountY;`
107			`reg Phase0Enable;`
108			`reg [15:0] Phase0CountX;`
109			`reg [15:0] Phase0CountY;`
110			`reg Phase1Enable;`
111			`reg [15:0] Phase1CountX;`
112			`reg [15:0] Phase1CountY;`
113			`reg Phase2Enable;`
114			`reg [15:0] Phase2CountX;`
115			`reg [15:0] Phase2CountY;`
116			`reg Phase3Enable;`
117			`reg [15:0] Phase3CountX;`
118			`reg [15:0] Phase3CountY;`
119
120			`reg signed [31:0] rgb00r;`
121			`reg signed [31:0] r00r;`
122			`reg signed [31:0] g00r;`
123			`reg signed [31:0] g01r;`
124			`reg signed [31:0] b00r;`
125			`reg signed [31:0] r10r;`
126			`reg signed [31:0] g10r;`
127			`reg signed [31:0] g11r;`
128			`reg signed [31:0] b10r;`
129			`reg signed [31:0] r20r;`
130			`reg signed [31:0] g20r;`
131			`reg signed [31:0] b20r;`
132
133			`wire signed [8:0] DataY;`
134			`wire signed [8:0] DataCb;`
135			`wire signed [8:0] DataCr;`
136
137			`reg signed [8:0] Phase0Y;`
138			`reg signed [8:0] Phase0Cb;`
139			`reg signed [8:0] Phase0Cr;`
140
141			`wire signed [19:0] C_RR = 20'h59BA5; // R_Cr: 1.402 * 0x4000`
142			`wire signed [19:0] C_GB = 20'h16066; // G_Cb: 0.34414 * 0x4000`
143			`wire signed [19:0] C_GR = 20'h2DB47; // G_Cr: 0.71414 * 0x4000`
144			`wire signed [19:0] C_BB = 20'h71687; // B_Cb: 1.772 * 0x4000`
145
146			`assign DataY = InY;`
147			`assign DataCb = InCb;`
148			`assign DataCr = InCr;`
149
150			`reg signed [8:0] Phase1Y,Phase1Cb,Phase1Cr;`
151			`reg signed [8:0] Phase2Y,Phase2Cb,Phase2Cr;`
152			`reg signed [8:0] Phase3Y,Phase3Cb,Phase3Cr;`
153
154			`always @(posedge clk or negedge rst) begin`
155			`if(!rst) begin`
156			`rgb00r <= 0;`
157			`r00r <= 0;`
158			`g00r <= 0;`
159			`g01r <= 0;`
160			`b00r <= 0;`
161
162			`r10r <= 0;`
163			`g10r <= 0;`
164			`g11r <= 0;`
165			`b10r <= 0;`
166
167			`r20r <= 0;`
168			`g20r <= 0;`
169			`b20r <= 0;`
170
171			`Phase0Enable <= 1'b0;`
172			`Phase0CountX <= 16'h0000;`
173			`Phase0CountY <= 16'h0000;`
174			`Phase1Enable <= 1'b0;`
175			`Phase1CountX <= 16'h0000;`
176			`Phase1CountY <= 16'h0000;`
177			`Phase2Enable <= 1'b0;`
178			`Phase2CountX <= 16'h0000;`
179			`Phase2CountY <= 16'h0000;`
180			`Phase3Enable <= 1'b0;`
181			`Phase3CountX <= 16'h0000;`
182			`Phase3CountY <= 16'h0000;`
183			`end else begin // if (!rst)`
184			`// Pre`
185			`PreEnable <= RunActive;`
186			`PreCountX <= {RunBlockX,RunCount[3:0]};`
187			`PreCountY <= {RunBlockY,RunCount[7:4]};`
188			`// Phase0`
189			`Phase0Enable <= PreEnable;`
190			`Phase0CountX <= PreCountX;`
191			`Phase0CountY <= PreCountY;`
192			`Phase0Y <= DataY;`
193			`Phase0Cb <= DataCb;`
194			`Phase0Cr <= DataCr;`
195			`// Phase1`
196			`Phase1Enable <= Phase0Enable;`
197			`Phase1CountX <= Phase0CountX;`
198			`Phase1CountY <= Phase0CountY;`
199			`rgb00r <= 32'h02000000 + {Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8:0],18'h0000};`
200			`r00r <= Phase0Cr * C_RR;`
201			`g00r <= Phase0Cb * C_GB;`
202			`g01r <= Phase0Cr * C_GR;`
203			`b00r <= Phase0Cb * C_BB;`
204
205			`Phase1Y <= Phase0Y;`
206			`Phase1Cb <= Phase0Cb;`
207			`Phase1Cr <= Phase0Cr;`
208
209
210			`// Phase2`
211			`Phase2Enable <= Phase1Enable;`
212			`Phase2CountX <= Phase1CountX;`
213			`Phase2CountY <= Phase1CountY;`
214			`r10r <= rgb00r + r00r;`
215			`g10r <= rgb00r - g00r;`
216			`g11r <= g01r;`
217			`b10r <= rgb00r + b00r;`
218
219			`Phase2Y <= Phase1Y;`
220			`Phase2Cb <= Phase1Cb;`
221			`Phase2Cr <= Phase1Cr;`
222
223			`// Phase3`
224			`Phase3Enable <= Phase2Enable;`
225			`Phase3CountX <= Phase2CountX;`
226			`Phase3CountY <= Phase2CountY;`
227			`r20r <= r10r;`
228			`g20r <= g10r - g11r;`
229			`b20r <= b10r;`
230
231			`Phase3Y <= Phase2Y;`
232			`Phase3Cb <= Phase2Cb;`
233			`Phase3Cr <= Phase2Cr;`
234
235			`end // else: !if(!rst)`
236			`end // always @ (posedge clk or negedge rst)`
237
238			`assign OutEnable = Phase3Enable;`
239			`assign OutPixelX = Phase3CountX;`
240			`assign OutPixelY = Phase3CountY;`
241			`assign OutR = (r20r[31])?8'h00:(r20r[26])?8'hFF:r20r[25:18];`
242			`assign OutG = (g20r[31])?8'h00:(g20r[26])?8'hFF:g20r[25:18];`
243			`assign OutB = (b20r[31])?8'h00:(b20r[26])?8'hFF:b20r[25:18];`
244
245			`endmodule // jpeg_ycbcbr2rgb`