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[/] [djpeg/] [trunk/] [src/] [jpeg_ziguzagu.v] - Blame information for rev 9

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1 3 hidemi 
//---------------------------------------------------------------------------
2 9 hidemi 
// File Name    : jpeg_ziguzagu.v
3 
// Module Name  : jpeg_ziguzagu
4 
// Description  : Ziguzagu
5 
// Project      : JPEG Decoder
6 
// Belong to    :
7 
// Author       : H.Ishihara
8 
// E-Mail       : hidemi@sweetcafe.jp
9 
// HomePage     : http://www.sweetcafe.jp/
10 
// Date         : 2008/03/05
11 
// Rev.         : 2.00
12 3 hidemi 
//---------------------------------------------------------------------------
13 
// Rev. Date       Description
14 
//---------------------------------------------------------------------------
15 
// 1.01 2006/10/01 1st Release
16 9 hidemi 
// 2.00 2008/03/05 Replace to Memory from D-FFs.
17 3 hidemi 
//---------------------------------------------------------------------------
18 
`timescale 1ps / 1ps
19 
 
20 9 hidemi 
module jpeg_ziguzagu(
21 
    rst,
22 
    clk,
23 3 hidemi 
 
24 9 hidemi 
    DataInit,
25 
    HuffmanEndEnable,
26 3 hidemi 
 
27 9 hidemi 
    DataInEnable,
28 
    DataInAddress,
29 
    DataInColor,
30 
    DataInIdle,
31 
    DataIn,
32 3 hidemi 
 
33 9 hidemi 
    DataOutEnable,
34 
    DataOutRead,
35 
    DataOutAddress,
36 
    DataOutColor,
37 
    DataOutA,
38 
    DataOutB
39 
);
40 
 
41 
    input           clk;
42 
    input           rst;
43 3 hidemi 
 
44 9 hidemi 
    input           DataInit;
45 
    input           HuffmanEndEnable;
46 
 
47 
    input           DataInEnable;
48 
    input [5:0]     DataInAddress;
49 
    input [2:0]     DataInColor;
50 
    output          DataInIdle;
51 
    input [15:0]    DataIn;
52 
 
53 
    output          DataOutEnable;
54 
    input           DataOutRead;
55 
    input [4:0]     DataOutAddress;
56 
    output [2:0]    DataOutColor;
57 
    output [15:0]   DataOutA;
58 
    output [15:0]   DataOutB;
59 3 hidemi 
 
60 9 hidemi 
    // State Machine Parameter
61 
    parameter S_IDLE    = 2'd0;
62 
    parameter S_VALID   = 2'd1;
63 
    parameter S_FULL    = 2'd2;
64 
    parameter S_INIT    = 2'd3;
65 
 
66 
    reg [1:0]   State;
67 
    reg [1:0]   BankCount;
68 
 
69 
    reg [2:0]   BankColor [0:3];
70 
    reg [1:0]   WriteBank;
71 
    reg [1:0]   ReadBank;
72 3 hidemi 
 
73 9 hidemi 
    wire [5:0]  WriteQuery;
74 3 hidemi 
 
75 9 hidemi 
    // State Machine
76 
    always @(posedge clk or negedge rst) begin
77 
        if(!rst) begin
78 
            State <= S_IDLE;
79 
            BankCount <= 2'd0;
80 
        end else begin
81 
            case(State)
82 
                S_IDLE: begin
83 
                    if(DataInit) begin
84 
                        State       <= S_INIT;
85 
                    end else if(HuffmanEndEnable) begin
86 
                        State       <= S_VALID;
87 
                        BankCount   <= 2'd0;
88 
                    end
89 
                end
90 
                S_VALID: begin
91 
                    if(HuffmanEndEnable && !(DataOutRead && (DataOutAddress == 5'd31))) begin
92 
                        if(BankCount == 2'd2) begin
93 
                            State       <= S_FULL;
94 
                            BankCount   <= 2'd3;
95 
                        end else begin
96 
                            BankCount <= BankCount + 2'd1;
97 
                        end
98 
                    end else if(!HuffmanEndEnable && (DataOutRead && (DataOutAddress == 5'd31))) begin
99 
                        if(BankCount == 2'd0) begin
100 
                            State       <= S_IDLE;
101 
                            BankCount   <= 2'd0;
102 
                        end else begin
103 
                            BankCount   <= BankCount - 2'd1;
104 
                        end
105 
                    end
106 
                end
107 
                S_FULL: begin
108 
                    if(DataOutRead && (DataOutAddress == 5'd31)) begin
109 
                        State       <= S_VALID;
110 
                        BankCount   <= 2'd2;
111 
                    end
112 
                end
113 
                S_INIT: begin
114 
                    State <= S_IDLE;
115 
                end
116 
            endcase
117 
        end
118 
    end
119 3 hidemi 
 
120 9 hidemi 
    // Color
121 
    always @(posedge clk or negedge rst) begin
122 
        if(!rst) begin
123 
            BankColor[0]    <= 3'd0;
124 
            BankColor[1]    <= 3'd0;
125 
            BankColor[2]    <= 3'd0;
126 
            BankColor[3]    <= 3'd0;
127 
        end else begin
128 
            if(HuffmanEndEnable) BankColor[WriteBank] <= DataInColor;
129 
        end
130 
    end
131 
 
132 
    // Bank
133 
    always @(posedge clk or negedge rst) begin
134 
        if(!rst) begin
135 
            WriteBank   <= 2'd0;
136 
            ReadBank    <= 2'd0;
137 
        end else begin
138 
            // Write Bank
139 
            if(State == S_INIT) begin
140 
                WriteBank <= 2'd0;
141 
            end else if(HuffmanEndEnable) begin
142 
                WriteBank <= WriteBank + 2'd1;
143 3 hidemi 
            end
144 9 hidemi 
            // Read Bank
145 
            if(State == S_INIT) begin
146 
                ReadBank <= 2'd0;
147 
            end else if(DataOutRead && (DataOutAddress == 5'd31)) begin
148 
                ReadBank <= ReadBank + 2'd1;
149 3 hidemi 
            end
150 9 hidemi 
        end
151 
    end
152 
 
153 
    // Make a Write Address
154 
    function [5:0] F_WriteQuery;
155 
        input [5:0] Count;
156 
        case(Count)
157 
            6'd0:  F_WriteQuery = {1'b0, 5'd0 };
158 
            6'd1:  F_WriteQuery = {1'b0, 5'd2 };
159 
            6'd2:  F_WriteQuery = {1'b0, 5'd4 };
160 
            6'd3:  F_WriteQuery = {1'b0, 5'd8 };
161 
            6'd4:  F_WriteQuery = {1'b0, 5'd6 };
162 
            6'd5:  F_WriteQuery = {1'b0, 5'd1 };
163 
            6'd6:  F_WriteQuery = {1'b1, 5'd3 };
164 
            6'd7:  F_WriteQuery = {1'b0, 5'd5 };
165 
            6'd8:  F_WriteQuery = {1'b0, 5'd10};
166 
            6'd9:  F_WriteQuery = {1'b0, 5'd12};
167 
            6'd10: F_WriteQuery = {1'b0, 5'd16};
168 
            6'd11: F_WriteQuery = {1'b0, 5'd14};
169 
            6'd12: F_WriteQuery = {1'b0, 5'd9 };
170 
            6'd13: F_WriteQuery = {1'b1, 5'd7 };
171 
            6'd14: F_WriteQuery = {1'b1, 5'd0 };
172 
            6'd15: F_WriteQuery = {1'b0, 5'd3 };
173 
            6'd16: F_WriteQuery = {1'b1, 5'd4 };
174 
            6'd17: F_WriteQuery = {1'b1, 5'd11};
175 
            6'd18: F_WriteQuery = {1'b0, 5'd13};
176 
            6'd19: F_WriteQuery = {1'b0, 5'd18};
177 
            6'd20: F_WriteQuery = {1'b0, 5'd20};
178 
            6'd21: F_WriteQuery = {1'b0, 5'd24};
179 
            6'd22: F_WriteQuery = {1'b0, 5'd22};
180 
            6'd23: F_WriteQuery = {1'b0, 5'd17};
181 
            6'd24: F_WriteQuery = {1'b1, 5'd15};
182 
            6'd25: F_WriteQuery = {1'b1, 5'd8 };
183 
            6'd26: F_WriteQuery = {1'b0, 5'd7 };
184 
            6'd27: F_WriteQuery = {1'b1, 5'd1 };
185 
            6'd28: F_WriteQuery = {1'b1, 5'd2 };
186 
            6'd29: F_WriteQuery = {1'b1, 5'd5 };
187 
            6'd30: F_WriteQuery = {1'b0, 5'd11};
188 
            6'd31: F_WriteQuery = {1'b1, 5'd12};
189 
            6'd32: F_WriteQuery = {1'b1, 5'd19};
190 
            6'd33: F_WriteQuery = {1'b0, 5'd21};
191 
            6'd34: F_WriteQuery = {1'b0, 5'd26};
192 
            6'd35: F_WriteQuery = {1'b0, 5'd28};
193 
            6'd36: F_WriteQuery = {1'b0, 5'd30};
194 
            6'd37: F_WriteQuery = {1'b0, 5'd25};
195 
            6'd38: F_WriteQuery = {1'b1, 5'd23};
196 
            6'd39: F_WriteQuery = {1'b1, 5'd16};
197 
            6'd40: F_WriteQuery = {1'b0, 5'd15};
198 
            6'd41: F_WriteQuery = {1'b1, 5'd9 };
199 
            6'd42: F_WriteQuery = {1'b1, 5'd6 };
200 
            6'd43: F_WriteQuery = {1'b1, 5'd10};
201 
            6'd44: F_WriteQuery = {1'b1, 5'd13};
202 
            6'd45: F_WriteQuery = {1'b0, 5'd19};
203 
            6'd46: F_WriteQuery = {1'b1, 5'd20};
204 
            6'd47: F_WriteQuery = {1'b1, 5'd27};
205 
            6'd48: F_WriteQuery = {1'b0, 5'd29};
206 
            6'd49: F_WriteQuery = {1'b1, 5'd31};
207 
            6'd50: F_WriteQuery = {1'b1, 5'd24};
208 
            6'd51: F_WriteQuery = {1'b0, 5'd23};
209 
            6'd52: F_WriteQuery = {1'b1, 5'd17};
210 
            6'd53: F_WriteQuery = {1'b1, 5'd14};
211 
            6'd54: F_WriteQuery = {1'b1, 5'd18};
212 
            6'd55: F_WriteQuery = {1'b1, 5'd21};
213 
            6'd56: F_WriteQuery = {1'b0, 5'd27};
214 
            6'd57: F_WriteQuery = {1'b1, 5'd28};
215 
            6'd58: F_WriteQuery = {1'b0, 5'd31};
216 
            6'd59: F_WriteQuery = {1'b1, 5'd25};
217 
            6'd60: F_WriteQuery = {1'b1, 5'd22};
218 
            6'd61: F_WriteQuery = {1'b1, 5'd26};
219 
            6'd62: F_WriteQuery = {1'b1, 5'd29};
220 
            6'd63: F_WriteQuery = {1'b1, 5'd30};
221 
        endcase
222 
    endfunction
223 
 
224 
    assign WriteQuery = F_WriteQuery(DataInAddress);
225 
 
226 
    // RAM(16bit x 32word x 2Bank)
227 
    reg [15:0]  MemoryA  [0:127];
228 
    reg [15:0]  MemoryB  [0:127];
229 
 
230 
    wire [6:0]  WriteAddress;
231 
    wire        WriteEnableA, WriteEnableB;
232 
 
233 
    assign WriteEnableA = DataInEnable & ~WriteQuery[5];
234 
    assign WriteEnableB = DataInEnable &  WriteQuery[5];
235 
    assign WriteAddress = {WriteBank, WriteQuery[4:0]};
236 3 hidemi 
 
237 9 hidemi 
    // Port A(Write Only)
238 
    always @(posedge clk) begin
239 
        if(WriteEnableA) MemoryA[WriteAddress] <= DataIn;
240 
        if(WriteEnableB) MemoryB[WriteAddress] <= DataIn;
241 
    end
242 3 hidemi 
 
243 9 hidemi 
    reg [15:0]  RegMemoryA, RegMemoryB;
244 
 
245 
    // Port B(Read/Wirte)
246 
    always @(posedge clk) begin
247 
        RegMemoryA <= MemoryA[{ReadBank, DataOutAddress}];
248 
        RegMemoryB <= MemoryB[{ReadBank, DataOutAddress}];
249 
    end
250 
 
251 
    // Data Enable Register
252 
    reg [127:0] DataEnableA, DataEnableB;
253 
 
254 
    always @(posedge clk or negedge rst) begin
255 
        if(!rst) begin
256 
            DataEnableA <= 128'd0;
257 
            DataEnableB <= 128'd0;
258 
        end else begin
259 
            if(State == S_INIT) begin
260 
                DataEnableA <= 128'd0;
261 
                DataEnableB <= 128'd0;
262 
            end else begin
263 
                if(DataInEnable && (WriteBank == 2'd0)) begin
264 
                    if(WriteEnableA) begin
265 
                        if(WriteAddress[4:0] == 5'd0) begin
266 
                            DataEnableA[{2'd0, WriteAddress[4:0]}] <= 1'b1;
267 
                            DataEnableA[31:1] <= 31'd0;
268 
                            DataEnableB[31:0] <= 32'd0;
269 
                        end else begin
270 
                            DataEnableA[{2'd0, WriteAddress[4:0]}] <= 1'b1;
271 
                        end
272 
                    end else begin
273 
                        DataEnableB[{2'd0, WriteAddress[4:0]}] <= 1'b1;
274 
                    end
275 
                end
276 
                if(DataInEnable && (WriteBank == 2'd1)) begin
277 
                    if(WriteEnableA) begin
278 
                        if(WriteAddress[4:0] == 5'd0) begin
279 
                            DataEnableA[{2'd1, WriteAddress[4:0]}] <= 1'b1;
280 
                            DataEnableA[63:33] <= 31'd0;
281 
                            DataEnableB[63:32] <= 32'd0;
282 
                        end else begin
283 
                            DataEnableA[{2'd1, WriteAddress[4:0]}] <= 1'b1;
284 
                        end
285 
                    end else begin
286 
                        DataEnableB[{2'd1, WriteAddress[4:0]}] <= 1'b1;
287 
                    end
288 
                end
289 
                if(DataInEnable && (WriteBank == 2'd2)) begin
290 
                    if(WriteEnableA) begin
291 
                        if(WriteAddress[4:0] == 5'd0) begin
292 
                            DataEnableA[{2'd2, WriteAddress[4:0]}] <= 1'b1;
293 
                            DataEnableA[95:65] <= 31'd0;
294 
                            DataEnableB[95:64] <= 32'd0;
295 
                        end else begin
296 
                            DataEnableA[{2'd2, WriteAddress[4:0]}] <= 1'b1;
297 
                        end
298 
                    end else begin
299 
                        DataEnableB[{2'd2, WriteAddress[4:0]}] <= 1'b1;
300 
                    end
301 
                end
302 
                if(DataInEnable && (WriteBank == 2'd3)) begin
303 
                    if(WriteEnableA) begin
304 
                        if(WriteAddress[4:0] == 5'd0) begin
305 
                            DataEnableA[{2'd3, WriteAddress[4:0]}] <= 1'b1;
306 
                            DataEnableA[127:97] <= 31'd0;
307 
                            DataEnableB[127:96] <= 32'd0;
308 
                        end else begin
309 
                            DataEnableA[{2'd3, WriteAddress[4:0]}] <= 1'b1;
310 
                        end
311 
                    end else begin
312 
                        DataEnableB[{2'd3, WriteAddress[4:0]}] <= 1'b1;
313 
                    end
314 
                end
315 
            end
316 
        end
317 
    end
318 
 
319 
    reg AddressDelayA, AddressDelayB;
320 
 
321 
    always @(posedge clk or negedge rst) begin
322 
        if(!rst) begin
323 
            AddressDelayA <= 1'b0;
324 
            AddressDelayB <= 1'b0;
325 
        end else begin
326 
            AddressDelayA <= DataEnableA[{ReadBank, DataOutAddress}];
327 
            AddressDelayB <= DataEnableB[{ReadBank, DataOutAddress}];
328 
        end
329 
    end
330 3 hidemi 
 
331 9 hidemi 
    // Output Signal
332 
    assign DataInIdle       = (State == S_IDLE) | (State == S_VALID);
333 
    assign DataOutEnable    = (State == S_VALID) | (State == S_FULL);
334 
    assign DataOutColor     = BankColor[ReadBank];
335 
    assign DataOutA         = (AddressDelayA)?RegMemoryA:16'd0;
336 
    assign DataOutB         = (AddressDelayB)?RegMemoryB:16'd0;
337 3 hidemi 
 
338 9 hidemi 
endmodule

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