URL https://opencores.org/ocsvn/dma_ahb/dma_ahb/trunk

Subversion Repositories dma_ahb

[/] [dma_ahb/] [trunk/] [src/] [dma_ahb32/] [dma_ahb32.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log


//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:31:21 2011
//--
//-- Source file: dma.v
//---------------------------------------------------------
 
 
 
module dma_ahb32(clk,reset,scan_en,idle,INT,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,pready,WHADDR0,WHBURST0,WHSIZE0,WHTRANS0,WHWDATA0,WHREADY0,WHRESP0,RHADDR0,RHBURST0,RHSIZE0,RHTRANS0,RHRDATA0,RHREADY0,RHRESP0);
`include "dma_ahb32_defines.v"
 
   input                                clk;
   input                 reset;
   input                 scan_en;
 
   output                 idle;
   output [1-1:0]                INT;
 
   input [31:1]             periph_tx_req;
   output [31:1]             periph_tx_clr;
   input [31:1]             periph_rx_req;
   output [31:1]             periph_rx_clr;
 
   input                                pclken;
   input                                psel;
   input                                penable;
   input [12:0]                         paddr;
   input                                pwrite;
   input [31:0]                         pwdata;
   output [31:0]                        prdata;
   output                               pslverr;
   output                               pready;
 
 
   output [32-1:0]              WHADDR0;
   output [2:0]                         WHBURST0;
   output [1:0]                         WHSIZE0;
   output [1:0]                         WHTRANS0;
   output [32-1:0]              WHWDATA0;
   input                                WHREADY0;
   input                                WHRESP0;
   output [32-1:0]              RHADDR0;
   output [2:0]                         RHBURST0;
   output [1:0]                         RHSIZE0;
   output [1:0]                         RHTRANS0;
   input [32-1:0]               RHRDATA0;
   input                                RHREADY0;
   input                                RHRESP0;
 
 
 
   wire                 rd_port_num0;
   wire                 wr_port_num0;
   wire                 rd_port_num1;
   wire                 wr_port_num1;
   wire                 slv_rd_port_num0;
   wire                 slv_wr_port_num0;
   wire                 slv_rd_port_num1;
   wire                 slv_wr_port_num1;
 
   wire [32-1:0]                WHADDR0;
   wire [2:0]                           WHBURST0;
   wire [1:0]                           WHSIZE0;
   wire [1:0]                           WHTRANS0;
   wire [32-1:0]                WHWDATA0;
   wire                                 WHREADY0;
   wire                                 WHRESP0;
   wire [32-1:0]                RHADDR0;
   wire [2:0]                           RHBURST0;
   wire [1:0]                           RHSIZE0;
   wire [1:0]                           RHTRANS0;
   wire [32-1:0]                RHRDATA0;
   wire                                 RHREADY0;
   wire                                 RHRESP0;
   wire                                 WHLAST0;
   wire                                 WHOLD0;
   wire                                 RHLAST0;
   wire                                 RHOLD0;
 
   wire [32-1:0]           M0_WHADDR;
   wire [2:0]                           M0_WHBURST;
   wire [1:0]                           M0_WHSIZE;
   wire [1:0]                           M0_WHTRANS;
   wire [32-1:0]           M0_WHWDATA;
   wire                                 M0_WHREADY;
   wire                                 M0_WHRESP;
   wire [32-1:0]           M0_RHADDR;
   wire [2:0]                           M0_RHBURST;
   wire [1:0]                           M0_RHSIZE;
   wire [1:0]                           M0_RHTRANS;
   wire [32-1:0]           M0_RHRDATA;
   wire                                 M0_RHREADY;
   wire                                 M0_RHRESP;
   wire                                 M0_WHLAST;
   wire                                 M0_WHOLD;
   wire                                 M0_RHLAST;
   wire                                 M0_RHOLD;
   wire [24-1:0]           M1_WHADDR;
   wire [2:0]                           M1_WHBURST;
   wire [1:0]                           M1_WHSIZE;
   wire [1:0]                           M1_WHTRANS;
   wire [32-1:0]           M1_WHWDATA;
   wire                                 M1_WHREADY;
   wire                                 M1_WHRESP;
   wire [24-1:0]           M1_RHADDR;
   wire [2:0]                           M1_RHBURST;
   wire [1:0]                           M1_RHSIZE;
   wire [1:0]                           M1_RHTRANS;
   wire [32-1:0]           M1_RHRDATA;
   wire                                 M1_RHREADY;
   wire                                 M1_RHRESP;
   wire                                 M1_WHLAST;
   wire                                 M1_WHOLD;
   wire                                 M1_RHLAST;
   wire                                 M1_RHOLD;
 
 
 
   wire [31:1]                 periph_tx_req;
   wire [31:1]                 periph_rx_req;
   wire [31:1]                 periph_tx_clr;
   wire [31:1]                 periph_rx_clr;
 
 
 
 
 
 
   assign                               WHADDR0   = M0_WHADDR;
   assign                               WHBURST0   = M0_WHBURST;
   assign                               WHSIZE0   = M0_WHSIZE;
   assign                               WHTRANS0   = M0_WHTRANS;
   assign                               WHWDATA0   = M0_WHWDATA;
   assign                               RHADDR0   = M0_RHADDR;
   assign                               RHBURST0   = M0_RHBURST;
   assign                               RHSIZE0   = M0_RHSIZE;
   assign                               RHTRANS0   = M0_RHTRANS;
   assign                               WHLAST0   = M0_WHLAST;
   assign                               RHLAST0   = M0_RHLAST;
   assign                               M0_WHREADY  = WHREADY0;
   assign                               M0_WHRESP  = WHRESP0;
   assign                               M0_RHRDATA  = RHRDATA0;
   assign                               M0_RHREADY  = RHREADY0;
   assign                               M0_RHRESP  = RHRESP0;
   assign                               M0_WHOLD  = WHOLD0;
   assign                               M0_RHOLD  = RHOLD0;
 
   assign                 RHOLD0 = 1'b0;
   assign                 WHOLD0 = 1'b0;
 
 
 
 
 
 
   dma_ahb32_dual_core
   dma_ahb32_dual_core (
             .clk(clk),
             .reset(reset),
             .scan_en(scan_en),
 
             .idle(idle),
             .INT(INT),
             .periph_tx_req(periph_tx_req),
             .periph_tx_clr(periph_tx_clr),
             .periph_rx_req(periph_rx_req),
             .periph_rx_clr(periph_rx_clr),
                     .pclken(pclken),
                     .psel(psel),
                     .penable(penable),
                     .paddr(paddr),
                     .pwrite(pwrite),
                     .pwdata(pwdata),
                     .prdata(prdata),
                     .pslverr(pslverr),
                     .pready(pready),
 
             .rd_port_num0(rd_port_num0),
             .wr_port_num0(wr_port_num0),
             .rd_port_num1(rd_port_num1),
             .wr_port_num1(wr_port_num1),
 
                     .M0_WHADDR(M0_WHADDR),
                     .M0_WHBURST(M0_WHBURST),
                     .M0_WHSIZE(M0_WHSIZE),
                     .M0_WHTRANS(M0_WHTRANS),
                     .M0_WHWDATA(M0_WHWDATA),
                     .M0_WHREADY(M0_WHREADY),
                     .M0_WHRESP(M0_WHRESP),
                     .M0_RHADDR(M0_RHADDR),
                     .M0_RHBURST(M0_RHBURST),
                     .M0_RHSIZE(M0_RHSIZE),
                     .M0_RHTRANS(M0_RHTRANS),
                     .M0_RHRDATA(M0_RHRDATA),
                     .M0_RHREADY(M0_RHREADY),
                     .M0_RHRESP(M0_RHRESP),
                     .M0_WHLAST(M0_WHLAST),
                     .M0_WHOLD(M0_WHOLD),
                     .M0_RHLAST(M0_RHLAST),
                     .M0_RHOLD(M0_RHOLD)
             );
 
 
 
endmodule
 
 
 
 

Browse

Tools

Subversion Repositories dma_ahb

[/] [dma_ahb/] [trunk/] [src/] [dma_ahb32/] [dma_ahb32.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	eyalhoc	`//---------------------------------------------------------`
2			`//-- File generated by RobustVerilog parser`
3			`//-- Version: 1.0`
4			`//-- Invoked Fri Mar 25 23:31:21 2011`
5			`//--`
6			`//-- Source file: dma.v`
7			`//---------------------------------------------------------`
8
9
10
11			`module dma_ahb32(clk,reset,scan_en,idle,INT,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,pready,WHADDR0,WHBURST0,WHSIZE0,WHTRANS0,WHWDATA0,WHREADY0,WHRESP0,RHADDR0,RHBURST0,RHSIZE0,RHTRANS0,RHRDATA0,RHREADY0,RHRESP0);`
12			`include "dma_ahb32_defines.v"
13
14			`input clk;`
15			`input reset;`
16			`input scan_en;`
17
18			`output idle;`
19			`output [1-1:0] INT;`
20
21			`input [31:1] periph_tx_req;`
22			`output [31:1] periph_tx_clr;`
23			`input [31:1] periph_rx_req;`
24			`output [31:1] periph_rx_clr;`
25
26			`input pclken;`
27			`input psel;`
28			`input penable;`
29			`input [12:0] paddr;`
30			`input pwrite;`
31			`input [31:0] pwdata;`
32			`output [31:0] prdata;`
33			`output pslverr;`
34			`output pready;`
35
36
37			`output [32-1:0] WHADDR0;`
38			`output [2:0] WHBURST0;`
39			`output [1:0] WHSIZE0;`
40			`output [1:0] WHTRANS0;`
41			`output [32-1:0] WHWDATA0;`
42			`input WHREADY0;`
43			`input WHRESP0;`
44			`output [32-1:0] RHADDR0;`
45			`output [2:0] RHBURST0;`
46			`output [1:0] RHSIZE0;`
47			`output [1:0] RHTRANS0;`
48			`input [32-1:0] RHRDATA0;`
49			`input RHREADY0;`
50			`input RHRESP0;`
51
52
53
54			`wire rd_port_num0;`
55			`wire wr_port_num0;`
56			`wire rd_port_num1;`
57			`wire wr_port_num1;`
58			`wire slv_rd_port_num0;`
59			`wire slv_wr_port_num0;`
60			`wire slv_rd_port_num1;`
61			`wire slv_wr_port_num1;`
62
63			`wire [32-1:0] WHADDR0;`
64			`wire [2:0] WHBURST0;`
65			`wire [1:0] WHSIZE0;`
66			`wire [1:0] WHTRANS0;`
67			`wire [32-1:0] WHWDATA0;`
68			`wire WHREADY0;`
69			`wire WHRESP0;`
70			`wire [32-1:0] RHADDR0;`
71			`wire [2:0] RHBURST0;`
72			`wire [1:0] RHSIZE0;`
73			`wire [1:0] RHTRANS0;`
74			`wire [32-1:0] RHRDATA0;`
75			`wire RHREADY0;`
76			`wire RHRESP0;`
77			`wire WHLAST0;`
78			`wire WHOLD0;`
79			`wire RHLAST0;`
80			`wire RHOLD0;`
81
82			`wire [32-1:0] M0_WHADDR;`
83			`wire [2:0] M0_WHBURST;`
84			`wire [1:0] M0_WHSIZE;`
85			`wire [1:0] M0_WHTRANS;`
86			`wire [32-1:0] M0_WHWDATA;`
87			`wire M0_WHREADY;`
88			`wire M0_WHRESP;`
89			`wire [32-1:0] M0_RHADDR;`
90			`wire [2:0] M0_RHBURST;`
91			`wire [1:0] M0_RHSIZE;`
92			`wire [1:0] M0_RHTRANS;`
93			`wire [32-1:0] M0_RHRDATA;`
94			`wire M0_RHREADY;`
95			`wire M0_RHRESP;`
96			`wire M0_WHLAST;`
97			`wire M0_WHOLD;`
98			`wire M0_RHLAST;`
99			`wire M0_RHOLD;`
100			`wire [24-1:0] M1_WHADDR;`
101			`wire [2:0] M1_WHBURST;`
102			`wire [1:0] M1_WHSIZE;`
103			`wire [1:0] M1_WHTRANS;`
104			`wire [32-1:0] M1_WHWDATA;`
105			`wire M1_WHREADY;`
106			`wire M1_WHRESP;`
107			`wire [24-1:0] M1_RHADDR;`
108			`wire [2:0] M1_RHBURST;`
109			`wire [1:0] M1_RHSIZE;`
110			`wire [1:0] M1_RHTRANS;`
111			`wire [32-1:0] M1_RHRDATA;`
112			`wire M1_RHREADY;`
113			`wire M1_RHRESP;`
114			`wire M1_WHLAST;`
115			`wire M1_WHOLD;`
116			`wire M1_RHLAST;`
117			`wire M1_RHOLD;`
118
119
120
121			`wire [31:1] periph_tx_req;`
122			`wire [31:1] periph_rx_req;`
123			`wire [31:1] periph_tx_clr;`
124			`wire [31:1] periph_rx_clr;`
125
126
127
128
129
130
131			`assign WHADDR0 = M0_WHADDR;`
132			`assign WHBURST0 = M0_WHBURST;`
133			`assign WHSIZE0 = M0_WHSIZE;`
134			`assign WHTRANS0 = M0_WHTRANS;`
135			`assign WHWDATA0 = M0_WHWDATA;`
136			`assign RHADDR0 = M0_RHADDR;`
137			`assign RHBURST0 = M0_RHBURST;`
138			`assign RHSIZE0 = M0_RHSIZE;`
139			`assign RHTRANS0 = M0_RHTRANS;`
140			`assign WHLAST0 = M0_WHLAST;`
141			`assign RHLAST0 = M0_RHLAST;`
142			`assign M0_WHREADY = WHREADY0;`
143			`assign M0_WHRESP = WHRESP0;`
144			`assign M0_RHRDATA = RHRDATA0;`
145			`assign M0_RHREADY = RHREADY0;`
146			`assign M0_RHRESP = RHRESP0;`
147			`assign M0_WHOLD = WHOLD0;`
148			`assign M0_RHOLD = RHOLD0;`
149
150			`assign RHOLD0 = 1'b0;`
151			`assign WHOLD0 = 1'b0;`
152
153
154
155
156
157
158			`dma_ahb32_dual_core`
159			`dma_ahb32_dual_core (`
160			`.clk(clk),`
161			`.reset(reset),`
162			`.scan_en(scan_en),`
163
164			`.idle(idle),`
165			`.INT(INT),`
166			`.periph_tx_req(periph_tx_req),`
167			`.periph_tx_clr(periph_tx_clr),`
168			`.periph_rx_req(periph_rx_req),`
169			`.periph_rx_clr(periph_rx_clr),`
170			`.pclken(pclken),`
171			`.psel(psel),`
172			`.penable(penable),`
173			`.paddr(paddr),`
174			`.pwrite(pwrite),`
175			`.pwdata(pwdata),`
176			`.prdata(prdata),`
177			`.pslverr(pslverr),`
178			`.pready(pready),`
179
180			`.rd_port_num0(rd_port_num0),`
181			`.wr_port_num0(wr_port_num0),`
182			`.rd_port_num1(rd_port_num1),`
183			`.wr_port_num1(wr_port_num1),`
184
185			`.M0_WHADDR(M0_WHADDR),`
186			`.M0_WHBURST(M0_WHBURST),`
187			`.M0_WHSIZE(M0_WHSIZE),`
188			`.M0_WHTRANS(M0_WHTRANS),`
189			`.M0_WHWDATA(M0_WHWDATA),`
190			`.M0_WHREADY(M0_WHREADY),`
191			`.M0_WHRESP(M0_WHRESP),`
192			`.M0_RHADDR(M0_RHADDR),`
193			`.M0_RHBURST(M0_RHBURST),`
194			`.M0_RHSIZE(M0_RHSIZE),`
195			`.M0_RHTRANS(M0_RHTRANS),`
196			`.M0_RHRDATA(M0_RHRDATA),`
197			`.M0_RHREADY(M0_RHREADY),`
198			`.M0_RHRESP(M0_RHRESP),`
199			`.M0_WHLAST(M0_WHLAST),`
200			`.M0_WHOLD(M0_WHOLD),`
201			`.M0_RHLAST(M0_RHLAST),`
202			`.M0_RHOLD(M0_RHOLD)`
203			`);`
204
205
206
207			`endmodule`
208
209
210
211