OpenCores
URL https://opencores.org/ocsvn/dma_ahb/dma_ahb/trunk

Subversion Repositories dma_ahb

[/] [dma_ahb/] [trunk/] [src/] [dma_ahb32/] [dma_ahb32_core0_channels_apb_mux.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 eyalhoc
//---------------------------------------------------------
2
//-- File generated by RobustVerilog parser
3
//-- Version: 1.0
4
//-- Invoked Fri Mar 25 23:31:23 2011
5
//--
6
//-- Source file: dma_core_channels_apb_mux.v
7
//---------------------------------------------------------
8
 
9
 
10
 
11
module  dma_ahb32_core0_channels_apb_mux (clk,reset,pclken,psel,penable,paddr,prdata,pslverr,ch_psel,ch_prdata,ch_pslverr);
12
 
13
   input                 clk;
14
   input                 reset;
15
 
16
   input          pclken;
17
   input          psel;
18
   input                 penable;
19
   input [10:8]          paddr;
20
   output [31:0]         prdata;
21
   output          pslverr;
22
 
23
   output [7:0]      ch_psel;
24
   input [32*8-1:0]      ch_prdata;
25
   input [7:0]          ch_pslverr;
26
 
27
 
28
   wire [2:0]          paddr_sel;
29
   reg [2:0]          paddr_sel_d;
30
 
31
 
32
 
33
   always @(posedge clk or posedge reset)
34
     if (reset)
35
       paddr_sel_d <= #1 3'b000;
36
     else if (psel & (~penable))
37
       paddr_sel_d <= #1 paddr_sel;
38
     else if ((~psel) & pclken) //release for empty channels after error
39
       paddr_sel_d <= #1 3'b000;
40
 
41
 
42
 
43
   assign          paddr_sel = paddr[10:8];
44
 
45
   prgen_demux8 #(1) mux_psel(
46
                  .sel(paddr_sel),
47
                  .x(psel),
48
                  .ch_x(ch_psel)
49
                  );
50
 
51
 
52
   prgen_mux8 #(32) mux_prdata(
53
                   .sel(paddr_sel_d),
54
 
55
                   .ch_x(ch_prdata),
56
                   .x(prdata)
57
                   );
58
 
59
 
60
   assign                pslverr = ch_pslverr[paddr_sel_d];
61
 
62
endmodule
63
 
64
 
65
 
66
 
67
 
68
 
69
 
70
 
71
 
72
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.