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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb32/] [prgen_rawstat.v] - Blame information for rev 2

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1 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:31:24 2011
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//--
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//-- Source file: prgen_rawstat.v
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//---------------------------------------------------------
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module  prgen_rawstat (clk,reset,clear,write,pwdata,int_bus,rawstat);
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   parameter           SIZE = 32;
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   input            clk;
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   input            reset;
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   input            clear;
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   input            write;
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   input [SIZE-1:0]    pwdata;
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   input [SIZE-1:0]    int_bus;
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   output [SIZE-1:0]   rawstat;
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   reg [SIZE-1:0]      rawstat;
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   wire [SIZE-1:0]     write_bus;
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   wire [SIZE-1:0]     clear_bus;
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   assign            write_bus = {SIZE{write}} & pwdata;
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   assign            clear_bus = {SIZE{clear}} & pwdata;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       rawstat <= #1 {SIZE{1'b0}};
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     else
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       rawstat <= #1 (rawstat | int_bus | write_bus) & (~clear_bus);
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endmodule
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