OpenCores
URL https://opencores.org/ocsvn/dma_ahb/dma_ahb/trunk

Subversion Repositories dma_ahb

[/] [dma_ahb/] [trunk/] [src/] [dma_ahb64/] [dma_ahb64_apb_mux.v] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 eyalhoc
//---------------------------------------------------------
2
//-- File generated by RobustVerilog parser
3
//-- Version: 1.0
4
//-- Invoked Fri Mar 25 23:32:59 2011
5
//--
6
//-- Source file: dma_apb_mux.v
7
//---------------------------------------------------------
8
 
9
 
10
 
11
module  dma_ahb64_apb_mux (clk,reset,pclken,psel,penable,pwrite,paddr,prdata,pslverr,pready,psel0,prdata0,pslverr0,psel1,prdata1,pslverr1,psel_reg,prdata_reg,pslverr_reg);
12
 
13
   input                 clk;
14
   input                 reset;
15
 
16
   input                 pclken;
17
   input                 psel;
18
   input                 penable;
19
   input          pwrite;
20
   input [12:11]      paddr;
21
   output [31:0]         prdata;
22
   output          pslverr;
23
   output          pready;
24
 
25
   output          psel0;
26
   input [31:0]      prdata0;
27
   input           pslverr0;
28
 
29
   output          psel1;
30
   input [31:0]      prdata1;
31
   input           pslverr1;
32
 
33
   output          psel_reg;
34
   input [31:0]      prdata_reg;
35
   input           pslverr_reg;
36
 
37
   wire [31:0]          prdata_pre;
38
   wire          pslverr_pre;
39
 
40
 
41
   reg              pready;
42
 
43
 
44
   assign          psel0    = pclken & psel & (paddr[12:11] == 2'b00);
45
   assign          psel1    = pclken & psel & (paddr[12:11] == 2'b01);
46
   assign          psel_reg = pclken & psel & (paddr[12] == 1'b1);
47
 
48
   assign          prdata_pre  = prdata0 | prdata1 | prdata_reg;
49
   assign          pslverr_pre = pslverr0 | pslverr1 | pslverr_reg;
50
 
51
   assign          prdata = prdata_pre;
52
   assign          pslverr = pslverr_pre;
53
 
54
 
55
   always @(posedge clk or posedge reset)
56
     if (reset)
57
       pready <= #1 1'b0;
58
     else if (pclken)
59
       pready <= #1 psel & (~penable);
60
 
61
 
62
endmodule
63
 
64
 
65
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.