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//---------------------------------------------------------

//-- File generated by RobustVerilog parser

//-- Version: 1.0

//-- Invoked Fri Mar 25 23:33:00 2011

//--

//-- Source file: dma_core_ahbm_timeout.v

//---------------------------------------------------------

module dma_ahb64_core0_ahbm_timeout(clk,reset,HTRANS,HREADY,ahb_timeout);

   input               clk;

   input               reset;

   input [1:0]               HTRANS;

   input               HREADY;

   output               ahb_timeout;

   wire               HVALID;

   reg [`TIMEOUT_BITS-1:0]    counter;

   assign               HVALID      = HTRANS[1];

   assign               ahb_timeout = (counter == 'd0);

   always @(posedge clk or posedge reset)

     if (reset)

       counter <= #1 {`TIMEOUT_BITS{1'b1}};

     else if (HVALID & HREADY)

       counter <= #1 {`TIMEOUT_BITS{1'b1}};

     else if (HVALID)

       counter <= #1 counter - 1'b1;

endmodule