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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb64/] [dma_ahb64_defines.v] - Blame information for rev 4
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eyalhoc |
/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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eyalhoc |
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:32:58 2011
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//--
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//-- Source file: dma_defines.v
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//---------------------------------------------------------
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`define FRAME_BITS 12
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`define X_BITS 8
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`define TOKEN_BITS 6
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`define OUT_BITS 4
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`define DELAY_BITS 3
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`define CMD_CNT_BITS 12
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`define INT_CNT_BITS 4
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`define WAIT_BITS 12
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`define TIMEOUT_BITS 10
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`define WDT_BITS 11
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`define CMD_BITS 7
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`define ID_BITS 1
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`define LEN_BITS 4
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`define SIZE_BITS 2
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`define ID_END_LINE 6
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`define ID_LAST 3
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