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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb64/] [prgen_delay.v] - Blame information for rev 2

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1 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:33:02 2011
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//--
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//-- Source file: prgen_delay.v
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//---------------------------------------------------------
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module prgen_delay(clk,reset,din,dout);
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   input               clk;
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   input               reset;
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   input               din;
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   output               dout;
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   parameter               DELAY = 2;
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   reg [DELAY:0]           shift_reg;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       shift_reg <= #1 {DELAY+1{1'b0}};
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     else
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       shift_reg <= #1 {shift_reg[DELAY-1:0], din};
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   assign               dout = shift_reg[DELAY-1];
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endmodule
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