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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb64/] [prgen_demux8.v] - Blame information for rev 2

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1 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:33:00 2011
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//--
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//-- Source file: prgen_demux.v
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//---------------------------------------------------------
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module prgen_demux8(sel,x,ch_x);
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   parameter                  WIDTH      = 8;
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   input [3-1:0]     sel;
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   input [WIDTH-1:0]           x;
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   output [8*WIDTH-1:0]    ch_x;
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   reg [8*WIDTH-1:0]       ch_x;
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   always @(/*AUTOSENSE*/sel or x)
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     begin
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    ch_x = {8*WIDTH{1'b0}};
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    case (sel)
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      3'd0 : ch_x[WIDTH-1+WIDTH*0:WIDTH*0] = x;
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      3'd1 : ch_x[WIDTH-1+WIDTH*1:WIDTH*1] = x;
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      3'd2 : ch_x[WIDTH-1+WIDTH*2:WIDTH*2] = x;
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      3'd3 : ch_x[WIDTH-1+WIDTH*3:WIDTH*3] = x;
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      3'd4 : ch_x[WIDTH-1+WIDTH*4:WIDTH*4] = x;
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      3'd5 : ch_x[WIDTH-1+WIDTH*5:WIDTH*5] = x;
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      3'd6 : ch_x[WIDTH-1+WIDTH*6:WIDTH*6] = x;
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      3'd7 : ch_x[WIDTH-1+WIDTH*7:WIDTH*7] = x;
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      default :
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        ch_x[WIDTH-1:0] = x;
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    endcase
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     end
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endmodule
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