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//---------------------------------------------------------

//-- File generated by RobustVerilog parser

//-- Version: 1.0

//-- Invoked Fri Mar 25 23:33:00 2011

//--

//-- Source file: prgen_stall.v

//---------------------------------------------------------

module prgen_stall(clk,reset,din,stall,dout);

   parameter                  DEPTH   = 1;

   input               clk;

   input               reset;

   input               din;

   input               stall;

   output               dout;

   reg [DEPTH-1:0]           count;

   wire               pend;

   always @(posedge clk or posedge reset)

     if (reset)

       count <= #1 {DEPTH{1'b0}};

     else if (pend & (~stall))

       count <= #1 count - 1'b1;

     else if (din & stall)

       count <= #1 count + 1'b1;

   assign               pend = (|count);

   assign               dout = (din | pend) & (~stall);

endmodule