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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb64/] [prgen_stall.v] - Blame information for rev 2

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1 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:33:00 2011
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//--
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//-- Source file: prgen_stall.v
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//---------------------------------------------------------
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module prgen_stall(clk,reset,din,stall,dout);
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   parameter                  DEPTH   = 1;
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   input               clk;
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   input               reset;
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   input               din;
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   input               stall;
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   output               dout;
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   reg [DEPTH-1:0]           count;
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   wire               pend;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       count <= #1 {DEPTH{1'b0}};
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     else if (pend & (~stall))
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       count <= #1 count - 1'b1;
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     else if (din & stall)
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       count <= #1 count + 1'b1;
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   assign               pend = (|count);
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   assign               dout = (din | pend) & (~stall);
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endmodule
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