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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb64/] [prgen_swap_32.v] - Blame information for rev 2

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1 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:33:02 2011
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//--
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//-- Source file: prgen_swap32.v
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//---------------------------------------------------------
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module  prgen_swap32 (end_swap,data_in,data_out,bsel_in,bsel_out);
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   input [1:0]            end_swap;
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   input [31:0]        data_in;
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   output [31:0]       data_out;
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   input [3:0]            bsel_in;
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   output [3:0]        bsel_out;
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   reg [31:0]            data_out;
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   reg [3:0]            bsel_out;
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   always @(/*AUTOSENSE*/data_in or end_swap)
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     begin
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    case (end_swap[1:0])
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      2'b00   : data_out = data_in;
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      2'b01   : data_out = {data_in[23:16], data_in[31:24], data_in[7:0], data_in[15:8]};
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      2'b10   : data_out = {data_in[7:0], data_in[15:8], data_in[23:16], data_in[31:24]};
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      2'b11   : data_out = {data_in[7:0], data_in[15:8], data_in[23:16], data_in[31:24]};
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    endcase
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     end
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   always @(/*AUTOSENSE*/bsel_in or end_swap)
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     begin
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    case (end_swap[1:0])
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      2'b00   : bsel_out = bsel_in;
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      2'b01   : bsel_out = {bsel_in[2], bsel_in[3], bsel_in[0], bsel_in[1]};
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      2'b10   : bsel_out = {bsel_in[0], bsel_in[1], bsel_in[2], bsel_in[3]};
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      2'b11   : bsel_out = {bsel_in[0], bsel_in[1], bsel_in[2], bsel_in[3]};
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    endcase
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     end
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endmodule
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