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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb64/] [prgen_swap_64.v] - Blame information for rev 2

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1 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:33:02 2011
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//--
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//-- Source file: prgen_swap64.v
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//---------------------------------------------------------
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module  prgen_swap64 (end_swap,data_in,data_out,bsel_in,bsel_out);
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   input [1:0]            end_swap;
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   input [63:0]        data_in;
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   output [63:0]       data_out;
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   input [7:0]            bsel_in;
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   output [7:0]        bsel_out;
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   wire [31:0]            data_in_low;
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   wire [31:0]            data_in_high;
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   wire [31:0]            data_out_low;
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   wire [31:0]            data_out_high;
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   wire [3:0]            bsel_in_low;
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   wire [3:0]            bsel_in_high;
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   wire [3:0]            bsel_out_low;
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   wire [3:0]            bsel_out_high;
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   assign            data_in_low  = end_swap == 2'b11 ? data_in[63:32] : data_in[31:0];
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   assign            data_in_high = end_swap == 2'b11 ? data_in[31:0]  : data_in[63:32];
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   assign            bsel_in_low  = end_swap == 2'b11 ? bsel_in[7:4] : bsel_in[3:0];
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   assign            bsel_in_high = end_swap == 2'b11 ? bsel_in[3:0] : bsel_in[7:4];
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   prgen_swap32 swap32_low(
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               .end_swap(end_swap),
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               .data_in(data_in_low),
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               .data_out(data_out_low),
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               .bsel_in(bsel_in_low),
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               .bsel_out(bsel_out_low)
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               );
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   prgen_swap32 swap32_high(
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                .end_swap(end_swap),
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                .data_in(data_in_high),
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                .data_out(data_out_high),
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                .bsel_in(bsel_in_high),
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                .bsel_out(bsel_out_high)
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               );
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   assign            data_out = {data_out_high, data_out_low};
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   assign            bsel_out = {bsel_out_high, bsel_out_low};
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endmodule
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