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//---------------------------------------------------------

//-- File generated by RobustVerilog parser

//-- Version: 1.0

//-- Invoked Fri Mar 25 23:33:02 2011

//--

//-- Source file: prgen_swap64.v

//---------------------------------------------------------

module  prgen_swap64 (end_swap,data_in,data_out,bsel_in,bsel_out);

   input [1:0]            end_swap;

   input [63:0]        data_in;

   output [63:0]       data_out;

   input [7:0]            bsel_in;

   output [7:0]        bsel_out;

   wire [31:0]            data_in_low;

   wire [31:0]            data_in_high;

   wire [31:0]            data_out_low;

   wire [31:0]            data_out_high;

   wire [3:0]            bsel_in_low;

   wire [3:0]            bsel_in_high;

   wire [3:0]            bsel_out_low;

   wire [3:0]            bsel_out_high;

   assign            data_in_low  = end_swap == 2'b11 ? data_in[63:32] : data_in[31:0];

   assign            data_in_high = end_swap == 2'b11 ? data_in[31:0]  : data_in[63:32];

   assign            bsel_in_low  = end_swap == 2'b11 ? bsel_in[7:4] : bsel_in[3:0];

   assign            bsel_in_high = end_swap == 2'b11 ? bsel_in[3:0] : bsel_in[7:4];

   prgen_swap32 swap32_low(

               .end_swap(end_swap),

               .data_in(data_in_low),

               .data_out(data_out_low),

               .bsel_in(bsel_in_low),

               .bsel_out(bsel_out_low)

               );

   prgen_swap32 swap32_high(

                .end_swap(end_swap),

                .data_in(data_in_high),

                .data_out(data_out_high),

                .bsel_in(bsel_in_high),

                .bsel_out(bsel_out_high)

               );

   assign            data_out = {data_out_high, data_out_low};

   assign            bsel_out = {bsel_out_high, bsel_out_low};

endmodule