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[/] [dmt_tx/] [trunk/] [const_encoder/] [tb/] [tb_const_enc.v] - Blame information for rev 16

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/* *****************************************************************
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 *
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 *  This file is part of the
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 *
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 *   Tone Order and Constellation Encoder Core.
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 *
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 *  Copyright (C) 2007 Guenter Dannoritzer
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 *
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 *   This source is free software; you can redistribute it
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 *   and/or modify it under the terms of the
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 *             GNU General Public License
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 *   as published by the Free Software Foundation;
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 *   either version 3 of the License,
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 *   or (at your option) any later version.
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 *
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 *   This source is distributed in the hope
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 *   that it will be useful, but WITHOUT ANY WARRANTY;
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 *   without even the implied warranty of MERCHANTABILITY
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 *   or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 *   GNU General Public License for more details.
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 *
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 *   You should have received a copy of the
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 *   GNU General Public License along with this source.
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 *   If not, see <http://www.gnu.org/licenses/>.
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 *
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 * *****************************************************************/
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module tb_const_encoder();
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parameter TW              = 10;
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`include "parameters.vh"
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reg                 clk;
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reg                 reset;
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wire                fast_ready_o;
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reg                 we_fast_data_i;
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reg   [DW-1:0]      fast_data_i;
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wire                inter_ready_o;
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reg                 we_inter_data_i;
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reg   [DW-1:0]      inter_data_i;
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reg                 we_conf_i;
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reg   [CONFAW-1:0]  addr_i;
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reg   [CONFDW-1:0]  conf_data_i;
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wire  [CNUMW-1:0]   carrier_num_o;
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wire  [CONSTW-1:0]  x_o;
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wire  [CONSTW-1:0]  y_o;
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//
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// instantiate the DUT
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// 
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const_encoder dut ( .clk(clk),
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                    .reset(reset),
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                    .fast_ready_o(fast_ready_o),
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                    .we_fast_data_i(we_fast_data_i),
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                    .fast_data_i(fast_data_i),
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                    .inter_ready_o(inter_ready_o),
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                    .we_inter_data_i(we_inter_data_i),
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                    .inter_data_i(inter_data_i),
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                    .addr_i(addr_i),
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                    .we_conf_i(we_conf_i),
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                    .conf_data_i(conf_data_i),
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                    .xy_ready_o(xy_ready_o),
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                    .carrier_num_o(carrier_num_o),
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                    .x_o(x_o),
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                    .y_o(y_o));
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initial begin
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  clk = 0;
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  we_fast_data_i = 0;
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  we_inter_data_i = 0;
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  we_conf_i = 0;
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  reset = 0;
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end
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always begin
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  #TW clk = ~clk;
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end
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//
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// dump signals
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//
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initial begin
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  $dumpfile("tb_const_enc.vcd");
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  $dumpvars;
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end
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//
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// main test
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// 
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initial begin
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  $monitor($time, " reset: ", reset);
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  apply_reset;
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  //
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  // write configuration
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  //
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  write_config(BIT_LOAD_ST_ADR, 2);
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  write_config(BIT_LOAD_ST_ADR+1, 3);
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  write_config(BIT_LOAD_ST_ADR+2, 4);
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  write_config(BIT_LOAD_ST_ADR+3, 5);
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  write_config(C_NUM_ST_ADR,    48);
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  write_config(C_NUM_ST_ADR+1,  49);
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  write_config(C_NUM_ST_ADR+2,  50);
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  write_config(C_NUM_ST_ADR+3,  51);
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  write_config(USED_C_ADR, 4);
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  write_config(F_BITS_ADR, 7);
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  //
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  // check written configuration
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  //
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  check_config(BIT_LOAD_ST_ADR,   2);
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  check_config(BIT_LOAD_ST_ADR+1, 3);
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  check_config(BIT_LOAD_ST_ADR+2, 4);
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  check_config(BIT_LOAD_ST_ADR+3, 5);
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  check_config(C_NUM_ST_ADR,    48);
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  check_config(C_NUM_ST_ADR+1,  49);
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  check_config(C_NUM_ST_ADR+2,  50);
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  check_config(C_NUM_ST_ADR+3,  51);
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  check_config(USED_C_ADR, 4);
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  check_config(F_BITS_ADR, 7);
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  #1000 $finish();
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end // main test
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// //////////////////////////////////////////////////////////////////// 
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// 
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// bus functional models
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// 
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// //////////////////////////////////////////////////////////////////// 
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task apply_reset;
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  begin
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    reset = 0;
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    #20
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    reset = 1;
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    @(posedge clk);
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    reset = 0;
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  end
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endtask
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//
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// write data to the configuration registers
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//
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task write_config(input [CONFAW-1:0] addr, input[CONFDW-1:0] data);
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  begin
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    addr_i = addr;
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    conf_data_i = data;
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    @(negedge clk);
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    we_conf_i = 1;
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    @(negedge clk);
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    we_conf_i = 0;
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  end
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endtask
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//
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// check the written configuration
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//
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task check_config(input [CONFAW-1:0] addr, input [CONFDW-1:0] exp_data);
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  begin
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    if(addr >= 0 && addr < C_NUM_ST_ADR) begin
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      if(dut.BitLoading[addr] !== exp_data) begin
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        $display("ERROR! => BitLoading does not match @ %x!", addr);
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        $display("          Got: %d expected: %d",
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                  dut.BitLoading[addr], exp_data);
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      end
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    end
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    else if(addr >= C_NUM_ST_ADR && addr < USED_C_ADR) begin
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      if(dut.CarrierNumber[addr-C_NUM_ST_ADR] !== exp_data) begin
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        $display("ERROR! => CarrierNumber does not match @ %x!", addr);
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        $display("          Got: %d expected: %d",
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                  dut.CarrierNumber[addr-C_NUM_ST_ADR], exp_data);
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      end
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    end
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    else if(addr == USED_C_ADR) begin
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      if(dut.UsedCarrier !== exp_data) begin
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        $display("ERROR! => UsedCarrier does not match @ %x!", addr);
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        $display("          Got: %d expected: %d",
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                  dut.UsedCarrier, exp_data);
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      end
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    end
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    else if(addr == F_BITS_ADR) begin
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      if(dut.FastBits !== exp_data) begin
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        $display("ERROR! => FastBits does not match @ %x!", addr);
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        $display("          Got: %d expected: %d",
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                  dut.FastBits, exp_data);
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      end
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    end
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  end
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endtask
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endmodule

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