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[/] [dmt_tx/] [trunk/] [myhdl/] [test/] [test_cmath.py] - Blame information for rev 30

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import unittest
 
from myhdl import *
 
 
from rtl.cmath import cadd, csub
 
class TestCplxMath(unittest.TestCase):
 
  def test_cadd(self):
 
    def bench():
      width = 4
      m = 2**(width-1)
      a_re, a_im, b_re, b_im, y_re, y_im = [
          Signal(intbv(0,min=-m, max=m)) for i in range(6)]
      overflow = Signal(bool(0))
 
      cadd_inst = cadd(a_re,a_im,b_re,b_im,y_re,y_im, overflow, width)
 
      @instance
      def stimulus():
        a_im.next = 1
        b_re.next = 1
        b_im.next = 1
        overflow.next = False
 
        for ar in range(-m,m):
          for  br in range(-m,m):
            a_re.next = ar
            b_re.next = br
            yield delay(10)
 
        yield delay(10)
 
        raise StopSimulation
 
 
      @instance
      def verify():
        yield delay(5)
 
        while True:
          yre_exp = a_re + b_re
          yim_exp = a_im + b_im
          txt = "got: %s at: %d"%(overflow, now())
          if yre_exp >= m:
            ovfl_re = True
            yre_exp = m-1
          elif yre_exp < -m:
            ovfl_re = True
            yre_exp = -m
          else:
            ovfl_re = False
 
          self.assertEqual(y_re, yre_exp)
 
          if yim_exp >= m:
            ovfl_im = True
            yim_exp = m-1
          elif yim_exp < -m:
            ovfl_im = True
            yim_exp = -m
          else:
            ovfl_im = False
 
          self.assertEqual(y_im, yim_exp)
 
          ovfl_exp = ovfl_re or ovfl_im
 
          self.assertEqual(ovfl_exp, overflow, txt)
 
          yield delay(10)
 
      return instances()
 
    tb = bench()
    #tb = traceSignals(bench)
    sim = Simulation(tb)
    sim.run()
 
 
  def test_csub(self):
 
    def bench():
      width = 4
      m = 2**(width-1)
      a_re, a_im, b_re, b_im, y_re, y_im = [
          Signal(intbv(0,min=-m, max=m)) for i in range(6)]
      overflow = Signal(bool(0))
 
      csub_inst = csub(a_re,a_im,b_re,b_im,y_re,y_im, overflow, width)
 
      @instance
      def stimulus():
        a_im.next = 1
        b_im.next = 1
        overflow.next = False
 
        for ar in range(-m,m):
          for  br in range(-m,m):
            a_re.next = ar
            b_re.next = br
            yield delay(10)
 
        yield delay(10)
 
        raise StopSimulation
 
 
      @instance
      def verify():
        yield delay(5)
 
        while True:
          yre_exp = a_re - b_re
          yim_exp = a_im - b_im
          txt = "got: %s at: %d"%(overflow, now())
          if yre_exp >= m:
            ovfl_re = True
            yre_exp = m-1
          elif yre_exp < -m:
            ovfl_re = True
            yre_exp = -m
          else:
            ovfl_re = False
 
          self.assertEqual(y_re, yre_exp)
 
          if yim_exp >= m:
            ovfl_im = True
            yim_exp = m-1
          elif yim_exp < -m:
            ovfl_im = True
            yim_exp = -m
          else:
            ovfl_im = False
 
          self.assertEqual(y_im, yim_exp)
 
          ovfl_exp = ovfl_re or ovfl_im
 
          self.assertEqual(ovfl_exp, overflow, txt)
 
          yield delay(10)
 
      return instances()
 
    tb = bench()
    #tb = traceSignals(bench)
    sim = Simulation(tb)
    sim.run()
 
 
  def test_cmult(self):
    pass

Line No.	Rev	Author	Line
1	27	dannori
2			`import unittest`
3
4			`from myhdl import *`
5
6
7			`from rtl.cmath import cadd, csub`
8
9			`class TestCplxMath(unittest.TestCase):`
10
11			`def test_cadd(self):`
12
13			`def bench():`
14			`width = 4`
15			`m = 2**(width-1)`
16			`a_re, a_im, b_re, b_im, y_re, y_im = [`
17			`Signal(intbv(0,min=-m, max=m)) for i in range(6)]`
18			`overflow = Signal(bool(0))`
19
20			`cadd_inst = cadd(a_re,a_im,b_re,b_im,y_re,y_im, overflow, width)`
21
22			`@instance`
23			`def stimulus():`
24			`a_im.next = 1`
25			`b_re.next = 1`
26			`b_im.next = 1`
27			`overflow.next = False`
28
29			`for ar in range(-m,m):`
30			`for br in range(-m,m):`
31			`a_re.next = ar`
32			`b_re.next = br`
33			`yield delay(10)`
34
35			`yield delay(10)`
36
37			`raise StopSimulation`
38
39
40			`@instance`
41			`def verify():`
42			`yield delay(5)`
43
44			`while True:`
45			`yre_exp = a_re + b_re`
46			`yim_exp = a_im + b_im`
47			`txt = "got: %s at: %d"%(overflow, now())`
48			`if yre_exp >= m:`
49			`ovfl_re = True`
50			`yre_exp = m-1`
51			`elif yre_exp < -m:`
52			`ovfl_re = True`
53			`yre_exp = -m`
54			`else:`
55			`ovfl_re = False`
56
57			`self.assertEqual(y_re, yre_exp)`
58
59			`if yim_exp >= m:`
60			`ovfl_im = True`
61			`yim_exp = m-1`
62			`elif yim_exp < -m:`
63			`ovfl_im = True`
64			`yim_exp = -m`
65			`else:`
66			`ovfl_im = False`
67
68			`self.assertEqual(y_im, yim_exp)`
69
70			`ovfl_exp = ovfl_re or ovfl_im`
71
72			`self.assertEqual(ovfl_exp, overflow, txt)`
73
74			`yield delay(10)`
75
76			`return instances()`
77
78			`tb = bench()`
79			`#tb = traceSignals(bench)`
80			`sim = Simulation(tb)`
81			`sim.run()`
82
83
84			`def test_csub(self):`
85
86			`def bench():`
87			`width = 4`
88			`m = 2**(width-1)`
89			`a_re, a_im, b_re, b_im, y_re, y_im = [`
90			`Signal(intbv(0,min=-m, max=m)) for i in range(6)]`
91			`overflow = Signal(bool(0))`
92
93			`csub_inst = csub(a_re,a_im,b_re,b_im,y_re,y_im, overflow, width)`
94
95			`@instance`
96			`def stimulus():`
97			`a_im.next = 1`
98			`b_im.next = 1`
99			`overflow.next = False`
100
101			`for ar in range(-m,m):`
102			`for br in range(-m,m):`
103			`a_re.next = ar`
104			`b_re.next = br`
105			`yield delay(10)`
106
107			`yield delay(10)`
108
109			`raise StopSimulation`
110
111
112			`@instance`
113			`def verify():`
114			`yield delay(5)`
115
116			`while True:`
117			`yre_exp = a_re - b_re`
118			`yim_exp = a_im - b_im`
119			`txt = "got: %s at: %d"%(overflow, now())`
120			`if yre_exp >= m:`
121			`ovfl_re = True`
122			`yre_exp = m-1`
123			`elif yre_exp < -m:`
124			`ovfl_re = True`
125			`yre_exp = -m`
126			`else:`
127			`ovfl_re = False`
128
129			`self.assertEqual(y_re, yre_exp)`
130
131			`if yim_exp >= m:`
132			`ovfl_im = True`
133			`yim_exp = m-1`
134			`elif yim_exp < -m:`
135			`ovfl_im = True`
136			`yim_exp = -m`
137			`else:`
138			`ovfl_im = False`
139
140			`self.assertEqual(y_im, yim_exp)`
141
142			`ovfl_exp = ovfl_re or ovfl_im`
143
144			`self.assertEqual(ovfl_exp, overflow, txt)`
145
146			`yield delay(10)`
147
148			`return instances()`
149
150			`tb = bench()`
151			`#tb = traceSignals(bench)`
152			`sim = Simulation(tb)`
153			`sim.run()`
154
155
156			`def test_cmult(self):`
157			`pass`

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[/] [dmt_tx/] [trunk/] [myhdl/] [test/] [test_cmath.py] - Blame information for rev 30