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[/] [dmt_tx/] [trunk/] [myhdl/] [test/] [test_fifo_sync.py] - Blame information for rev 30

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#!/usr/bin/env python
 
import unittest
import os
from myhdl import *
 
if __name__ == '__main__':
  import sys
  sys.path.append('../')
 
from rtl.fifo_sync import fifo_sync
 
 
class TestFifo(unittest.TestCase):
 
  def test_fifo_simple(self):
 
    def bench():
 
      DWIDTH = 4
      SIZE = 4
 
      clk, reset, full_o, wen_i, data_avail_o, rden_i = \
          [Signal(bool(0)) for i in range(6)]
 
      data_i, data_o = [Signal(intbv(0)[DWIDTH:]) for i in range(2)]
 
      fifo_inst = fifo_sync( clk, reset,
                              full_o, wen_i, data_i,
                              data_avail_o, rden_i, data_o,
                              DWIDTH,SIZE)
 
      @always(delay(10))
      def clkgen():
        clk.next = not clk
 
      @instance
      def stim_and_check():
        reset.next = 1
        yield clk.negedge
        reset.next = 0
        yield clk.negedge
 
        self.assertEqual(full_o, 0)
        self.assertEqual(data_avail_o, 0)
 
        # write fifo full
        yield clk.negedge
        for i in range(SIZE+1):
 
          data_i.next = i
          wen_i.next = 1
          yield clk.negedge
 
          if i < SIZE-1:
            msg = "full (0): %d at %d"%(full_o, now())
            self.assertEqual(full_o, 0, msg)
          else:
            msg = "full (1): %d at %d"%(full_o, now())
            self.assertEqual(full_o, 1, msg)
 
        wen_i.next = 0
 
        # read fifo back empty
        yield clk.negedge
        rden_i.next = 1
 
        yield clk.posedge
        self.assertEqual(full_o, 1)
 
        yield delay(1)
        self.assertEqual(full_o, 0)
 
        for i in range(SIZE+1):
          yield clk.negedge
 
          if i < SIZE-1:
            msg = "i: %d data_o: %d at %d"%(i, data_o, now())
            self.assertEqual(data_o, i, msg)
          elif i == SIZE-1:
            msg = "i: %d data_o: %d at %d"%(i, data_o, now())
            self.assertEqual(data_o, SIZE-1, msg)
            self.assertEqual(data_avail_o, 0)
 
        rden_i.next = 0
        yield clk.negedge
 
        #
        # fill 2 words, read/write 3 words, should not get full
        #
 
        # 1st data
        data_i.next = 1
        wen_i.next = 1
        yield clk.negedge
 
        self.assertEqual(data_avail_o, 1)
 
        # 2nd data
        data_i.next = 2
        yield clk.negedge
 
        # write and read
        rden_i.next = 1
        for i in range(3):
          data_i.next = 11 + i
          yield clk.negedge
 
          self.assertEqual(full_o, 0)
          self.assertEqual(data_avail_o, 1)
 
          if i == 0:
            self.assertEqual(data_o, 1)
          elif i == 1:
            self.assertEqual(data_o, 2)
          elif i == 2:
            self.assertEqual(data_o, 11)
 
        wen_i.next = 0
 
        yield clk.negedge
        self.assertEqual(full_o, 0)
        self.assertEqual(data_avail_o, 1)
        self.assertEqual(data_o, 12)
 
        yield clk.negedge
        self.assertEqual(full_o, 0)
        self.assertEqual(data_avail_o, 0)
        self.assertEqual(data_o, 13)
 
 
        yield clk.negedge
        self.assertEqual(full_o, 0)
        self.assertEqual(data_avail_o, 0)
        self.assertEqual(data_o, 13)
 
        rden_i.next = 0
 
        raise StopSimulation
 
      return instances()
 
    tb = bench()
    #tb = traceSignals(bench)
    sim = Simulation(tb)
    sim.run()
 
########################################################################
# main
if __name__ == '__main__':
  suite = unittest.TestLoader().loadTestsFromTestCase(TestFifo)
  unittest.TextTestRunner(verbosity=2).run(suite)

Line No.	Rev	Author	Line
1	30	dannori	`#!/usr/bin/env python`
2
3			`import unittest`
4			`import os`
5			`from myhdl import *`
6
7			`if __name__ == '__main__':`
8			`import sys`
9			`sys.path.append('../')`
10
11			`from rtl.fifo_sync import fifo_sync`
12
13
14			`class TestFifo(unittest.TestCase):`
15
16			`def test_fifo_simple(self):`
17
18			`def bench():`
19
20			`DWIDTH = 4`
21			`SIZE = 4`
22
23			`clk, reset, full_o, wen_i, data_avail_o, rden_i = \`
24			`[Signal(bool(0)) for i in range(6)]`
25
26			`data_i, data_o = [Signal(intbv(0)[DWIDTH:]) for i in range(2)]`
27
28			`fifo_inst = fifo_sync( clk, reset,`
29			`full_o, wen_i, data_i,`
30			`data_avail_o, rden_i, data_o,`
31			`DWIDTH,SIZE)`
32
33			`@always(delay(10))`
34			`def clkgen():`
35			`clk.next = not clk`
36
37			`@instance`
38			`def stim_and_check():`
39			`reset.next = 1`
40			`yield clk.negedge`
41			`reset.next = 0`
42			`yield clk.negedge`
43
44			`self.assertEqual(full_o, 0)`
45			`self.assertEqual(data_avail_o, 0)`
46
47			`# write fifo full`
48			`yield clk.negedge`
49			`for i in range(SIZE+1):`
50
51			`data_i.next = i`
52			`wen_i.next = 1`
53			`yield clk.negedge`
54
55			`if i < SIZE-1:`
56			`msg = "full (0): %d at %d"%(full_o, now())`
57			`self.assertEqual(full_o, 0, msg)`
58			`else:`
59			`msg = "full (1): %d at %d"%(full_o, now())`
60			`self.assertEqual(full_o, 1, msg)`
61
62			`wen_i.next = 0`
63
64			`# read fifo back empty`
65			`yield clk.negedge`
66			`rden_i.next = 1`
67
68			`yield clk.posedge`
69			`self.assertEqual(full_o, 1)`
70
71			`yield delay(1)`
72			`self.assertEqual(full_o, 0)`
73
74			`for i in range(SIZE+1):`
75			`yield clk.negedge`
76
77			`if i < SIZE-1:`
78			`msg = "i: %d data_o: %d at %d"%(i, data_o, now())`
79			`self.assertEqual(data_o, i, msg)`
80			`elif i == SIZE-1:`
81			`msg = "i: %d data_o: %d at %d"%(i, data_o, now())`
82			`self.assertEqual(data_o, SIZE-1, msg)`
83			`self.assertEqual(data_avail_o, 0)`
84
85			`rden_i.next = 0`
86			`yield clk.negedge`
87
88			`#`
89			`# fill 2 words, read/write 3 words, should not get full`
90			`#`
91
92			`# 1st data`
93			`data_i.next = 1`
94			`wen_i.next = 1`
95			`yield clk.negedge`
96
97			`self.assertEqual(data_avail_o, 1)`
98
99			`# 2nd data`
100			`data_i.next = 2`
101			`yield clk.negedge`
102
103			`# write and read`
104			`rden_i.next = 1`
105			`for i in range(3):`
106			`data_i.next = 11 + i`
107			`yield clk.negedge`
108
109			`self.assertEqual(full_o, 0)`
110			`self.assertEqual(data_avail_o, 1)`
111
112			`if i == 0:`
113			`self.assertEqual(data_o, 1)`
114			`elif i == 1:`
115			`self.assertEqual(data_o, 2)`
116			`elif i == 2:`
117			`self.assertEqual(data_o, 11)`
118
119			`wen_i.next = 0`
120
121			`yield clk.negedge`
122			`self.assertEqual(full_o, 0)`
123			`self.assertEqual(data_avail_o, 1)`
124			`self.assertEqual(data_o, 12)`
125
126			`yield clk.negedge`
127			`self.assertEqual(full_o, 0)`
128			`self.assertEqual(data_avail_o, 0)`
129			`self.assertEqual(data_o, 13)`
130
131
132			`yield clk.negedge`
133			`self.assertEqual(full_o, 0)`
134			`self.assertEqual(data_avail_o, 0)`
135			`self.assertEqual(data_o, 13)`
136
137			`rden_i.next = 0`
138
139			`raise StopSimulation`
140
141			`return instances()`
142
143			`tb = bench()`
144			`#tb = traceSignals(bench)`
145			`sim = Simulation(tb)`
146			`sim.run()`
147
148			`########################################################################`
149			`# main`
150			`if __name__ == '__main__':`
151			`suite = unittest.TestLoader().loadTestsFromTestCase(TestFifo)`
152			`unittest.TextTestRunner(verbosity=2).run(suite)`

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[/] [dmt_tx/] [trunk/] [myhdl/] [test/] [test_fifo_sync.py] - Blame information for rev 30