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[/] [double_fpu/] [branches/] [avendor/] [fpu_round.v] - Blame information for rev 13

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1 2 davidklun
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  FPU                                                        ////
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////  Floating Point Unit (Double precision)                     ////
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////                                                             ////
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////  Author: David Lundgren                                     ////
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////          davidklun@gmail.com                                ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2009 David Lundgren                           ////
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////                  davidklun@gmail.com                        ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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module fpu_round( clk, rst, enable, round_mode, sign_term,
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mantissa_term, exponent_term, round_out, exponent_final);
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input           clk;
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input           rst;
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input           enable;
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input   [1:0]    round_mode;
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input           sign_term;
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input   [55:0]   mantissa_term;
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input   [11:0]   exponent_term;
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output  [63:0]   round_out;
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output  [11:0]   exponent_final;
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wire    [55:0] rounding_amount = { 53'b0, 1'b1, 2'b0};
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wire    round_nearest = (round_mode == 2'b00);
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wire    round_to_zero = (round_mode == 2'b01);
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wire    round_to_pos_inf = (round_mode == 2'b10);
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wire    round_to_neg_inf = (round_mode == 2'b11);
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wire    round_nearest_trigger = round_nearest &  mantissa_term[1];
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wire    round_to_pos_inf_trigger = !sign_term & |mantissa_term[1:0];
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wire    round_to_neg_inf_trigger = sign_term & |mantissa_term[1:0];
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wire    round_trigger = ( round_nearest & round_nearest_trigger)
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                                                | (round_to_pos_inf & round_to_pos_inf_trigger)
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                                                | (round_to_neg_inf & round_to_neg_inf_trigger);
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reg       [55:0] sum_round;
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wire    sum_round_overflow = sum_round[55];
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        // will be 0 if no carry, 1 if overflow from the rounding unit
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        // overflow from rounding is extremely rare, but possible
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reg       [55:0] sum_round_2;
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reg   [11:0] exponent_round;
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reg       [55:0] sum_final;
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reg   [11:0] exponent_final;
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reg   [63:0] round_out;
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always @(posedge clk)
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        begin
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                if (rst) begin
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                        sum_round <= 0;
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                        sum_round_2 <= 0;
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                        exponent_round <= 0;
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                        sum_final <= 0;
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                        exponent_final <= 0;
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                        round_out <= 0;
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                end
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                else begin
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                        sum_round <= rounding_amount + mantissa_term;
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                        sum_round_2 <= sum_round_overflow ? sum_round >> 1 : sum_round;
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                        exponent_round <= sum_round_overflow ? (exponent_term + 1) : exponent_term;
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                        sum_final <= round_trigger ? sum_round_2 : mantissa_term;
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                        exponent_final <= round_trigger ? exponent_round : exponent_term;
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                        round_out <= { sign_term, exponent_final[10:0], sum_final[53:2] };
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                        end
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        end
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endmodule

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