1 |
6 |
davidklun |
/////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// FPU ////
|
4 |
|
|
//// Floating Point Unit (Double precision) ////
|
5 |
|
|
//// ////
|
6 |
|
|
//// Author: David Lundgren ////
|
7 |
|
|
//// davidklun@gmail.com ////
|
8 |
|
|
//// ////
|
9 |
|
|
/////////////////////////////////////////////////////////////////////
|
10 |
|
|
//// ////
|
11 |
|
|
//// Copyright (C) 2009 David Lundgren ////
|
12 |
|
|
//// davidklun@gmail.com ////
|
13 |
|
|
//// ////
|
14 |
|
|
//// This source file may be used and distributed without ////
|
15 |
|
|
//// restriction provided that this copyright statement is not ////
|
16 |
|
|
//// removed from the file and that any derivative work contains ////
|
17 |
|
|
//// the original copyright notice and the associated disclaimer.////
|
18 |
|
|
//// ////
|
19 |
|
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
20 |
|
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
21 |
|
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
22 |
|
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
23 |
|
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
24 |
|
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
25 |
|
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
26 |
|
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
27 |
|
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
28 |
|
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
29 |
|
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
30 |
|
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
31 |
|
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
32 |
|
|
//// ////
|
33 |
|
|
/////////////////////////////////////////////////////////////////////
|
34 |
|
|
|
35 |
|
|
// fpu_op, add = 0, subtract = 1
|
36 |
8 |
davidklun |
// rmode = 00 (nearest), 01 (to zero), 10 (+ infinity), 11 (- infinity)
|
37 |
6 |
davidklun |
|
38 |
|
|
`timescale 1ns / 100ps
|
39 |
|
|
|
40 |
8 |
davidklun |
module fpu_addsub( clk, rst, enable, fpu_op, rmode, opa, opb, out, ready);
|
41 |
6 |
davidklun |
input clk;
|
42 |
|
|
input rst;
|
43 |
|
|
input enable;
|
44 |
|
|
input fpu_op;
|
45 |
8 |
davidklun |
input [1:0] rmode;
|
46 |
6 |
davidklun |
input [63:0] opa, opb;
|
47 |
|
|
output [63:0] out;
|
48 |
|
|
output ready;
|
49 |
|
|
|
50 |
|
|
|
51 |
8 |
davidklun |
|
52 |
|
|
reg [63:0] outfp, out;
|
53 |
|
|
reg [1:0] rm_1, rm_2, rm_3, rm_4, rm_5, rm_6, rm_7, rm_8, rm_9;
|
54 |
|
|
reg [1:0] rm_10, rm_11, rm_12, rm_13, rm_14, rm_15, rm_16;
|
55 |
|
|
reg sign, sign_a, sign_b, fpu_op_1, fpu_op_2, fpu_op_3, fpu_op_final;
|
56 |
6 |
davidklun |
reg fpuf_2, fpuf_3, fpuf_4, fpuf_5, fpuf_6, fpuf_7, fpuf_8, fpuf_9, fpuf_10;
|
57 |
8 |
davidklun |
reg fpuf_11, fpuf_12, fpuf_13, fpuf_14, fpuf_15, fpuf_16;
|
58 |
|
|
reg fpuf_17, fpuf_18, fpuf_19, fpuf_20, fpuf_21;
|
59 |
6 |
davidklun |
reg sign_a2, sign_a3, sign_b2, sign_b3, sign_2, sign_3, sign_4, sign_5, sign_6;
|
60 |
|
|
reg sign_7, sign_8, sign_9, sign_10, sign_11, sign_12;
|
61 |
8 |
davidklun |
reg sign_13, sign_14, sign_15, sign_16, sign_17, sign_18, sign_19;
|
62 |
6 |
davidklun |
reg [10:0] exponent_a, exponent_b, expa_2, expb_2, expa_3, expb_3;
|
63 |
|
|
reg [51:0] mantissa_a, mantissa_b, mana_2, mana_3, manb_2, manb_3;
|
64 |
|
|
reg expa_et_inf, expb_et_inf, input_is_inf, in_inf2, in_inf3, in_inf4, in_inf5;
|
65 |
|
|
reg in_inf6, in_inf7, in_inf8, in_inf9, in_inf10, in_inf11, in_inf12, in_inf13;
|
66 |
8 |
davidklun |
reg in_inf14, in_inf15, in_inf16, in_inf17, in_inf18, in_inf19, in_inf20;
|
67 |
|
|
reg in_inf21, expa_gt_expb, expa_et_expb, mana_gtet_manb, a_gtet_b;
|
68 |
|
|
reg [10:0] exponent_small, exponent_large, expl_2, expl_3, expl_4;
|
69 |
6 |
davidklun |
reg [10:0] expl_5, expl_6, expl_7, expl_8, expl_9, expl_10, expl_11;
|
70 |
|
|
reg [51:0] mantissa_small, mantissa_large;
|
71 |
|
|
reg [51:0] mantissa_small_2, mantissa_large_2;
|
72 |
|
|
reg [51:0] mantissa_small_3, mantissa_large_3;
|
73 |
|
|
reg exp_small_et0, exp_large_et0, exp_small_et0_2, exp_large_et0_2;
|
74 |
8 |
davidklun |
reg [10:0] exponent_diff, exponent_diff_2, exponent_diff_3;
|
75 |
|
|
reg [107:0] bits_shifted_out, bits_shifted_out_2;
|
76 |
|
|
reg bits_shifted;
|
77 |
|
|
reg [55:0] large_add, large_add_2, large_add_3, small_add;
|
78 |
|
|
reg [55:0] small_shift, small_shift_2, small_shift_3, small_shift_4;
|
79 |
|
|
reg [55:0] large_add_4, large_add_5;
|
80 |
6 |
davidklun |
reg small_shift_nonzero;
|
81 |
|
|
reg small_is_nonzero, small_is_nonzero_2, small_is_nonzero_3;
|
82 |
|
|
reg small_fraction_enable;
|
83 |
8 |
davidklun |
wire [55:0] small_shift_LSB = { 55'b0, 1'b1 };
|
84 |
|
|
reg [55:0] sum, sum_2, sum_3, sum_4, sum_5;
|
85 |
|
|
reg [55:0] sum_6, sum_7, sum_8, sum_9, sum_10, sum_11;
|
86 |
|
|
reg sum_overflow, sumround_overflow, sum_lsb, sum_lsb_2;
|
87 |
|
|
reg [10:0] exponent_add, exp_add_2, exponent_sub, exp_sub_2;
|
88 |
|
|
reg [10:0] exp_sub_3, exp_sub_4, exp_sub_5, exp_sub_6, exp_sub_7;
|
89 |
|
|
reg [10:0] exp_sub_8, exp_add_3, exp_add_4, exp_add_5, exp_add_6;
|
90 |
|
|
reg [10:0] exp_add_7, exp_add_8, exp_add_9;
|
91 |
6 |
davidklun |
reg [5:0] diff_shift, diff_shift_2;
|
92 |
8 |
davidklun |
reg [55:0] diff, diff_2, diff_3, diff_4, diff_5;
|
93 |
|
|
reg [55:0] diff_6, diff_7, diff_8, diff_9, diff_10, diff_11;
|
94 |
|
|
reg diffshift_gt_exponent, diffshift_et_55, diffround_overflow;
|
95 |
|
|
reg round_nearest_mode, round_posinf_mode, round_neginf_mode;
|
96 |
|
|
reg round_nearest_trigger, round_nearest_exception;
|
97 |
|
|
reg round_nearest_enable, round_posinf_trigger, round_posinf_enable;
|
98 |
|
|
reg round_neginf_trigger, round_neginf_enable, round_enable;
|
99 |
6 |
davidklun |
reg ready, count_ready, count_ready_0;
|
100 |
|
|
reg [4:0] count;
|
101 |
|
|
|
102 |
|
|
always @(posedge clk)
|
103 |
|
|
begin
|
104 |
|
|
if (rst) begin
|
105 |
8 |
davidklun |
fpu_op_1 <= 0; fpu_op_final <= 0; fpu_op_2 <= 0;
|
106 |
|
|
fpu_op_3 <= 0; fpuf_2 <= 0; fpuf_3 <= 0; fpuf_4 <= 0;
|
107 |
6 |
davidklun |
fpuf_5 <= 0; fpuf_6 <= 0; fpuf_7 <= 0; fpuf_8 <= 0; fpuf_9 <= 0;
|
108 |
|
|
fpuf_10 <= 0; fpuf_11 <= 0; fpuf_12 <= 0; fpuf_13 <= 0; fpuf_14 <= 0;
|
109 |
8 |
davidklun |
fpuf_15 <= 0; fpuf_16 <= 0; fpuf_17 <= 0; fpuf_18 <= 0; fpuf_19 <= 0;
|
110 |
|
|
fpuf_20 <= 0; fpuf_21 <= 0;
|
111 |
|
|
rm_1 <= 0; rm_2 <= 0; rm_3 <= 0; rm_4 <= 0; rm_5 <= 0;
|
112 |
|
|
rm_6 <= 0; rm_7 <= 0; rm_8 <= 0; rm_9 <= 0; rm_10 <= 0; rm_11 <= 0;
|
113 |
|
|
rm_12 <= 0; rm_13 <= 0; rm_14 <= 0; rm_15 <= 0; rm_16 <= 0; sign_a <= 0;
|
114 |
|
|
sign_b <= 0; sign_a2 <= 0; sign_b2 <= 0; sign_a3 <= 0; sign_b3 <= 0;
|
115 |
6 |
davidklun |
exponent_a <= 0; exponent_b <= 0; expa_2 <= 0; expa_3 <= 0;
|
116 |
|
|
expb_2 <= 0; expb_3 <= 0; mantissa_a <= 0; mantissa_b <= 0; mana_2 <= 0; mana_3 <= 0;
|
117 |
|
|
manb_2 <= 0; manb_3 <= 0; expa_et_inf <= 0; expb_et_inf <= 0;
|
118 |
|
|
input_is_inf <= 0; in_inf2 <= 0; in_inf3 <= 0; in_inf4 <= 0; in_inf5 <= 0;
|
119 |
|
|
in_inf6 <= 0; in_inf7 <= 0; in_inf8 <= 0; in_inf9 <= 0; in_inf10 <= 0;
|
120 |
|
|
in_inf11 <= 0; in_inf12 <= 0; in_inf13 <= 0; in_inf14 <= 0; in_inf15 <= 0;
|
121 |
8 |
davidklun |
in_inf16 <= 0; in_inf17 <= 0; in_inf18 <= 0; in_inf19 <= 0; in_inf20 <= 0;
|
122 |
|
|
in_inf21 <= 0; expa_gt_expb <= 0; expa_et_expb <= 0; mana_gtet_manb <= 0;
|
123 |
6 |
davidklun |
a_gtet_b <= 0; sign <= 0; sign_2 <= 0; sign_3 <= 0; sign_4 <= 0; sign_5 <= 0;
|
124 |
|
|
sign_6 <= 0; sign_7 <= 0; sign_8 <= 0; sign_9 <= 0;
|
125 |
8 |
davidklun |
sign_10 <= 0; sign_11 <= 0; sign_12 <= 0; sign_13 <= 0; sign_14 <= 0;
|
126 |
|
|
sign_15 <= 0; sign_16 <= 0; sign_17 <= 0; sign_18 <= 0; sign_19 <= 0;
|
127 |
|
|
exponent_small <= 0; exponent_large <= 0; expl_2 <= 0;
|
128 |
6 |
davidklun |
expl_3 <= 0; expl_4 <= 0; expl_5 <= 0; expl_6 <= 0; expl_7 <= 0;
|
129 |
|
|
expl_8 <= 0; expl_9 <= 0; expl_10 <= 0; expl_11 <= 0;
|
130 |
|
|
exp_small_et0 <= 0; exp_large_et0 <= 0;
|
131 |
|
|
exp_small_et0_2 <= 0; exp_large_et0_2 <= 0;
|
132 |
|
|
mantissa_small <= 0; mantissa_large <= 0;
|
133 |
|
|
mantissa_small_2 <= 0; mantissa_large_2 <= 0;
|
134 |
|
|
mantissa_small_3 <= 0; mantissa_large_3 <= 0;
|
135 |
|
|
exponent_diff <= 0; exponent_diff_2 <= 0; exponent_diff_3 <= 0;
|
136 |
8 |
davidklun |
bits_shifted_out <= 0;
|
137 |
|
|
bits_shifted_out_2 <= 0; bits_shifted <= 0;
|
138 |
|
|
large_add <= 0; large_add_2 <= 0;
|
139 |
6 |
davidklun |
large_add_3 <= 0; large_add_4 <= 0; large_add_5 <= 0; small_add <= 0;
|
140 |
|
|
small_shift <= 0; small_shift_2 <= 0; small_shift_3 <= 0;
|
141 |
|
|
small_shift_4 <= 0; small_shift_nonzero <= 0;
|
142 |
|
|
small_is_nonzero <= 0; small_is_nonzero_2 <= 0; small_is_nonzero_3 <= 0;
|
143 |
|
|
small_fraction_enable <= 0;
|
144 |
|
|
sum <= 0; sum_2 <= 0; sum_overflow <= 0; sum_3 <= 0; sum_4 <= 0;
|
145 |
8 |
davidklun |
sum_5 <= 0; sum_6 <= 0; sum_7 <= 0; sum_8 <= 0; sum_9 <= 0; sum_10 <= 0;
|
146 |
|
|
sum_11 <= 0; sumround_overflow <= 0; sum_lsb <= 0; sum_lsb_2 <= 0;
|
147 |
|
|
exponent_add <= 0; exp_add_2 <= 0; exp_add_3 <= 0; exp_add_4 <= 0;
|
148 |
|
|
exp_add_5 <= 0; exp_add_6 <= 0; exp_add_7 <= 0; exp_add_8 <= 0;
|
149 |
|
|
exp_add_9 <= 0; diff_shift_2 <= 0; diff <= 0;
|
150 |
|
|
diffshift_gt_exponent <= 0; diffshift_et_55 <= 0; diff_2 <= 0;
|
151 |
|
|
diff_3 <= 0; diff_4 <= 0; diff_5 <= 0; diff_6 <= 0; diff_7 <= 0; diff_8 <= 0;
|
152 |
|
|
diff_9 <= 0; diff_10 <= 0;
|
153 |
|
|
diff_11 <= 0; diffround_overflow <= 0; exponent_sub <= 0;
|
154 |
|
|
exp_sub_2 <= 0; exp_sub_3 <= 0; exp_sub_4 <= 0; exp_sub_5 <= 0;
|
155 |
|
|
exp_sub_6 <= 0; exp_sub_7 <= 0; exp_sub_8 <= 0; outfp <= 0;
|
156 |
|
|
round_nearest_mode <= 0; round_posinf_mode <= 0; round_neginf_mode <= 0; round_nearest_trigger <= 0;
|
157 |
|
|
round_nearest_exception <= 0; round_nearest_enable <= 0; round_posinf_trigger <= 0; round_posinf_enable <= 0;
|
158 |
|
|
round_neginf_trigger <= 0; round_neginf_enable <= 0; round_enable <= 0;
|
159 |
6 |
davidklun |
end
|
160 |
|
|
else if (enable) begin
|
161 |
|
|
fpu_op_1 <= fpu_op; fpu_op_final <= fpu_op_1 ^ (sign_a ^ sign_b);
|
162 |
|
|
fpuf_2 <= fpu_op_final; fpuf_3 <= fpuf_2; fpuf_4 <= fpuf_3;
|
163 |
|
|
fpuf_5 <= fpuf_4; fpuf_6 <= fpuf_5; fpuf_7 <= fpuf_6; fpuf_8 <= fpuf_7;
|
164 |
|
|
fpuf_9 <= fpuf_8; fpuf_10 <= fpuf_9; fpuf_11 <= fpuf_10; fpuf_12 <= fpuf_11;
|
165 |
|
|
fpuf_13 <= fpuf_12; fpuf_14 <= fpuf_13; fpuf_15 <= fpuf_14;
|
166 |
8 |
davidklun |
fpuf_16 <= fpuf_15; fpuf_17 <= fpuf_16; fpuf_18 <= fpuf_17;
|
167 |
|
|
fpuf_19 <= fpuf_18; fpuf_20 <= fpuf_19; fpuf_21 <= fpuf_20;
|
168 |
|
|
fpu_op_2 <= fpu_op_1; fpu_op_3 <= fpu_op_2;
|
169 |
|
|
rm_1 <= rmode; rm_2 <= rm_1; rm_3 <= rm_2; rm_4 <= rm_3;
|
170 |
|
|
rm_5 <= rm_4; rm_6 <= rm_5; rm_7 <= rm_6; rm_8 <= rm_7; rm_9 <= rm_8;
|
171 |
|
|
rm_10 <= rm_9; rm_11 <= rm_10; rm_12 <= rm_11; rm_13 <= rm_12;
|
172 |
|
|
rm_14 <= rm_13; rm_15 <= rm_14; rm_16 <= rm_15;
|
173 |
6 |
davidklun |
sign_a <= opa[63]; sign_b <= opb[63]; sign_a2 <= sign_a;
|
174 |
|
|
sign_b2 <= sign_b; sign_a3 <= sign_a2; sign_b3 <= sign_b2;
|
175 |
|
|
exponent_a <= opa[62:52]; expa_2 <= exponent_a; expa_3 <= expa_2;
|
176 |
|
|
exponent_b <= opb[62:52]; expb_2 <= exponent_b; expb_3 <= expb_2;
|
177 |
|
|
mantissa_a <= opa[51:0]; mana_2 <= mantissa_a; mana_3 <= mana_2;
|
178 |
|
|
mantissa_b <= opb[51:0]; manb_2 <= mantissa_b; manb_3 <= manb_2;
|
179 |
|
|
expa_et_inf <= exponent_a == 2047;
|
180 |
|
|
expb_et_inf <= exponent_b == 2047;
|
181 |
|
|
input_is_inf <= expa_et_inf | expb_et_inf; in_inf2 <= input_is_inf;
|
182 |
|
|
in_inf3 <= in_inf2; in_inf4 <= in_inf3; in_inf5 <= in_inf4; in_inf6 <= in_inf5;
|
183 |
|
|
in_inf7 <= in_inf6; in_inf8 <= in_inf7; in_inf9 <= in_inf8; in_inf10 <= in_inf9;
|
184 |
|
|
in_inf11 <= in_inf10; in_inf12 <= in_inf11; in_inf13 <= in_inf12;
|
185 |
8 |
davidklun |
in_inf14 <= in_inf13; in_inf15 <= in_inf14; in_inf16 <= in_inf15;
|
186 |
|
|
in_inf17 <= in_inf16; in_inf18 <= in_inf17; in_inf19 <= in_inf18;
|
187 |
|
|
in_inf20 <= in_inf19; in_inf21 <= in_inf20;
|
188 |
6 |
davidklun |
expa_gt_expb <= exponent_a > exponent_b;
|
189 |
|
|
expa_et_expb <= exponent_a == exponent_b;
|
190 |
|
|
mana_gtet_manb <= mantissa_a >= mantissa_b;
|
191 |
|
|
a_gtet_b <= expa_gt_expb | (expa_et_expb & mana_gtet_manb);
|
192 |
|
|
sign <= a_gtet_b ? sign_a3 :!sign_b3 ^ (fpu_op_3 == 0);
|
193 |
|
|
sign_2 <= sign; sign_3 <= sign_2; sign_4 <= sign_3; sign_5 <= sign_4;
|
194 |
|
|
sign_6 <= sign_5; sign_7 <= sign_6; sign_8 <= sign_7; sign_9 <= sign_8;
|
195 |
|
|
sign_10 <= sign_9; sign_11 <= sign_10; sign_12 <= sign_11;
|
196 |
8 |
davidklun |
sign_13 <= sign_12; sign_14 <= sign_13; sign_15 <= sign_14;
|
197 |
|
|
sign_16 <= sign_15; sign_17 <= sign_16; sign_18 <= sign_17;
|
198 |
|
|
sign_19 <= sign_18;
|
199 |
6 |
davidklun |
exponent_small <= a_gtet_b ? expb_3 : expa_3;
|
200 |
|
|
exponent_large <= a_gtet_b ? expa_3 : expb_3;
|
201 |
|
|
expl_2 <= exponent_large; expl_3 <= expl_2; expl_4 <= expl_3;
|
202 |
|
|
expl_5 <= expl_4; expl_6 <= expl_5; expl_7 <= expl_6; expl_8 <= expl_7;
|
203 |
|
|
expl_9 <= expl_8; expl_10 <= expl_9; expl_11 <= expl_10;
|
204 |
|
|
exp_small_et0 <= exponent_small == 0;
|
205 |
|
|
exp_large_et0 <= exponent_large == 0;
|
206 |
|
|
exp_small_et0_2 <= exp_small_et0;
|
207 |
|
|
exp_large_et0_2 <= exp_large_et0;
|
208 |
|
|
mantissa_small <= a_gtet_b ? manb_3 : mana_3;
|
209 |
|
|
mantissa_large <= a_gtet_b ? mana_3 : manb_3;
|
210 |
|
|
mantissa_small_2 <= mantissa_small;
|
211 |
|
|
mantissa_large_2 <= mantissa_large;
|
212 |
|
|
mantissa_small_3 <= exp_small_et0 ? 0 : mantissa_small_2;
|
213 |
|
|
mantissa_large_3 <= exp_large_et0 ? 0 : mantissa_large_2;
|
214 |
|
|
exponent_diff <= exponent_large - exponent_small;
|
215 |
|
|
exponent_diff_2 <= exponent_diff;
|
216 |
|
|
exponent_diff_3 <= exponent_diff_2;
|
217 |
8 |
davidklun |
bits_shifted_out <= exp_small_et0 ? 108'b0 : { 1'b1, mantissa_small_2, 55'b0 };
|
218 |
|
|
bits_shifted_out_2 <= bits_shifted_out >> exponent_diff_2;
|
219 |
|
|
bits_shifted <= |bits_shifted_out_2[52:0];
|
220 |
|
|
large_add <= { 1'b0, !exp_large_et0_2, mantissa_large_3, 2'b0};
|
221 |
6 |
davidklun |
large_add_2 <= large_add; large_add_3 <= large_add_2;
|
222 |
|
|
large_add_4 <= large_add_3; large_add_5 <= large_add_4;
|
223 |
8 |
davidklun |
small_add <= { 1'b0, !exp_small_et0_2, mantissa_small_3, 2'b0};
|
224 |
6 |
davidklun |
small_shift <= small_add >> exponent_diff_3;
|
225 |
8 |
davidklun |
small_shift_2 <= { small_shift[55:1], (bits_shifted | small_shift[0]) };
|
226 |
|
|
small_shift_3 <= small_shift_2;
|
227 |
6 |
davidklun |
small_fraction_enable <= small_is_nonzero_3 & !small_shift_nonzero;
|
228 |
|
|
small_shift_4 <= small_fraction_enable ? small_shift_LSB : small_shift_3;
|
229 |
8 |
davidklun |
small_shift_nonzero <= |small_shift[54:0];
|
230 |
6 |
davidklun |
small_is_nonzero <= !exp_small_et0_2;
|
231 |
|
|
small_is_nonzero_2 <= small_is_nonzero; small_is_nonzero_3 <= small_is_nonzero_2;
|
232 |
|
|
sum <= large_add_5 + small_shift_4;
|
233 |
8 |
davidklun |
sum_overflow <= sum[55];
|
234 |
|
|
sum_2 <= sum; sum_lsb <= sum[0];
|
235 |
|
|
sum_3 <= sum_overflow ? sum_2 >> 1 : sum_2; sum_lsb_2 <= sum_lsb;
|
236 |
|
|
sum_4 <= { sum_3[55:1], sum_lsb_2 | sum_3[0] };
|
237 |
|
|
sum_5 <= sum_4; sum_6 <= sum_5; sum_7 <= sum_6; sum_8 <= sum_7;
|
238 |
6 |
davidklun |
exponent_add <= sum_overflow ? expl_10 + 1: expl_10;
|
239 |
8 |
davidklun |
exp_add_2 <= exponent_add;
|
240 |
6 |
davidklun |
diff_shift_2 <= diff_shift;
|
241 |
8 |
davidklun |
diff <= large_add_5 - small_shift_4; diff_2 <= diff; diff_3 <= diff_2;
|
242 |
6 |
davidklun |
diffshift_gt_exponent <= diff_shift > expl_10;
|
243 |
8 |
davidklun |
diffshift_et_55 <= diff_shift_2 == 55;
|
244 |
6 |
davidklun |
diff_4 <= diffshift_gt_exponent ? diff_3 << expl_11 : diff_3 << diff_shift_2;
|
245 |
8 |
davidklun |
diff_5 <= diff_4; diff_6 <= diff_5; diff_7 <= diff_6; diff_8 <= diff_7;
|
246 |
6 |
davidklun |
exponent_sub <= diffshift_gt_exponent ? 0 : (expl_11 - diff_shift_2);
|
247 |
8 |
davidklun |
exp_sub_2 <= diffshift_et_55 ? 0 : exponent_sub;
|
248 |
|
|
round_nearest_mode <= rm_16 == 2'b00;
|
249 |
|
|
round_posinf_mode <= rm_16 == 2'b10;
|
250 |
|
|
round_neginf_mode <= rm_16 == 2'b11;
|
251 |
|
|
round_nearest_trigger <= fpuf_15 ? diff_5[1] : sum_5[1];
|
252 |
|
|
round_nearest_exception <= fpuf_15 ? !diff_5[0] & !diff_5[2] : !sum_5[0] & !sum_5[2];
|
253 |
|
|
round_nearest_enable <= round_nearest_mode & round_nearest_trigger & !round_nearest_exception;
|
254 |
|
|
round_posinf_trigger <= fpuf_15 ? |diff_5[1:0] & !sign_13 : |sum_5[1:0] & !sign_13;
|
255 |
|
|
round_posinf_enable <= round_posinf_mode & round_posinf_trigger;
|
256 |
|
|
round_neginf_trigger <= fpuf_15 ? |diff_5[1:0] & sign_13 : |sum_5[1:0] & sign_13;
|
257 |
|
|
round_neginf_enable <= round_neginf_mode & round_neginf_trigger;
|
258 |
|
|
round_enable <= round_posinf_enable | round_neginf_enable | round_nearest_enable;
|
259 |
|
|
sum_9 <= round_enable ? sum_8 + 4 : sum_8;
|
260 |
|
|
sumround_overflow <= sum_9[55]; sum_10 <= sum_9;
|
261 |
|
|
sum_11 <= sumround_overflow ? sum_10 >> 1 : sum_10;
|
262 |
|
|
diff_9 <= round_enable ? diff_8 + 4 : diff_8;
|
263 |
|
|
diffround_overflow <= diff_9[55]; diff_10 <= diff_9;
|
264 |
|
|
diff_11 <= diffround_overflow ? diff_10 >> 1 : diff_10;
|
265 |
|
|
exp_add_3 <= exp_add_2; exp_add_4 <= exp_add_3; exp_add_5 <= exp_add_4;
|
266 |
|
|
exp_add_6 <= exp_add_5; exp_add_7 <= exp_add_6; exp_add_8 <= exp_add_7;
|
267 |
|
|
exp_add_9 <= sumround_overflow ? exp_add_8 + 1 : exp_add_8;
|
268 |
|
|
exp_sub_3 <= exp_sub_2; exp_sub_4 <= exp_sub_3; exp_sub_5 <= exp_sub_4;
|
269 |
|
|
exp_sub_6 <= exp_sub_5; exp_sub_7 <= exp_sub_6;
|
270 |
|
|
exp_sub_8 <= diffround_overflow ? exp_sub_7 + 1 : exp_sub_7;
|
271 |
|
|
outfp <= fpuf_21 ? {sign_19, exp_sub_8, diff_11[53:2]} : {sign_19, exp_add_9, sum_11[53:2]};
|
272 |
|
|
end
|
273 |
6 |
davidklun |
end
|
274 |
|
|
|
275 |
|
|
|
276 |
|
|
|
277 |
|
|
always @(posedge clk)
|
278 |
8 |
davidklun |
casex(diff[54:0])
|
279 |
|
|
55'b1??????????????????????????????????????????????????????: diff_shift <= 0;
|
280 |
|
|
55'b01?????????????????????????????????????????????????????: diff_shift <= 1;
|
281 |
|
|
55'b001????????????????????????????????????????????????????: diff_shift <= 2;
|
282 |
|
|
55'b0001???????????????????????????????????????????????????: diff_shift <= 3;
|
283 |
|
|
55'b00001??????????????????????????????????????????????????: diff_shift <= 4;
|
284 |
|
|
55'b000001?????????????????????????????????????????????????: diff_shift <= 5;
|
285 |
|
|
55'b0000001????????????????????????????????????????????????: diff_shift <= 6;
|
286 |
|
|
55'b00000001???????????????????????????????????????????????: diff_shift <= 7;
|
287 |
|
|
55'b000000001??????????????????????????????????????????????: diff_shift <= 8;
|
288 |
|
|
55'b0000000001?????????????????????????????????????????????: diff_shift <= 9;
|
289 |
|
|
55'b00000000001????????????????????????????????????????????: diff_shift <= 10;
|
290 |
|
|
55'b000000000001???????????????????????????????????????????: diff_shift <= 11;
|
291 |
|
|
55'b0000000000001??????????????????????????????????????????: diff_shift <= 12;
|
292 |
|
|
55'b00000000000001?????????????????????????????????????????: diff_shift <= 13;
|
293 |
|
|
55'b000000000000001????????????????????????????????????????: diff_shift <= 14;
|
294 |
|
|
55'b0000000000000001???????????????????????????????????????: diff_shift <= 15;
|
295 |
|
|
55'b00000000000000001??????????????????????????????????????: diff_shift <= 16;
|
296 |
|
|
55'b000000000000000001?????????????????????????????????????: diff_shift <= 17;
|
297 |
|
|
55'b0000000000000000001????????????????????????????????????: diff_shift <= 18;
|
298 |
|
|
55'b00000000000000000001???????????????????????????????????: diff_shift <= 19;
|
299 |
|
|
55'b000000000000000000001??????????????????????????????????: diff_shift <= 20;
|
300 |
|
|
55'b0000000000000000000001?????????????????????????????????: diff_shift <= 21;
|
301 |
|
|
55'b00000000000000000000001????????????????????????????????: diff_shift <= 22;
|
302 |
|
|
55'b000000000000000000000001???????????????????????????????: diff_shift <= 23;
|
303 |
|
|
55'b0000000000000000000000001??????????????????????????????: diff_shift <= 24;
|
304 |
|
|
55'b00000000000000000000000001?????????????????????????????: diff_shift <= 25;
|
305 |
|
|
55'b000000000000000000000000001????????????????????????????: diff_shift <= 26;
|
306 |
|
|
55'b0000000000000000000000000001???????????????????????????: diff_shift <= 27;
|
307 |
|
|
55'b00000000000000000000000000001??????????????????????????: diff_shift <= 28;
|
308 |
|
|
55'b000000000000000000000000000001?????????????????????????: diff_shift <= 29;
|
309 |
|
|
55'b0000000000000000000000000000001????????????????????????: diff_shift <= 30;
|
310 |
|
|
55'b00000000000000000000000000000001???????????????????????: diff_shift <= 31;
|
311 |
|
|
55'b000000000000000000000000000000001??????????????????????: diff_shift <= 32;
|
312 |
|
|
55'b0000000000000000000000000000000001?????????????????????: diff_shift <= 33;
|
313 |
|
|
55'b00000000000000000000000000000000001????????????????????: diff_shift <= 34;
|
314 |
|
|
55'b000000000000000000000000000000000001???????????????????: diff_shift <= 35;
|
315 |
|
|
55'b0000000000000000000000000000000000001??????????????????: diff_shift <= 36;
|
316 |
|
|
55'b00000000000000000000000000000000000001?????????????????: diff_shift <= 37;
|
317 |
|
|
55'b000000000000000000000000000000000000001????????????????: diff_shift <= 38;
|
318 |
|
|
55'b0000000000000000000000000000000000000001???????????????: diff_shift <= 39;
|
319 |
|
|
55'b00000000000000000000000000000000000000001??????????????: diff_shift <= 40;
|
320 |
|
|
55'b000000000000000000000000000000000000000001?????????????: diff_shift <= 41;
|
321 |
|
|
55'b0000000000000000000000000000000000000000001????????????: diff_shift <= 42;
|
322 |
|
|
55'b00000000000000000000000000000000000000000001???????????: diff_shift <= 43;
|
323 |
|
|
55'b000000000000000000000000000000000000000000001??????????: diff_shift <= 44;
|
324 |
|
|
55'b0000000000000000000000000000000000000000000001?????????: diff_shift <= 45;
|
325 |
|
|
55'b00000000000000000000000000000000000000000000001????????: diff_shift <= 46;
|
326 |
|
|
55'b000000000000000000000000000000000000000000000001???????: diff_shift <= 47;
|
327 |
|
|
55'b0000000000000000000000000000000000000000000000001??????: diff_shift <= 48;
|
328 |
|
|
55'b00000000000000000000000000000000000000000000000001?????: diff_shift <= 49;
|
329 |
|
|
55'b000000000000000000000000000000000000000000000000001????: diff_shift <= 50;
|
330 |
|
|
55'b0000000000000000000000000000000000000000000000000001???: diff_shift <= 51;
|
331 |
|
|
55'b00000000000000000000000000000000000000000000000000001??: diff_shift <= 52;
|
332 |
|
|
55'b000000000000000000000000000000000000000000000000000001?: diff_shift <= 53;
|
333 |
|
|
55'b0000000000000000000000000000000000000000000000000000001: diff_shift <= 54;
|
334 |
|
|
55'b0000000000000000000000000000000000000000000000000000000: diff_shift <= 55;
|
335 |
6 |
davidklun |
endcase
|
336 |
|
|
|
337 |
|
|
|
338 |
|
|
always @(posedge clk)
|
339 |
|
|
begin
|
340 |
|
|
if (rst) begin
|
341 |
|
|
ready <= 0;
|
342 |
|
|
count_ready_0 <= 0;
|
343 |
|
|
count_ready <= 0;
|
344 |
|
|
end
|
345 |
|
|
else if (enable) begin
|
346 |
|
|
ready <= count_ready;
|
347 |
8 |
davidklun |
count_ready_0 <= count == 21;
|
348 |
|
|
count_ready <= count == 22;
|
349 |
6 |
davidklun |
end
|
350 |
|
|
end
|
351 |
|
|
|
352 |
|
|
always @(posedge clk)
|
353 |
|
|
begin
|
354 |
|
|
if (rst)
|
355 |
|
|
count <= 0;
|
356 |
|
|
else if (enable & !count_ready_0 & !count_ready)
|
357 |
|
|
count <= count + 1;
|
358 |
|
|
end
|
359 |
|
|
|
360 |
8 |
davidklun |
always @(posedge clk)
|
361 |
|
|
begin
|
362 |
|
|
if (rst)
|
363 |
|
|
out <= 0;
|
364 |
|
|
else if (enable & count_ready)
|
365 |
|
|
out <= in_inf21 ? { outfp[63], 11'b11111111111, 52'b0 } : outfp;
|
366 |
|
|
end
|
367 |
6 |
davidklun |
endmodule
|