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[/] [dpsfmnce/] [trunk/] [RTL/] [DPSFnmCE.v] - Blame information for rev 2

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////////////////////////////////////////////////////////////////////////////////
//
//  Copyright 2007-2013 by Michael A. Morris, dba M. A. Morris & Associates
//
//  All rights reserved. The source code contained herein is publicly released
//  under the terms and conditions of the GNU Lesser Public License. No part of
//  this source code may be reproduced or transmitted in any form or by any
//  means, electronic or mechanical, including photocopying, recording, or any
//  information storage and retrieval system in violation of the license under
//  which the source code is released.
//
//  The source code contained herein is free; it may be redistributed and/or
//  modified in accordance with the terms of the GNU Lesser General Public
//  License as published by the Free Software Foundation; either version 2.1 of
//  the GNU Lesser General Public License, or any later version.
//
//  The source code contained herein is freely released WITHOUT ANY WARRANTY;
//  without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
//  PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
//  more details.)
//
//  A copy of the GNU Lesser General Public License should have been received
//  along with the source code contained herein; if not, a copy can be obtained
//  by writing to:
//
//  Free Software Foundation, Inc.
//  51 Franklin Street, Fifth Floor
//  Boston, MA  02110-1301 USA
//
//  Further, no use of this source code is permitted in any form or means
//  without inclusion of this banner prominently in any derived works.
//
//  Michael A. Morris
//  Huntsville, AL
//
////////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company:         M. A. Morris & Associates
// Engineer:        Michael A. Morris
// 
// Create Date:     12:11:30 12/22/2007 
// Design Name:     HAWK Interface FPGA, 4020-0420, U35
// Module Name:     DPSFnmCE 
// Project Name:    4020 HAWK ZAOM Upgrade
// Target Devices:  XC2S150-5PQ208I
// Tool versions:   ISE 8.2i 
//
// Description: This module implements a parameterized version of a distributed
//              RAM synchronous FIFO. The address width, FIFO width and depth
//              are all specified by parameters. Default parameters settings 
//              describe a 16x16 FIFO with Full (FF), Empty (EF), and Half 
//              Full (HF) flags. The module also outputs the count words in the
//              FIFO.
//
// Dependencies:    None
//
// Revision History: 
//
//  0.01    07L22   MAM     File Created
//
//  0.10    08K05   MAM     Changed depth to a localparam based on addr
//
//  1.00    13G14   MAM     Converted to Verilog 2001 standard
//
// Additional Comments: 
//
////////////////////////////////////////////////////////////////////////////////
 
module DPSFnmCE #(
    parameter addr  = 4,                // Sets depth of the FIFO: 2**addr
    parameter width = 16,               // Sets width of the FIFO
    parameter init  = "DPSFnmRAM.coe"   // Initializes FIFO memory
)(
    input   Rst,
    input   Clk,
    input   WE,
    input   RE,
    input   [(width - 1):0] DI,
    output  [(width - 1):0] DO,
    output  FF,
    output  EF,
    output  HF,
    output  [addr:0] Cnt
);
 
////////////////////////////////////////////////////////////////////////////////
//
//  Module Parameter List
//
 
localparam  depth = (2**addr);
 
////////////////////////////////////////////////////////////////////////////////
//
//  Module Level Declarations
//
 
    reg     [(width - 1):0] RAM [(depth - 1):0];
 
    reg     [ (addr - 1):0] A, DPRA;
    reg     [ (addr - 1):0] WCnt;
    reg     nEF, rFF;
 
    wire    Wr, Rd, CE;
 
////////////////////////////////////////////////////////////////////////////////
//
//  Implementation
//
 
//
//  Combinatorial Control Signals
//
 
assign Wr = WE & ~FF;
assign Rd = RE & ~EF;
assign CE = Wr ^ Rd;
 
//
//  Write Address Counter
//
 
always @(posedge Clk)
begin
    if(Rst)
        A <= #1 0;
    else if(Wr)
        A <= #1 A + 1;
end
 
//
//  Read Address Counter
//
 
always @(posedge Clk)
begin
    if(Rst)
       DPRA <= #1 0;
    else if(Rd)
        DPRA <= #1 DPRA + 1;
end
 
//
//   Word Counter
//
 
always @(posedge Clk)
begin
    if(Rst)
        WCnt <= #1 0;
    else if(Wr & ~Rd)
        WCnt <= #1 WCnt + 1;
    else if(Rd & ~Wr)
        WCnt <= #1 WCnt - 1;
end
 
//
//  External Word Count
//
 
assign Cnt = {FF, WCnt};
 
//
//  Empty Flag Register (Active Low)
//
 
always @(posedge Clk)
begin
    if(Rst)
        nEF <= #1 0;
    else if(CE)
        nEF <= #1 ~(RE & (Cnt == 1));
end
 
assign EF = ~nEF;
 
//
//  Full Flag Register
//
 
always @(posedge Clk)
begin
    if(Rst)
        rFF <= #1 0;
    else if(CE)
        rFF <= #1 (WE & (&WCnt));
end
 
assign FF = rFF;
 
//
//  Half-Full Flag
//
 
assign HF = Cnt[addr] | Cnt[(addr - 1)];
 
//
//  Dual-Port Synchronous RAM
//
 
initial
  $readmemh(init, RAM, 0, (depth - 1));
 
always @(posedge Clk)
begin
    if(Wr)
        RAM[A] <= #1 DI;    // Synchronous Write
end
 
assign DO = RAM[DPRA];      // Asynchronous Read
 
endmodule
 

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[/] [dpsfmnce/] [trunk/] [RTL/] [DPSFnmCE.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	MichaelA	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Copyright 2007-2013 by Michael A. Morris, dba M. A. Morris & Associates`
4			`//`
5			`// All rights reserved. The source code contained herein is publicly released`
6			`// under the terms and conditions of the GNU Lesser Public License. No part of`
7			`// this source code may be reproduced or transmitted in any form or by any`
8			`// means, electronic or mechanical, including photocopying, recording, or any`
9			`// information storage and retrieval system in violation of the license under`
10			`// which the source code is released.`
11			`//`
12			`// The source code contained herein is free; it may be redistributed and/or`
13			`// modified in accordance with the terms of the GNU Lesser General Public`
14			`// License as published by the Free Software Foundation; either version 2.1 of`
15			`// the GNU Lesser General Public License, or any later version.`
16			`//`
17			`// The source code contained herein is freely released WITHOUT ANY WARRANTY;`
18			`// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A`
19			`// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for`
20			`// more details.)`
21			`//`
22			`// A copy of the GNU Lesser General Public License should have been received`
23			`// along with the source code contained herein; if not, a copy can be obtained`
24			`// by writing to:`
25			`//`
26			`// Free Software Foundation, Inc.`
27			`// 51 Franklin Street, Fifth Floor`
28			`// Boston, MA 02110-1301 USA`
29			`//`
30			`// Further, no use of this source code is permitted in any form or means`
31			`// without inclusion of this banner prominently in any derived works.`
32			`//`
33			`// Michael A. Morris`
34			`// Huntsville, AL`
35			`//`
36			`////////////////////////////////////////////////////////////////////////////////`
37
38			`timescale 1ns / 1ps
39
40			`////////////////////////////////////////////////////////////////////////////////`
41			`// Company: M. A. Morris & Associates`
42			`// Engineer: Michael A. Morris`
43			`//`
44			`// Create Date: 12:11:30 12/22/2007`
45			`// Design Name: HAWK Interface FPGA, 4020-0420, U35`
46			`// Module Name: DPSFnmCE`
47			`// Project Name: 4020 HAWK ZAOM Upgrade`
48			`// Target Devices: XC2S150-5PQ208I`
49			`// Tool versions: ISE 8.2i`
50			`//`
51			`// Description: This module implements a parameterized version of a distributed`
52			`// RAM synchronous FIFO. The address width, FIFO width and depth`
53			`// are all specified by parameters. Default parameters settings`
54			`// describe a 16x16 FIFO with Full (FF), Empty (EF), and Half`
55			`// Full (HF) flags. The module also outputs the count words in the`
56			`// FIFO.`
57			`//`
58			`// Dependencies: None`
59			`//`
60			`// Revision History:`
61			`//`
62			`// 0.01 07L22 MAM File Created`
63			`//`
64			`// 0.10 08K05 MAM Changed depth to a localparam based on addr`
65			`//`
66			`// 1.00 13G14 MAM Converted to Verilog 2001 standard`
67			`//`
68			`// Additional Comments:`
69			`//`
70			`////////////////////////////////////////////////////////////////////////////////`
71
72			`module DPSFnmCE #(`
73			`parameter addr = 4, // Sets depth of the FIFO: 2**addr`
74			`parameter width = 16, // Sets width of the FIFO`
75			`parameter init = "DPSFnmRAM.coe" // Initializes FIFO memory`
76			`)(`
77			`input Rst,`
78			`input Clk,`
79			`input WE,`
80			`input RE,`
81			`input [(width - 1):0] DI,`
82			`output [(width - 1):0] DO,`
83			`output FF,`
84			`output EF,`
85			`output HF,`
86			`output [addr:0] Cnt`
87			`);`
88
89			`////////////////////////////////////////////////////////////////////////////////`
90			`//`
91			`// Module Parameter List`
92			`//`
93
94			`localparam depth = (2**addr);`
95
96			`////////////////////////////////////////////////////////////////////////////////`
97			`//`
98			`// Module Level Declarations`
99			`//`
100
101			`reg [(width - 1):0] RAM [(depth - 1):0];`
102
103			`reg [ (addr - 1):0] A, DPRA;`
104			`reg [ (addr - 1):0] WCnt;`
105			`reg nEF, rFF;`
106
107			`wire Wr, Rd, CE;`
108
109			`////////////////////////////////////////////////////////////////////////////////`
110			`//`
111			`// Implementation`
112			`//`
113
114			`//`
115			`// Combinatorial Control Signals`
116			`//`
117
118			`assign Wr = WE & ~FF;`
119			`assign Rd = RE & ~EF;`
120			`assign CE = Wr ^ Rd;`
121
122			`//`
123			`// Write Address Counter`
124			`//`
125
126			`always @(posedge Clk)`
127			`begin`
128			`if(Rst)`
129			`A <= #1 0;`
130			`else if(Wr)`
131			`A <= #1 A + 1;`
132			`end`
133
134			`//`
135			`// Read Address Counter`
136			`//`
137
138			`always @(posedge Clk)`
139			`begin`
140			`if(Rst)`
141			`DPRA <= #1 0;`
142			`else if(Rd)`
143			`DPRA <= #1 DPRA + 1;`
144			`end`
145
146			`//`
147			`// Word Counter`
148			`//`
149
150			`always @(posedge Clk)`
151			`begin`
152			`if(Rst)`
153			`WCnt <= #1 0;`
154			`else if(Wr & ~Rd)`
155			`WCnt <= #1 WCnt + 1;`
156			`else if(Rd & ~Wr)`
157			`WCnt <= #1 WCnt - 1;`
158			`end`
159
160			`//`
161			`// External Word Count`
162			`//`
163
164			`assign Cnt = {FF, WCnt};`
165
166			`//`
167			`// Empty Flag Register (Active Low)`
168			`//`
169
170			`always @(posedge Clk)`
171			`begin`
172			`if(Rst)`
173			`nEF <= #1 0;`
174			`else if(CE)`
175			`nEF <= #1 ~(RE & (Cnt == 1));`
176			`end`
177
178			`assign EF = ~nEF;`
179
180			`//`
181			`// Full Flag Register`
182			`//`
183
184			`always @(posedge Clk)`
185			`begin`
186			`if(Rst)`
187			`rFF <= #1 0;`
188			`else if(CE)`
189			`rFF <= #1 (WE & (&WCnt));`
190			`end`
191
192			`assign FF = rFF;`
193
194			`//`
195			`// Half-Full Flag`
196			`//`
197
198			`assign HF = Cnt[addr] \| Cnt[(addr - 1)];`
199
200			`//`
201			`// Dual-Port Synchronous RAM`
202			`//`
203
204			`initial`
205			`$readmemh(init, RAM, 0, (depth - 1));`
206
207			`always @(posedge Clk)`
208			`begin`
209			`if(Wr)`
210			`RAM[A] <= #1 DI; // Synchronous Write`
211			`end`
212
213			`assign DO = RAM[DPRA]; // Asynchronous Read`
214
215			`endmodule`
216