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entactogen |
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-- Copyright (c) 2013 Antonio de la Piedra
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity TETRA_phy is
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port(tetra_clk_36_KHz : in std_logic;
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tetra_clk_18_KHz : in std_logic;
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tetra_rst : in std_logic;
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tetra_bit_stream_input : in STD_LOGIC;
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tetra_valid_input : in STD_LOGIC;
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tetra_debug_dbit_output : out std_logic_vector(1 downto 0);
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tetra_diffPhaseEncoder_output_0 : out std_logic_vector(7 downto 0);
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tetra_diffPhaseEncoder_output_1 : out std_logic_vector(7 downto 0)
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);
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end TETRA_phy;
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architecture Behavioral of TETRA_phy is
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component dataConverter is
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Port (clk_36_KHz : in STD_LOGIC;
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rst : in std_logic;
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bit_stream_input : in STD_LOGIC;
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valid_input : in STD_LOGIC;
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dbit_output : out std_logic_vector(1 downto 0));
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end component;
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component biPolarEncoder is
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Port (bit_input : in std_logic;
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valid_input : in STD_LOGIC;
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bi_polar_output : out std_logic_vector(1 downto 0));
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end component;
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component diffPhaseEncoder is
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port(clk_18_KHz: in std_logic;
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rst: in std_logic;
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en: in std_logic;
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a_k : in std_logic;
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b_k : in std_logic;
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i_k : out std_logic_vector(7 downto 0);
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q_k : out std_logic_vector(7 downto 0));
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end component;
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signal dc_dbit_output_tmp : std_logic_vector(1 downto 0);
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signal valid_input_diffPhaseEncoder_1_s : std_logic;
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signal valid_input_diffPhaseEncoder_2_s : std_logic;
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signal tetra_diffPhaseEncoder_output_0_tmp : std_logic_vector(7 downto 0);
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signal tetra_diffPhaseEncoder_output_1_tmp : std_logic_vector(7 downto 0);
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begin
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DCONV: dataConverter port map (tetra_clk_36_KHz,
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tetra_rst,
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tetra_bit_stream_input,
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tetra_valid_input,
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dc_dbit_output_tmp);
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PHENC: diffPhaseEncoder port map (tetra_clk_18_KHz,
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tetra_rst,
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valid_input_diffPhaseEncoder_2_s, --valid_input_diffPhaseEncoder_s,
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dc_dbit_output_tmp(1),
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dc_dbit_output_tmp(0),
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tetra_diffPhaseEncoder_output_0_tmp,
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tetra_diffPhaseEncoder_output_1_tmp);
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tetra_debug_dbit_output <= dc_dbit_output_tmp;
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tetra_diffPhaseEncoder_output_0 <= tetra_diffPhaseEncoder_output_0_tmp;
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tetra_diffPhaseEncoder_output_1 <= tetra_diffPhaseEncoder_output_1_tmp;
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delay_biPolarEncoder_1: process(tetra_clk_18_KHz, tetra_valid_input)
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variable valid_input_diffPhaseEncoder_v : std_logic := '0';
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begin
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if falling_edge(tetra_clk_36_KHz) then
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valid_input_diffPhaseEncoder_v := tetra_valid_input;
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end if;
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valid_input_diffPhaseEncoder_1_s <= valid_input_diffPhaseEncoder_v;
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end process;
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delay_biPolarEncoder_2: process(tetra_clk_18_KHz, tetra_valid_input, valid_input_diffPhaseEncoder_1_s)
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variable valid_input_diffPhaseEncoder_v : std_logic := '0';
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begin
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if falling_edge(tetra_clk_36_KHz) then
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valid_input_diffPhaseEncoder_v := valid_input_diffPhaseEncoder_1_s;
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end if;
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valid_input_diffPhaseEncoder_2_s <= valid_input_diffPhaseEncoder_v;
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end process;
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end Behavioral;
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