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akhachat |
ncverilog(64): 08.20-s010: (c) Copyright 1995-2009 Cadence Design Systems, Inc.
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TOOL: ncverilog 08.20-s010: Started on Apr 02, 2010 at 14:33:38 AMST
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/et/hw/vendor/cadence/ius/v8.2USR10/tools/bin/64bit/ncverilog
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+sv
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-f sim_args.v
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+libext+.v+.vp
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+access+rwc
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+incdir+ds1621/files+
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-f sim.files
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ds1621/files/tb_top.sv
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ds1621/files/DS1621_b.sv
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ds1621/files/24LC16B.v
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+notimingchecks
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+nowarn+LIBNOU
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+define+NOCHECKS
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+define+verbose_0
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+define+nobanner
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+nclibdirname+.INCA_libs
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file: ds1621/files/tb_top.sv
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default input #1step output #1step;
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ncvlog: *W,SAWSTP (ds1621/files/tb_top.sv,96|23): Time unit "step" seen in literal - using local precision.
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default input #1step output #1step;
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ncvlog: *W,SAWSTP (ds1621/files/tb_top.sv,96|37): Time unit "step" seen in literal - using local precision.
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module worklib.top:sv
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errors: 0, warnings: 2
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file: ds1621/files/DS1621_b.sv
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tri1 SDA;
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ncvlog: *W,ILLPDX (ds1621/files/DS1621_b.sv,76|14): Multiple declarations for a port not allowed in module with ANSI list of port declarations (port 'SDA') [12.3.4(IEEE-2001)].
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module worklib.DS1621_b:sv
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errors: 0, warnings: 1
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file: ds1621/files/24LC16B.v
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Caching library 'worklib' ....... Done
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Elaborating the design hierarchy:
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M24LC16B u_24LC16B(
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ncelab: *W,CUVWSI (../files/tb_top.sv,65|18): 3 input ports were not connected:
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ncelab: (../files/24LC16B.v,81): A0
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ncelab: (../files/24LC16B.v,81): A1
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ncelab: (../files/24LC16B.v,81): A2
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Building instance overlay tables: ...............
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$readmemh( "DS1621_b_nvm.sv", nv_RAM );
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ncelab: *W,MEMODR (../files/DS1621_b.sv,368|43): $readmem default memory order incompatible with IEEE1364.
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.....
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$readmemh( "DS1621_b_nvm.sv", nv_RAM );
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ncelab: *W,MEMODR (../files/DS1621_b.sv,368|43): $readmem default memory order incompatible with IEEE1364.
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Done
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Generating native compiled code:
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worklib.DS1621_b:sv <0x0a2e8c6e>
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streams: 103, words: 33942
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worklib.DS1621_b:sv <0x2dea07dd>
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streams: 103, words: 33942
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worklib.top:sv <0x5508e5e8>
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streams: 18, words: 69160
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Loading native compiled code: .................... Done
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Building instance specific data structures.
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Design hierarchy summary:
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Instances Unique
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Modules: 4 3
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Primitives: 1 1
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Registers: 165 109
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Scalar wires: 111 -
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Vectored wires: 152 -
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Always blocks: 87 52
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Initial blocks: 15 12
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Clocking blocks: 1 1
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Cont. assignments: 217 202
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Pseudo assignments: 4 4
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Timing checks: 21 -
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Simulation timescale: 1ps
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Writing initial simulation snapshot: worklib.top:sv
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Loading snapshot worklib.top:sv .................... Done
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ncsim> source /et/hw/vendor/cadence/ius/v8.2USR10/tools/inca/files/ncsimrc
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ncsim> run
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*****************************
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* *
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* DS1621 simulation *
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* *
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*****************************
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--DS1621 test 01 begin-->
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----DS1621 sending CFG=03, TH=16'h2800, TL=16'h0A00
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----DS1621 sending done
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----DS1621 reading TH
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----DS1621 TH = 2800
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----DS1621 start TMP conversion
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passing 1000 us
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passing 2000 us
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----DS1621 T=25.5*C, expecting 1980, TMP = 1980
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----DS1621 start TMP conversion
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passing 3000 us
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passing 4000 us
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----DS1621 T=-13.0*C, expecting F300, TMP = f300
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----DS1621 start TMP conversion
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passing 5000 us
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passing 6000 us
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----DS1621 T=-13.5*C, expecting F380, TMP = f380
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----DS1621 start TMP conversion
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passing 7000 us
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passing 8000 us
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----DS1621 T=130.0*C, expecting 7D00, TMP = 7d00
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----DS1621 start TMP conversion
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passing 9000 us
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passing 10000 us
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passing 11000 us
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----DS1621 T=-60.0*C, expecting C900, TMP = c900
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--DS1621 test 01 end--<
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--------------------------------------------------------------------------------
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--DS1621 test 06 begin-->
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----DS1621 sending CFG=03, TH=16'h2800, TL=16'h0A00
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----DS1621 sending done
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----DS1621 start TMP conversion
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passing 12000 us
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passing 13000 us
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----DS1621 T=25.5*C, expecting 1980, TMP = 1980
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----DS1621 start TMP conversion
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passing 14000 us
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passing 15000 us
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----DS1621 T=-13.0*C, expecting F300, TMP = f300
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--DS1621 test 06 end--<
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--------------------------------------------------------------------------------
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--EEPROM test begin-->
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---- writing A=12'h001, D=8'h5A
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passing 16000 us
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passing 17000 us
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passing 18000 us
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passing 19000 us
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passing 20000 us
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---- writing done A=12'h001, D=8'h5A
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---- reading A=12'h001
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---- reading done A=12'h001 contains 5a
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--EEPROM test end--<
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Simulation complete via $finish(1) at time 20899601 NS + 0
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../files/tb_top.sv:61 $finish;
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ncsim> exit
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TOOL: ncverilog 08.20-s010: Exiting on Apr 02, 2010 at 14:33:41 AMST (total: 00:00:03)
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