| 1 |
2 |
victor |
library ieee;
|
| 2 |
|
|
use ieee.std_logic_1164.all;
|
| 3 |
|
|
USE ieee.std_logic_arith.all;
|
| 4 |
|
|
USE ieee.std_logic_unsigned.all;
|
| 5 |
|
|
|
| 6 |
|
|
|
| 7 |
|
|
entity e1_frm is
|
| 8 |
|
|
port(E1_out,nr: out STD_LOGIC;--output serial stream
|
| 9 |
|
|
E1_CLK_in: in STD_LOGIC;--clock for output stream
|
| 10 |
|
|
reset: in STD_LOGIC; -- reset
|
| 11 |
|
|
frame_start,RD: out STD_LOGIC;-- determines frame start, RD - read signal for "look forvard" memory
|
| 12 |
|
|
data: in STD_LOGIC_VECTOR (0 to 7);
|
| 13 |
|
|
zero_frame: in STD_LOGIC_VECTOR (0 to 7)-- zero frame data
|
| 14 |
|
|
|
| 15 |
|
|
--isEmpty : in STD_LOGIC
|
| 16 |
|
|
);
|
| 17 |
|
|
end e1_frm;
|
| 18 |
|
|
|
| 19 |
|
|
architecture BEHAVIOR of e1_frm is
|
| 20 |
|
|
|
| 21 |
|
|
SIGNAL cnt: integer range 0 to 7;
|
| 22 |
|
|
signal ires,state,frame_type: STD_LOGIC;
|
| 23 |
|
|
signal iData: STD_LOGIC_VECTOR (0 to 7);
|
| 24 |
|
|
|
| 25 |
|
|
begin
|
| 26 |
|
|
nr<=ires;
|
| 27 |
|
|
------------------------------------------------------------------------------------------------------
|
| 28 |
|
|
-- lower bits come first!!!
|
| 29 |
|
|
-- parallel to serial converter
|
| 30 |
|
|
------------------------------------------------------------------------------------------------------
|
| 31 |
|
|
process (E1_CLK_in,ires)
|
| 32 |
|
|
begin
|
| 33 |
|
|
if (ires='1') then
|
| 34 |
|
|
cnt<=0;
|
| 35 |
|
|
E1_out<='0';
|
| 36 |
|
|
elsif (FALLING_EDGE(E1_CLK_in)) then
|
| 37 |
|
|
E1_out<=iData(cnt);
|
| 38 |
|
|
cnt<=cnt+1;
|
| 39 |
|
|
end if;
|
| 40 |
|
|
end process;
|
| 41 |
|
|
|
| 42 |
|
|
--------------------------------------------------------------------------------------------------------
|
| 43 |
|
|
--this trigger is used to eliminate "short reset" situation: when reset becomes low during "high" E1_CLK_in
|
| 44 |
|
|
--in this situation transmitter starts before state machine set up valid iData signal
|
| 45 |
|
|
--------------------------------------------------------------------------------------------------------
|
| 46 |
|
|
process (E1_CLK_in,reset)
|
| 47 |
|
|
begin
|
| 48 |
|
|
if (reset='1') then
|
| 49 |
|
|
ires<='1';
|
| 50 |
|
|
elsif (FALLING_EDGE(E1_CLK_in)) then
|
| 51 |
|
|
ires<='0';
|
| 52 |
|
|
end if;
|
| 53 |
|
|
end process;
|
| 54 |
|
|
|
| 55 |
|
|
--------------------------------------------------------------------------------------------------------
|
| 56 |
|
|
-- state machine
|
| 57 |
|
|
-- 0 - zero time slot generation.
|
| 58 |
|
|
-- 1 - transmission
|
| 59 |
|
|
--------------------------------------------------------------------------------------------------------
|
| 60 |
|
|
process (E1_CLK_in,ires)
|
| 61 |
|
|
variable byte_cnt: integer range 0 to 31;
|
| 62 |
|
|
begin
|
| 63 |
|
|
if (ires='1') then
|
| 64 |
|
|
state<='0';
|
| 65 |
|
|
frame_type<='0';
|
| 66 |
|
|
elsif (RISING_EDGE(E1_CLK_in)) then
|
| 67 |
|
|
CASE state IS
|
| 68 |
|
|
WHEN '0' =>
|
| 69 |
|
|
byte_cnt:=0;
|
| 70 |
|
|
frame_start<='1';
|
| 71 |
|
|
if(frame_type='0') then
|
| 72 |
|
|
iData<="10011011";
|
| 73 |
|
|
else
|
| 74 |
|
|
iData(0)<=zero_frame(0);
|
| 75 |
|
|
iData(2 to 7)<=zero_frame(2 to 7);
|
| 76 |
|
|
iData(1)<='1';--warranty of correct frame signal
|
| 77 |
|
|
end if;
|
| 78 |
|
|
state<=CONV_STD_LOGIC_VECTOR(cnt,3)(0) and CONV_STD_LOGIC_VECTOR(cnt,3)(1) and CONV_STD_LOGIC_VECTOR(cnt,3)(2);
|
| 79 |
|
|
WHEN '1' =>
|
| 80 |
|
|
frame_start<='0';
|
| 81 |
|
|
if (cnt = 0) then
|
| 82 |
|
|
iData<=data;
|
| 83 |
|
|
RD<='1';
|
| 84 |
|
|
else
|
| 85 |
|
|
RD<='0';
|
| 86 |
|
|
end if;
|
| 87 |
|
|
if(cnt=7)then
|
| 88 |
|
|
if(byte_cnt=30) then
|
| 89 |
|
|
state<='0';-- frame trensmitted
|
| 90 |
|
|
frame_type<=not(frame_type);
|
| 91 |
|
|
else
|
| 92 |
|
|
byte_cnt:=byte_cnt+1;
|
| 93 |
|
|
end if;
|
| 94 |
|
|
end if;
|
| 95 |
|
|
when others=> state<='0';
|
| 96 |
|
|
END CASE;
|
| 97 |
|
|
end if;
|
| 98 |
|
|
end process;
|
| 99 |
|
|
|
| 100 |
|
|
end BEHAVIOR;
|
| 101 |
|
|
|
