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[/] [eco32/] [tags/] [eco32-0.22/] [monitor/] [monitor/] [start.s] - Blame information for rev 279

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;
; start.s -- ECO32 ROM monitor startup and support routines
;
 
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
        .set    stacktop,0xC0400000     ; monitor stack is at top of memory
 
        .set    PSW,0                    ; reg # of PSW
        .set    TLB_INDEX,1             ; reg # of TLB Index
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
        .set    TLB_ENTRIES,32          ; number of TLB entries
 
        .set    USER_CONTEXT_SIZE,36*4  ; size of user context
 
;***************************************************************
 
        .import _ecode
        .import _edata
        .import _ebss
 
        .import kbdinit
        .import kbdinchk
        .import kbdin
 
        .import dspinit
        .import dspoutchk
        .import dspout
 
        .import serinit
        .import ser0inchk
        .import ser0in
        .import ser0outchk
        .import ser0out
 
        .import sctcapctl
        .import sctioctl
        .import sctcapser
        .import sctioser
 
        .import main
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export cinchk
        .export cin
        .export coutchk
        .export cout
        .export sinchk
        .export sin
        .export soutchk
        .export sout
        .export dskcap
        .export dskio
 
        .export getTLB_HI
        .export getTLB_LO
        .export setTLB
 
        .export saveState
        .export monitorReturn
 
        .import userContext
        .export resume
 
;***************************************************************
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
;***************************************************************
 
        .code
        .align  4
 
reset:
        j       start
 
interrupt:
        j       isr
 
userMiss:
        j       umsr
 
;***************************************************************
 
        .code
        .align  4
 
cinchk:
;       j       kbdinchk
        j       ser0inchk
 
cin:
;       j       kbdin
        j       ser0in
 
coutchk:
;       j       dspoutchk
        j       ser0outchk
 
cout:
;       j       dspout
        j       ser0out
 
sinchk:
        j       ser0inchk
 
sin:
        j       ser0in
 
soutchk:
        j       ser0outchk
 
sout:
        j       ser0out
 
dskcap:
        j       dcap
 
dskio:
        j       dio
 
;***************************************************************
 
        .code
        .align  4
 
start:
        ; force CPU into a defined state
        mvts    $0,PSW                   ; disable interrupts and user mode
 
        ; initialize TLB
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
        add     $8,$0,dmapaddr           ; by impossible virtual page number
        add     $9,$0,$0
        add     $10,$0,TLB_ENTRIES
tlbloop:
        mvts    $8,TLB_ENTRY_HI
        mvts    $9,TLB_INDEX
        tbwi
        add     $8,$8,0x1000            ; all entries must be different
        add     $9,$9,1
        bne     $9,$10,tlbloop
 
        ; copy data segment
        add     $10,$0,_bdata            ; lowest dst addr to be written to
        add     $8,$0,_edata             ; one above the top dst addr
        sub     $9,$8,$10               ; $9 = size of data segment
        add     $9,$9,_ecode            ; data is waiting right after code
        j       cpytest
cpyloop:
        ldw     $11,$9,0         ; src addr in $9
        stw     $11,$8,0         ; dst addr in $8
cpytest:
        sub     $8,$8,4                 ; downward
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
 
        ; clear bss segment
        add     $8,$0,_bbss              ; start with first word of bss
        add     $9,$0,_ebss              ; this is one above the top
        j       clrtest
clrloop:
        stw     $0,$8,0                   ; dst addr in $8
        add     $8,$8,4                 ; upward
clrtest:
        bltu    $8,$9,clrloop
 
        ; now do some useful work
        add     $29,$0,stacktop          ; setup monitor stack
;       jal     dspinit                 ; init display
;       jal     kbdinit                 ; init keyboard
        jal     serinit                 ; init serial interface
        jal     main                    ; enter command loop
 
        ; main should never return
        j       start                   ; just to be sure...
 
;***************************************************************
 
        ; Word getTLB_HI(int index)
getTLB_HI:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_HI
        jr      $31
 
        ; Word getTLB_LO(int index)
getTLB_LO:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_LO
        jr      $31
 
        ; void setTLB(int index, Word entryHi, Word entryLo)
setTLB:
        mvts    $4,TLB_INDEX
        mvts    $5,TLB_ENTRY_HI
        mvts    $6,TLB_ENTRY_LO
        tbwi
        jr      $31
 
;***************************************************************
 
        ; int dskcap(int dskno)
dcap:
        bne     $4,$0,dcapser
        j       sctcapctl
dcapser:
        j       sctcapser
 
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
dio:
        bne     $4,$0,dioser
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       sctioctl
dioser:
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       sctioser
 
;***************************************************************
 
        .code
        .align  4
 
        ; Bool saveState(MonitorState *msp)
        ; always return 'true' here
saveState:
        stw     $31,$4,0*4               ; return address
        stw     $29,$4,1*4              ; stack pointer
        stw     $16,$4,2*4              ; local variables
        stw     $17,$4,3*4
        stw     $18,$4,4*4
        stw     $19,$4,5*4
        stw     $20,$4,6*4
        stw     $21,$4,7*4
        stw     $22,$4,8*4
        stw     $23,$4,9*4
        add     $2,$0,1
        jr      $31
 
        ; load state when re-entering monitor
        ; this appears as if returning from saveState
        ; but the return value is 'false' here
loadState:
        ldw     $8,$0,monitorReturn
        beq     $8,$0,loadState          ; fatal error: monitor state lost
        ldw     $31,$8,0*4               ; return address
        ldw     $29,$8,1*4              ; stack pointer
        ldw     $16,$8,2*4              ; local variables
        ldw     $17,$8,3*4
        ldw     $18,$8,4*4
        ldw     $19,$8,5*4
        ldw     $20,$8,6*4
        ldw     $21,$8,7*4
        ldw     $22,$8,8*4
        ldw     $23,$8,9*4
        add     $2,$0,0
        jr      $31
 
        .bss
        .align  4
 
        ; extern MonitorState *monitorReturn
monitorReturn:
        .space  4
 
        ; extern UserContext userContext
userContext:
        .space  USER_CONTEXT_SIZE
 
;***************************************************************
 
        .code
        .align  4
 
        ; void resume(void)
        ; use userContext to load state
resume:
        mvts    $0,PSW
        add     $28,$0,userContext
        .nosyn
        ldw     $8,$28,33*4             ; tlbIndex
        mvts    $8,TLB_INDEX
        ldw     $8,$28,34*4             ; tlbWntryHi
        mvts    $8,TLB_ENTRY_HI
        ldw     $8,$28,35*4             ; tlbEntryLo
        mvts    $8,TLB_ENTRY_LO
        ;ldw    $0,$28,0*4              ; registers
        ldw     $1,$28,1*4
        ldw     $2,$28,2*4
        ldw     $3,$28,3*4
        ldw     $4,$28,4*4
        ldw     $5,$28,5*4
        ldw     $6,$28,6*4
        ldw     $7,$28,7*4
        ldw     $8,$28,8*4
        ldw     $9,$28,9*4
        ldw     $10,$28,10*4
        ldw     $11,$28,11*4
        ldw     $12,$28,12*4
        ldw     $13,$28,13*4
        ldw     $14,$28,14*4
        ldw     $15,$28,15*4
        ldw     $16,$28,16*4
        ldw     $17,$28,17*4
        ldw     $18,$28,18*4
        ldw     $19,$28,19*4
        ldw     $20,$28,20*4
        ldw     $21,$28,21*4
        ldw     $22,$28,22*4
        ldw     $23,$28,23*4
        ldw     $24,$28,24*4
        ldw     $25,$28,25*4
        ldw     $26,$28,26*4
        ldw     $27,$28,27*4
        ;ldw    $28,$28,28*4
        ldw     $29,$28,29*4
        ldw     $30,$28,30*4
        ldw     $31,$28,31*4
        ldw     $28,$28,32*4            ; psw
        mvts    $28,PSW
        rfx
        .syn
 
        ; interrupt entry
        ; use userContext to store state
isr:
umsr:
        .nosyn
        ldhi    $28,userContext
        or      $28,$28,userContext
        stw     $0,$28,0*4                ; registers
        stw     $1,$28,1*4
        stw     $2,$28,2*4
        stw     $3,$28,3*4
        stw     $4,$28,4*4
        stw     $5,$28,5*4
        stw     $6,$28,6*4
        stw     $7,$28,7*4
        stw     $8,$28,8*4
        stw     $9,$28,9*4
        stw     $10,$28,10*4
        stw     $11,$28,11*4
        stw     $12,$28,12*4
        stw     $13,$28,13*4
        stw     $14,$28,14*4
        stw     $15,$28,15*4
        stw     $16,$28,16*4
        stw     $17,$28,17*4
        stw     $18,$28,18*4
        stw     $19,$28,19*4
        stw     $20,$28,20*4
        stw     $21,$28,21*4
        stw     $22,$28,22*4
        stw     $23,$28,23*4
        stw     $24,$28,24*4
        stw     $25,$28,25*4
        stw     $26,$28,26*4
        stw     $27,$28,27*4
        stw     $28,$28,28*4
        stw     $29,$28,29*4
        stw     $30,$28,30*4
        stw     $31,$28,31*4
        mvfs    $8,PSW
        stw     $8,$28,32*4             ; psw
        mvfs    $8,TLB_INDEX
        stw     $8,$28,33*4             ; tlbIndex
        mvfs    $8,TLB_ENTRY_HI
        stw     $8,$28,34*4             ; tlbEntryHi
        mvfs    $8,TLB_ENTRY_LO
        stw     $8,$28,35*4             ; tlbEntryLo
        .syn
        j       loadState

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Subversion Repositories eco32

[/] [eco32/] [tags/] [eco32-0.22/] [monitor/] [monitor/] [start.s] - Blame information for rev 279

Line No.	Rev	Author	Line
1	16	hellwig	`;`
2			`; start.s -- ECO32 ROM monitor startup and support routines`
3			`;`
4
5			`.set dmapaddr,0xC0000000 ; base of directly mapped addresses`
6			`.set stacktop,0xC0400000 ; monitor stack is at top of memory`
7
8			`.set PSW,0 ; reg # of PSW`
9			`.set TLB_INDEX,1 ; reg # of TLB Index`
10			`.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi`
11			`.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo`
12			`.set TLB_ENTRIES,32 ; number of TLB entries`
13
14			`.set USER_CONTEXT_SIZE,36*4 ; size of user context`
15
16			`;***************************************************************`
17
18			`.import _ecode`
19			`.import _edata`
20			`.import _ebss`
21
22			`.import kbdinit`
23			`.import kbdinchk`
24			`.import kbdin`
25
26			`.import dspinit`
27			`.import dspoutchk`
28			`.import dspout`
29
30			`.import serinit`
31			`.import ser0inchk`
32			`.import ser0in`
33			`.import ser0outchk`
34			`.import ser0out`
35
36			`.import sctcapctl`
37			`.import sctioctl`
38			`.import sctcapser`
39			`.import sctioser`
40
41			`.import main`
42
43			`.export _bcode`
44			`.export _bdata`
45			`.export _bbss`
46
47			`.export cinchk`
48			`.export cin`
49			`.export coutchk`
50			`.export cout`
51			`.export sinchk`
52			`.export sin`
53			`.export soutchk`
54			`.export sout`
55			`.export dskcap`
56			`.export dskio`
57
58			`.export getTLB_HI`
59			`.export getTLB_LO`
60			`.export setTLB`
61
62			`.export saveState`
63			`.export monitorReturn`
64
65			`.import userContext`
66			`.export resume`
67
68			`;***************************************************************`
69
70			`.code`
71			`_bcode:`
72
73			`.data`
74			`_bdata:`
75
76			`.bss`
77			`_bbss:`
78
79			`;***************************************************************`
80
81			`.code`
82			`.align 4`
83
84			`reset:`
85			`j start`
86
87			`interrupt:`
88			`j isr`
89
90			`userMiss:`
91			`j umsr`
92
93			`;***************************************************************`
94
95			`.code`
96			`.align 4`
97
98			`cinchk:`
99			`; j kbdinchk`
100			`j ser0inchk`
101
102			`cin:`
103			`; j kbdin`
104			`j ser0in`
105
106			`coutchk:`
107			`; j dspoutchk`
108			`j ser0outchk`
109
110			`cout:`
111			`; j dspout`
112			`j ser0out`
113
114			`sinchk:`
115			`j ser0inchk`
116
117			`sin:`
118			`j ser0in`
119
120			`soutchk:`
121			`j ser0outchk`
122
123			`sout:`
124			`j ser0out`
125
126			`dskcap:`
127			`j dcap`
128
129			`dskio:`
130			`j dio`
131
132			`;***************************************************************`
133
134			`.code`
135			`.align 4`
136
137			`start:`
138			`; force CPU into a defined state`
139			`mvts $0,PSW ; disable interrupts and user mode`
140
141			`; initialize TLB`
142			`mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries`
143			`add $8,$0,dmapaddr ; by impossible virtual page number`
144			`add $9,$0,$0`
145			`add $10,$0,TLB_ENTRIES`
146			`tlbloop:`
147			`mvts $8,TLB_ENTRY_HI`
148			`mvts $9,TLB_INDEX`
149			`tbwi`
150			`add $8,$8,0x1000 ; all entries must be different`
151			`add $9,$9,1`
152			`bne $9,$10,tlbloop`
153
154			`; copy data segment`
155			`add $10,$0,_bdata ; lowest dst addr to be written to`
156			`add $8,$0,_edata ; one above the top dst addr`
157			`sub $9,$8,$10 ; $9 = size of data segment`
158			`add $9,$9,_ecode ; data is waiting right after code`
159			`j cpytest`
160			`cpyloop:`
161			`ldw $11,$9,0 ; src addr in $9`
162			`stw $11,$8,0 ; dst addr in $8`
163			`cpytest:`
164			`sub $8,$8,4 ; downward`
165			`sub $9,$9,4`
166			`bgeu $8,$10,cpyloop`
167
168			`; clear bss segment`
169			`add $8,$0,_bbss ; start with first word of bss`
170			`add $9,$0,_ebss ; this is one above the top`
171			`j clrtest`
172			`clrloop:`
173			`stw $0,$8,0 ; dst addr in $8`
174			`add $8,$8,4 ; upward`
175			`clrtest:`
176			`bltu $8,$9,clrloop`
177
178			`; now do some useful work`
179			`add $29,$0,stacktop ; setup monitor stack`
180			`; jal dspinit ; init display`
181			`; jal kbdinit ; init keyboard`
182			`jal serinit ; init serial interface`
183			`jal main ; enter command loop`
184
185			`; main should never return`
186			`j start ; just to be sure...`
187
188			`;***************************************************************`
189
190			`; Word getTLB_HI(int index)`
191			`getTLB_HI:`
192			`mvts $4,TLB_INDEX`
193			`tbri`
194			`mvfs $2,TLB_ENTRY_HI`
195			`jr $31`
196
197			`; Word getTLB_LO(int index)`
198			`getTLB_LO:`
199			`mvts $4,TLB_INDEX`
200			`tbri`
201			`mvfs $2,TLB_ENTRY_LO`
202			`jr $31`
203
204			`; void setTLB(int index, Word entryHi, Word entryLo)`
205			`setTLB:`
206			`mvts $4,TLB_INDEX`
207			`mvts $5,TLB_ENTRY_HI`
208			`mvts $6,TLB_ENTRY_LO`
209			`tbwi`
210			`jr $31`
211
212			`;***************************************************************`
213
214			`; int dskcap(int dskno)`
215			`dcap:`
216			`bne $4,$0,dcapser`
217			`j sctcapctl`
218			`dcapser:`
219			`j sctcapser`
220
221			`; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)`
222			`dio:`
223			`bne $4,$0,dioser`
224			`add $4,$5,$0`
225			`add $5,$6,$0`
226			`add $6,$7,$0`
227			`ldw $7,$29,16`
228			`j sctioctl`
229			`dioser:`
230			`add $4,$5,$0`
231			`add $5,$6,$0`
232			`add $6,$7,$0`
233			`ldw $7,$29,16`
234			`j sctioser`
235
236			`;***************************************************************`
237
238			`.code`
239			`.align 4`
240
241			`; Bool saveState(MonitorState *msp)`
242			`; always return 'true' here`
243			`saveState:`
244			`stw $31,$4,0*4 ; return address`
245			`stw $29,$4,1*4 ; stack pointer`
246			`stw $16,$4,2*4 ; local variables`
247			`stw $17,$4,3*4`
248			`stw $18,$4,4*4`
249			`stw $19,$4,5*4`
250			`stw $20,$4,6*4`
251			`stw $21,$4,7*4`
252			`stw $22,$4,8*4`
253			`stw $23,$4,9*4`
254			`add $2,$0,1`
255			`jr $31`
256
257			`; load state when re-entering monitor`
258			`; this appears as if returning from saveState`
259			`; but the return value is 'false' here`
260			`loadState:`
261			`ldw $8,$0,monitorReturn`
262			`beq $8,$0,loadState ; fatal error: monitor state lost`
263			`ldw $31,$8,0*4 ; return address`
264			`ldw $29,$8,1*4 ; stack pointer`
265			`ldw $16,$8,2*4 ; local variables`
266			`ldw $17,$8,3*4`
267			`ldw $18,$8,4*4`
268			`ldw $19,$8,5*4`
269			`ldw $20,$8,6*4`
270			`ldw $21,$8,7*4`
271			`ldw $22,$8,8*4`
272			`ldw $23,$8,9*4`
273			`add $2,$0,0`
274			`jr $31`
275
276			`.bss`
277			`.align 4`
278
279			`; extern MonitorState *monitorReturn`
280			`monitorReturn:`
281			`.space 4`
282
283			`; extern UserContext userContext`
284			`userContext:`
285			`.space USER_CONTEXT_SIZE`
286
287			`;***************************************************************`
288
289			`.code`
290			`.align 4`
291
292			`; void resume(void)`
293			`; use userContext to load state`
294			`resume:`
295			`mvts $0,PSW`
296			`add $28,$0,userContext`
297			`.nosyn`
298			`ldw $8,$28,33*4 ; tlbIndex`
299			`mvts $8,TLB_INDEX`
300			`ldw $8,$28,34*4 ; tlbWntryHi`
301			`mvts $8,TLB_ENTRY_HI`
302			`ldw $8,$28,35*4 ; tlbEntryLo`
303			`mvts $8,TLB_ENTRY_LO`
304			`;ldw $0,$28,0*4 ; registers`
305			`ldw $1,$28,1*4`
306			`ldw $2,$28,2*4`
307			`ldw $3,$28,3*4`
308			`ldw $4,$28,4*4`
309			`ldw $5,$28,5*4`
310			`ldw $6,$28,6*4`
311			`ldw $7,$28,7*4`
312			`ldw $8,$28,8*4`
313			`ldw $9,$28,9*4`
314			`ldw $10,$28,10*4`
315			`ldw $11,$28,11*4`
316			`ldw $12,$28,12*4`
317			`ldw $13,$28,13*4`
318			`ldw $14,$28,14*4`
319			`ldw $15,$28,15*4`
320			`ldw $16,$28,16*4`
321			`ldw $17,$28,17*4`
322			`ldw $18,$28,18*4`
323			`ldw $19,$28,19*4`
324			`ldw $20,$28,20*4`
325			`ldw $21,$28,21*4`
326			`ldw $22,$28,22*4`
327			`ldw $23,$28,23*4`
328			`ldw $24,$28,24*4`
329			`ldw $25,$28,25*4`
330			`ldw $26,$28,26*4`
331			`ldw $27,$28,27*4`
332			`;ldw $28,$28,28*4`
333			`ldw $29,$28,29*4`
334			`ldw $30,$28,30*4`
335			`ldw $31,$28,31*4`
336			`ldw $28,$28,32*4 ; psw`
337			`mvts $28,PSW`
338			`rfx`
339			`.syn`
340
341			`; interrupt entry`
342			`; use userContext to store state`
343			`isr:`
344			`umsr:`
345			`.nosyn`
346			`ldhi $28,userContext`
347			`or $28,$28,userContext`
348			`stw $0,$28,0*4 ; registers`
349			`stw $1,$28,1*4`
350			`stw $2,$28,2*4`
351			`stw $3,$28,3*4`
352			`stw $4,$28,4*4`
353			`stw $5,$28,5*4`
354			`stw $6,$28,6*4`
355			`stw $7,$28,7*4`
356			`stw $8,$28,8*4`
357			`stw $9,$28,9*4`
358			`stw $10,$28,10*4`
359			`stw $11,$28,11*4`
360			`stw $12,$28,12*4`
361			`stw $13,$28,13*4`
362			`stw $14,$28,14*4`
363			`stw $15,$28,15*4`
364			`stw $16,$28,16*4`
365			`stw $17,$28,17*4`
366			`stw $18,$28,18*4`
367			`stw $19,$28,19*4`
368			`stw $20,$28,20*4`
369			`stw $21,$28,21*4`
370			`stw $22,$28,22*4`
371			`stw $23,$28,23*4`
372			`stw $24,$28,24*4`
373			`stw $25,$28,25*4`
374			`stw $26,$28,26*4`
375			`stw $27,$28,27*4`
376			`stw $28,$28,28*4`
377			`stw $29,$28,29*4`
378			`stw $30,$28,30*4`
379			`stw $31,$28,31*4`
380			`mvfs $8,PSW`
381			`stw $8,$28,32*4 ; psw`
382			`mvfs $8,TLB_INDEX`
383			`stw $8,$28,33*4 ; tlbIndex`
384			`mvfs $8,TLB_ENTRY_HI`
385			`stw $8,$28,34*4 ; tlbEntryHi`
386			`mvfs $8,TLB_ENTRY_LO`
387			`stw $8,$28,35*4 ; tlbEntryLo`
388			`.syn`
389			`j loadState`