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[/] [eco32/] [tags/] [eco32-0.23/] [fpga/] [src/] [clk_reset/] [clk_reset.v] - Blame information for rev 27

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Line No. Rev Author Line
1 27 hellwig
module clk_reset(clk_in, reset_inout_n,
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                 sdram_clk, sdram_fb,
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                 clk, clk_ok, reset);
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    input clk_in;
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    inout reset_inout_n;
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    output sdram_clk;
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    input sdram_fb;
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    output clk;
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    output clk_ok;
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    output reset;
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  wire clk_in_buf;
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  wire int_clk;
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  wire int_locked;
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  wire ext_rst_n;
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  wire ext_fb;
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  wire ext_locked;
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  reg reset_p_n;
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  reg reset_s_n;
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  reg [23:0] reset_counter;
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  wire reset_counting;
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//--------------------------------------------------------------
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  IBUFG clk_in_buffer(.I(clk_in), .O(clk_in_buf));
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  DCM int_dcm (
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    .CLKIN(clk_in_buf),
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    .CLKFB(clk),
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    .RST(1'b0),
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    .CLK0(int_clk),
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    .LOCKED(int_locked)
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  );
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  BUFG int_clk_buffer(.I(int_clk), .O(clk));
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//--------------------------------------------------------------
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  SRL16 ext_dll_rst_gen(
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    .CLK(clk_in_buf),
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    .D(int_locked),
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    .Q(ext_rst_n),
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    .A0(1'b1),
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    .A1(1'b1),
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    .A2(1'b1),
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    .A3(1'b1)
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  );
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  defparam ext_dll_rst_gen.INIT = 16'h0000;
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//--------------------------------------------------------------
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  IBUFG ext_fb_buffer(.I(sdram_fb), .O(ext_fb));
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  DCM ext_dcm (
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    .CLKIN(clk_in_buf),
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    .CLKFB(ext_fb),
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    .RST(~ext_rst_n),
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    .CLK0(sdram_clk),
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    .LOCKED(ext_locked)
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  );
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  assign clk_ok = int_locked & ext_locked;
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//--------------------------------------------------------------
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  assign reset_counting = (reset_counter == 24'hFFFFFF) ? 0 : 1;
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  assign reset_inout_n = (reset_counter[23] == 0) ? 1'b0 : 1'bz;
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  always @(posedge clk_in_buf) begin
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    reset_p_n <= reset_inout_n;
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    reset_s_n <= reset_p_n;
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    if (reset_counting == 1) begin
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      reset_counter <= reset_counter + 1;
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    end else begin
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      if (int_locked == 0 ||
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          ext_locked == 0 ||
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          reset_s_n == 0) begin
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        reset_counter <= 24'h000000;
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      end
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    end
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  end
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  assign reset = reset_counting;
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endmodule

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