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[/] [eco32/] [tags/] [eco32-0.23/] [fpga/] [src/] [dsp/] [display.v] - Blame information for rev 185

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Line No. Rev Author Line
1 123 hellwig
//
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// display.v -- 30x80 character display, with attributes
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//
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6 27 hellwig
module display(clk,
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               dsp_row, dsp_col, dsp_en, dsp_wr,
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               dsp_wr_data, dsp_rd_data,
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               hsync, vsync, r, g, b);
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    input clk;
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    input [4:0] dsp_row;
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    input [6:0] dsp_col;
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    input dsp_en;
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    input dsp_wr;
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    input [15:0] dsp_wr_data;
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    output [15:0] dsp_rd_data;
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    output hsync;
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    output vsync;
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    output [2:0] r;
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    output [2:0] g;
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    output [2:0] b;
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  wire pixclk;
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  wire [4:0] timing_txtrow;
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  wire [6:0] timing_txtcol;
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  wire [3:0] timing_chrrow;
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  wire [2:0] timing_chrcol;
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  wire timing_blank;
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  wire timing_hsync;
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  wire timing_vsync;
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  wire timing_blink;
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  wire [7:0] dspmem_attcode;
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  wire [7:0] dspmem_chrcode;
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  wire [3:0] dspmem_chrrow;
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  wire [2:0] dspmem_chrcol;
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  wire dspmem_blank;
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  wire dspmem_hsync;
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  wire dspmem_vsync;
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  wire dspmem_blink;
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  wire [7:0] chrgen_attcode;
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  wire chrgen_pixel;
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  wire chrgen_blank;
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  wire chrgen_hsync;
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  wire chrgen_vsync;
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  wire chrgen_blink;
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  timing timing1(
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    .clk(clk),
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    .pixclk(pixclk),
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    .txtrow(timing_txtrow[4:0]),
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    .txtcol(timing_txtcol[6:0]),
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    .chrrow(timing_chrrow[3:0]),
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    .chrcol(timing_chrcol[2:0]),
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    .blank(timing_blank),
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    .hsync(timing_hsync),
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    .vsync(timing_vsync),
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    .blink(timing_blink)
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  );
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  dspmem dspmem1(
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    .rdwr_row(dsp_row[4:0]),
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    .rdwr_col(dsp_col[6:0]),
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    .wr_data(dsp_wr_data[15:0]),
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    .rd_data(dsp_rd_data[15:0]),
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    .en(dsp_en),
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    .wr(dsp_wr),
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    .clk(clk),
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    .pixclk(pixclk),
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    .txtrow(timing_txtrow[4:0]),
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    .txtcol(timing_txtcol[6:0]),
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    .attcode(dspmem_attcode[7:0]),
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    .chrcode(dspmem_chrcode[7:0]),
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    .chrrow_in(timing_chrrow[3:0]),
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    .chrcol_in(timing_chrcol[2:0]),
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    .blank_in(timing_blank),
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    .hsync_in(timing_hsync),
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    .vsync_in(timing_vsync),
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    .blink_in(timing_blink),
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    .chrrow_out(dspmem_chrrow[3:0]),
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    .chrcol_out(dspmem_chrcol[2:0]),
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    .blank_out(dspmem_blank),
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    .hsync_out(dspmem_hsync),
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    .vsync_out(dspmem_vsync),
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    .blink_out(dspmem_blink)
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  );
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  chrgen chrgen1(
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    .clk(clk),
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    .pixclk(pixclk),
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    .chrcode(dspmem_chrcode[7:0]),
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    .chrrow(dspmem_chrrow[3:0]),
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    .chrcol(dspmem_chrcol[2:0]),
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    .pixel(chrgen_pixel),
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    .attcode_in(dspmem_attcode[7:0]),
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    .blank_in(dspmem_blank),
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    .hsync_in(dspmem_hsync),
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    .vsync_in(dspmem_vsync),
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    .blink_in(dspmem_blink),
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    .attcode_out(chrgen_attcode[7:0]),
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    .blank_out(chrgen_blank),
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    .hsync_out(chrgen_hsync),
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    .vsync_out(chrgen_vsync),
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    .blink_out(chrgen_blink)
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  );
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  pixel pixel1(
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    .clk(clk),
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    .pixclk(pixclk),
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    .attcode(chrgen_attcode[7:0]),
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    .pixel(chrgen_pixel),
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    .blank(chrgen_blank),
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    .hsync_in(chrgen_hsync),
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    .vsync_in(chrgen_vsync),
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    .blink(chrgen_blink),
115 123 hellwig
    .hsync(hsync),
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    .vsync(vsync),
117 27 hellwig
    .r(r[2:0]),
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    .g(g[2:0]),
119 123 hellwig
    .b(b[2:0])
120 27 hellwig
  );
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endmodule

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