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[/] [eco32/] [tags/] [eco32-0.23/] [fpga/] [src/] [dsp/] [timing.v] - Blame information for rev 199

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Line No. Rev Author Line
1 123 hellwig 
//
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// timing.v -- timing generator
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//
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6 27 hellwig 
module timing(clk, pixclk,
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              txtrow, txtcol,
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              chrrow, chrcol,
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              blank, hsync, vsync, blink);
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    input clk;
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    output pixclk;
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    output [4:0] txtrow;
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    output [6:0] txtcol;
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    output [3:0] chrrow;
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    output [2:0] chrcol;
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    output blank;
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    output hsync;
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    output vsync;
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    output reg blink;
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  reg pclk;
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  reg [9:0] hcnt;
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  reg hblank, hsynch;
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  reg [9:0] vcnt;
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  reg vblank, vsynch;
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  reg [5:0] bcnt;
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  always @(posedge clk) begin
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    pclk <= ~pclk;
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  end
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  assign pixclk = pclk;
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  always @(posedge clk) begin
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    if (pclk == 1) begin
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      if (hcnt == 10'd799) begin
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        hcnt <= 10'd0;
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        hblank <= 1;
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      end else begin
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        hcnt <= hcnt + 1;
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      end
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      if (hcnt == 10'd639) begin
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        hblank <= 0;
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      end
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      if (hcnt == 10'd655) begin
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        hsynch <= 0;
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      end
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      if (hcnt == 10'd751) begin
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        hsynch <= 1;
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      end
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    end
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  end
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  always @(posedge clk) begin
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    if (pclk == 1 && hcnt == 10'd799) begin
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      if (vcnt == 10'd524) begin
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        vcnt <= 10'd0;
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        vblank <= 1;
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      end else begin
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        vcnt <= vcnt + 1;
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      end
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      if (vcnt == 10'd479) begin
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        vblank <= 0;
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      end
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      if (vcnt == 10'd489) begin
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        vsynch <= 0;
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      end
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      if (vcnt == 10'd491) begin
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        vsynch <= 1;
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      end
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    end
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  end
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  always @(posedge clk) begin
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    if (pclk == 1 && hcnt == 10'd799 && vcnt == 10'd524) begin
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      if (bcnt == 6'd59) begin
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        bcnt <= 6'd0;
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        blink <= 1;
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      end else begin
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        bcnt <= bcnt + 1;
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      end
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      if (bcnt == 6'd29) begin
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        blink <= 0;
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      end
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    end
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  end
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  assign blank = hblank & vblank;
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  assign hsync = hsynch;
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  assign vsync = vsynch;
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  assign txtrow[4:0] = vcnt[8:4];
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  assign txtcol[6:0] = hcnt[9:3];
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  assign chrrow[3:0] = vcnt[3:0];
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  assign chrcol[2:0] = hcnt[2:0];
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endmodule

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