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URL https://opencores.org/ocsvn/eco32/eco32/trunk

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[/] [eco32/] [tags/] [eco32-0.24/] [fpga/] [src/] [eco32.v] - Blame information for rev 211

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Line No. Rev Author Line
1 27 hellwig
//
2 68 hellwig
// eco32.v -- ECO32 top-level description
3 27 hellwig
//
4
 
5
 
6
module eco32(clk_in,
7
             reset_inout_n,
8
             sdram_clk,
9
             sdram_fb,
10
             sdram_cke,
11
             sdram_cs_n,
12
             sdram_ras_n,
13
             sdram_cas_n,
14
             sdram_we_n,
15
             sdram_ba,
16
             sdram_a,
17 125 hellwig
             sdram_udqm,
18
             sdram_ldqm,
19 27 hellwig
             sdram_dq,
20
             flash_ce_n,
21
             flash_oe_n,
22
             flash_we_n,
23
             flash_rst_n,
24
             flash_byte_n,
25
             flash_a,
26
             flash_d,
27 68 hellwig
             vga_hsync,
28
             vga_vsync,
29
             vga_r,
30
             vga_g,
31
             vga_b,
32 27 hellwig
             ps2_clk,
33
             ps2_data,
34
             rs232_0_rxd,
35
             rs232_0_txd,
36
             rs232_1_rxd,
37
             rs232_1_txd,
38
             pbus_d,
39
             pbus_a,
40
             pbus_read_n,
41
             pbus_write_n,
42
             ata_cs0_n,
43
             ata_cs1_n,
44
             ata_intrq,
45
             ata_dmarq,
46
             ata_dmack_n,
47
             ata_iordy,
48
             slot1_cs_n,
49
             slot2_cs_n,
50 191 hellwig
             ether_cs_n,
51 192 hellwig
             sw1_3,
52
             sw1_4,
53 191 hellwig
             sw2_n,
54
             sw3_n);
55 27 hellwig
 
56
    // clock and reset
57
    input clk_in;
58
    inout reset_inout_n;
59
    // SDRAM
60
    output sdram_clk;
61
    input sdram_fb;
62
    output sdram_cke;
63
    output sdram_cs_n;
64
    output sdram_ras_n;
65
    output sdram_cas_n;
66
    output sdram_we_n;
67
    output [1:0] sdram_ba;
68
    output [12:0] sdram_a;
69 125 hellwig
    output sdram_udqm;
70
    output sdram_ldqm;
71 27 hellwig
    inout [15:0] sdram_dq;
72
    // flash ROM
73
    output flash_ce_n;
74
    output flash_oe_n;
75
    output flash_we_n;
76
    output flash_rst_n;
77
    output flash_byte_n;
78
    output [19:0] flash_a;
79
    input [15:0] flash_d;
80
    // VGA display
81 68 hellwig
    output vga_hsync;
82
    output vga_vsync;
83
    output [2:0] vga_r;
84
    output [2:0] vga_g;
85
    output [2:0] vga_b;
86 27 hellwig
    // keyboard
87
    input ps2_clk;
88
    input ps2_data;
89
    // serial line 0
90
    input rs232_0_rxd;
91
    output rs232_0_txd;
92
    // serial line 1
93
    input rs232_1_rxd;
94
    output rs232_1_txd;
95
    // peripheral bus
96
    inout [15:0] pbus_d;
97
    output [4:0] pbus_a;
98
    output pbus_read_n;
99
    output pbus_write_n;
100
    // ATA adapter
101
    output ata_cs0_n;
102
    output ata_cs1_n;
103
    input ata_intrq;
104
    input ata_dmarq;
105
    output ata_dmack_n;
106
    input ata_iordy;
107
    // expansion slot 1
108
    output slot1_cs_n;
109
    // expansion slot 2
110
    output slot2_cs_n;
111
    // ethernet
112
    output ether_cs_n;
113 190 hellwig
    // board I/O
114 192 hellwig
    input sw1_3;
115
    input sw1_4;
116 191 hellwig
    input sw2_n;
117
    input sw3_n;
118 27 hellwig
 
119
  // clk_reset
120
  wire clk;
121
  wire clk_ok;
122
  wire reset;
123
  // cpu
124
  wire cpu_en;
125
  wire cpu_wr;
126
  wire [1:0] cpu_size;
127
  wire [31:0] cpu_addr;
128
  wire [31:0] cpu_data_in;
129
  wire [31:0] cpu_data_out;
130
  wire cpu_wt;
131
  wire [15:0] cpu_irq;
132
  // ram
133
  wire ram_en;
134
  wire ram_wr;
135
  wire [1:0] ram_size;
136
  wire [24:0] ram_addr;
137
  wire [31:0] ram_data_in;
138
  wire [31:0] ram_data_out;
139
  wire ram_wt;
140
  // rom
141
  wire rom_en;
142
  wire rom_wr;
143
  wire [1:0] rom_size;
144
  wire [20:0] rom_addr;
145
  wire [31:0] rom_data_out;
146
  wire rom_wt;
147 70 hellwig
  // tmr0
148
  wire tmr0_en;
149
  wire tmr0_wr;
150
  wire [3:2] tmr0_addr;
151
  wire [31:0] tmr0_data_in;
152
  wire [31:0] tmr0_data_out;
153
  wire tmr0_wt;
154
  wire tmr0_irq;
155
  // tmr1
156
  wire tmr1_en;
157
  wire tmr1_wr;
158
  wire [3:2] tmr1_addr;
159
  wire [31:0] tmr1_data_in;
160
  wire [31:0] tmr1_data_out;
161
  wire tmr1_wt;
162
  wire tmr1_irq;
163 27 hellwig
  // dsp
164
  wire dsp_en;
165
  wire dsp_wr;
166
  wire [13:2] dsp_addr;
167
  wire [15:0] dsp_data_in;
168
  wire [15:0] dsp_data_out;
169
  wire dsp_wt;
170
  // kbd
171
  wire kbd_en;
172
  wire kbd_wr;
173 67 hellwig
  wire kbd_addr;
174 27 hellwig
  wire [7:0] kbd_data_in;
175
  wire [7:0] kbd_data_out;
176
  wire kbd_wt;
177
  wire kbd_irq;
178
  // ser0
179
  wire ser0_en;
180
  wire ser0_wr;
181
  wire [3:2] ser0_addr;
182
  wire [7:0] ser0_data_in;
183
  wire [7:0] ser0_data_out;
184
  wire ser0_wt;
185
  wire ser0_irq_r;
186
  wire ser0_irq_t;
187
  // ser1
188
  wire ser1_en;
189
  wire ser1_wr;
190
  wire [3:2] ser1_addr;
191
  wire [7:0] ser1_data_in;
192
  wire [7:0] ser1_data_out;
193
  wire ser1_wt;
194
  wire ser1_irq_r;
195
  wire ser1_irq_t;
196
  // dsk
197
  wire dsk_en;
198
  wire dsk_wr;
199
  wire [19:2] dsk_addr;
200
  wire [31:0] dsk_data_in;
201
  wire [31:0] dsk_data_out;
202
  wire dsk_wt;
203
  wire dsk_irq;
204 190 hellwig
  // bio
205
  wire bio_en;
206
  wire bio_wr;
207
  wire bio_addr;
208
  wire [31:0] bio_data_in;
209
  wire [31:0] bio_data_out;
210
  wire bio_wt;
211 27 hellwig
 
212
  clk_reset clk_reset1(
213
    .clk_in(clk_in),
214
    .reset_inout_n(reset_inout_n),
215
    .sdram_clk(sdram_clk),
216
    .sdram_fb(sdram_fb),
217
    .clk(clk),
218
    .clk_ok(clk_ok),
219
    .reset(reset)
220
  );
221
 
222
  busctrl busctrl1(
223
    // cpu
224
    .cpu_en(cpu_en),
225
    .cpu_wr(cpu_wr),
226
    .cpu_size(cpu_size[1:0]),
227
    .cpu_addr(cpu_addr[31:0]),
228
    .cpu_data_in(cpu_data_in[31:0]),
229
    .cpu_data_out(cpu_data_out[31:0]),
230
    .cpu_wt(cpu_wt),
231
    // ram
232
    .ram_en(ram_en),
233
    .ram_wr(ram_wr),
234
    .ram_size(ram_size[1:0]),
235
    .ram_addr(ram_addr[24:0]),
236
    .ram_data_in(ram_data_in[31:0]),
237
    .ram_data_out(ram_data_out[31:0]),
238
    .ram_wt(ram_wt),
239
    // rom
240
    .rom_en(rom_en),
241
    .rom_wr(rom_wr),
242
    .rom_size(rom_size[1:0]),
243
    .rom_addr(rom_addr[20:0]),
244
    .rom_data_out(rom_data_out[31:0]),
245
    .rom_wt(rom_wt),
246 70 hellwig
    // tmr0
247
    .tmr0_en(tmr0_en),
248
    .tmr0_wr(tmr0_wr),
249
    .tmr0_addr(tmr0_addr[3:2]),
250
    .tmr0_data_in(tmr0_data_in[31:0]),
251
    .tmr0_data_out(tmr0_data_out[31:0]),
252
    .tmr0_wt(tmr0_wt),
253
    // tmr1
254
    .tmr1_en(tmr1_en),
255
    .tmr1_wr(tmr1_wr),
256
    .tmr1_addr(tmr1_addr[3:2]),
257
    .tmr1_data_in(tmr1_data_in[31:0]),
258
    .tmr1_data_out(tmr1_data_out[31:0]),
259
    .tmr1_wt(tmr1_wt),
260 27 hellwig
    // dsp
261
    .dsp_en(dsp_en),
262
    .dsp_wr(dsp_wr),
263
    .dsp_addr(dsp_addr[13:2]),
264
    .dsp_data_in(dsp_data_in[15:0]),
265
    .dsp_data_out(dsp_data_out[15:0]),
266
    .dsp_wt(dsp_wt),
267
    // kbd
268
    .kbd_en(kbd_en),
269
    .kbd_wr(kbd_wr),
270 67 hellwig
    .kbd_addr(kbd_addr),
271 27 hellwig
    .kbd_data_in(kbd_data_in[7:0]),
272
    .kbd_data_out(kbd_data_out[7:0]),
273
    .kbd_wt(kbd_wt),
274
    // ser0
275
    .ser0_en(ser0_en),
276
    .ser0_wr(ser0_wr),
277
    .ser0_addr(ser0_addr[3:2]),
278
    .ser0_data_in(ser0_data_in[7:0]),
279
    .ser0_data_out(ser0_data_out[7:0]),
280
    .ser0_wt(ser0_wt),
281
    // ser1
282
    .ser1_en(ser1_en),
283
    .ser1_wr(ser1_wr),
284
    .ser1_addr(ser1_addr[3:2]),
285
    .ser1_data_in(ser1_data_in[7:0]),
286
    .ser1_data_out(ser1_data_out[7:0]),
287
    .ser1_wt(ser1_wt),
288
    // dsk
289
    .dsk_en(dsk_en),
290
    .dsk_wr(dsk_wr),
291
    .dsk_addr(dsk_addr[19:2]),
292
    .dsk_data_in(dsk_data_in[31:0]),
293
    .dsk_data_out(dsk_data_out[31:0]),
294 190 hellwig
    .dsk_wt(dsk_wt),
295
    // bio
296
    .bio_en(bio_en),
297
    .bio_wr(bio_wr),
298
    .bio_addr(bio_addr),
299
    .bio_data_in(bio_data_in[31:0]),
300
    .bio_data_out(bio_data_out[31:0]),
301
    .bio_wt(bio_wt)
302 27 hellwig
  );
303
 
304
  cpu cpu1(
305
    .clk(clk),
306
    .reset(reset),
307
    .bus_en(cpu_en),
308
    .bus_wr(cpu_wr),
309
    .bus_size(cpu_size[1:0]),
310
    .bus_addr(cpu_addr[31:0]),
311
    .bus_data_in(cpu_data_in[31:0]),
312
    .bus_data_out(cpu_data_out[31:0]),
313
    .bus_wt(cpu_wt),
314
    .irq(cpu_irq[15:0])
315
  );
316
 
317 70 hellwig
  assign cpu_irq[15] = tmr1_irq;
318
  assign cpu_irq[14] = tmr0_irq;
319 27 hellwig
  assign cpu_irq[13] = 1'b0;
320
  assign cpu_irq[12] = 1'b0;
321
  assign cpu_irq[11] = 1'b0;
322
  assign cpu_irq[10] = 1'b0;
323
  assign cpu_irq[ 9] = 1'b0;
324
  assign cpu_irq[ 8] = dsk_irq;
325
  assign cpu_irq[ 7] = 1'b0;
326
  assign cpu_irq[ 6] = 1'b0;
327
  assign cpu_irq[ 5] = 1'b0;
328
  assign cpu_irq[ 4] = kbd_irq;
329
  assign cpu_irq[ 3] = ser1_irq_r;
330
  assign cpu_irq[ 2] = ser1_irq_t;
331
  assign cpu_irq[ 1] = ser0_irq_r;
332
  assign cpu_irq[ 0] = ser0_irq_t;
333
 
334
  ram ram1(
335
    .clk(clk),
336
    .clk_ok(clk_ok),
337
    .reset(reset),
338
    .en(ram_en),
339
    .wr(ram_wr),
340
    .size(ram_size[1:0]),
341
    .addr(ram_addr[24:0]),
342
    .data_in(ram_data_in[31:0]),
343
    .data_out(ram_data_out[31:0]),
344
    .wt(ram_wt),
345
    .sdram_cke(sdram_cke),
346
    .sdram_cs_n(sdram_cs_n),
347
    .sdram_ras_n(sdram_ras_n),
348
    .sdram_cas_n(sdram_cas_n),
349
    .sdram_we_n(sdram_we_n),
350
    .sdram_ba(sdram_ba[1:0]),
351
    .sdram_a(sdram_a[12:0]),
352 125 hellwig
    .sdram_udqm(sdram_udqm),
353
    .sdram_ldqm(sdram_ldqm),
354 27 hellwig
    .sdram_dq(sdram_dq[15:0])
355
  );
356
 
357
  rom rom1(
358
    .clk(clk),
359
    .reset(reset),
360
    .en(rom_en),
361
    .wr(rom_wr),
362
    .size(rom_size[1:0]),
363
    .addr(rom_addr[20:0]),
364
    .data_out(rom_data_out[31:0]),
365
    .wt(rom_wt),
366
    .ce_n(flash_ce_n),
367
    .oe_n(flash_oe_n),
368
    .we_n(flash_we_n),
369
    .rst_n(flash_rst_n),
370
    .byte_n(flash_byte_n),
371
    .a(flash_a[19:0]),
372
    .d(flash_d[15:0])
373
  );
374
 
375 70 hellwig
  tmr tmr1_0(
376 27 hellwig
    .clk(clk),
377
    .reset(reset),
378 70 hellwig
    .en(tmr0_en),
379
    .wr(tmr0_wr),
380
    .addr(tmr0_addr[3:2]),
381
    .data_in(tmr0_data_in[31:0]),
382
    .data_out(tmr0_data_out[31:0]),
383
    .wt(tmr0_wt),
384
    .irq(tmr0_irq)
385 27 hellwig
  );
386
 
387 70 hellwig
  tmr tmr1_1(
388
    .clk(clk),
389
    .reset(reset),
390
    .en(tmr1_en),
391
    .wr(tmr1_wr),
392
    .addr(tmr1_addr[3:2]),
393
    .data_in(tmr1_data_in[31:0]),
394
    .data_out(tmr1_data_out[31:0]),
395
    .wt(tmr1_wt),
396
    .irq(tmr1_irq)
397
  );
398
 
399 27 hellwig
  dsp dsp1(
400
    .clk(clk),
401
    .reset(reset),
402
    .en(dsp_en),
403
    .wr(dsp_wr),
404
    .addr(dsp_addr[13:2]),
405
    .data_in(dsp_data_in[15:0]),
406
    .data_out(dsp_data_out[15:0]),
407
    .wt(dsp_wt),
408 68 hellwig
    .hsync(vga_hsync),
409
    .vsync(vga_vsync),
410
    .r(vga_r[2:0]),
411
    .g(vga_g[2:0]),
412
    .b(vga_b[2:0])
413 27 hellwig
  );
414
 
415
  kbd kbd1(
416
    .clk(clk),
417
    .reset(reset),
418
    .en(kbd_en),
419
    .wr(kbd_wr),
420 67 hellwig
    .addr(kbd_addr),
421 27 hellwig
    .data_in(kbd_data_in[7:0]),
422
    .data_out(kbd_data_out[7:0]),
423
    .wt(kbd_wt),
424 116 hellwig
    .irq(kbd_irq),
425
    .ps2_clk(ps2_clk),
426
    .ps2_data(ps2_data)
427 27 hellwig
  );
428
 
429
  ser ser1_0(
430
    .clk(clk),
431
    .reset(reset),
432
    .en(ser0_en),
433
    .wr(ser0_wr),
434
    .addr(ser0_addr[3:2]),
435
    .data_in(ser0_data_in[7:0]),
436
    .data_out(ser0_data_out[7:0]),
437
    .wt(ser0_wt),
438
    .irq_r(ser0_irq_r),
439
    .irq_t(ser0_irq_t),
440
    .rxd(rs232_0_rxd),
441
    .txd(rs232_0_txd)
442
  );
443
 
444
  ser ser1_1(
445
    .clk(clk),
446
    .reset(reset),
447
    .en(ser1_en),
448
    .wr(ser1_wr),
449
    .addr(ser1_addr[3:2]),
450
    .data_in(ser1_data_in[7:0]),
451
    .data_out(ser1_data_out[7:0]),
452
    .wt(ser1_wt),
453
    .irq_r(ser1_irq_r),
454
    .irq_t(ser1_irq_t),
455
    .rxd(rs232_1_rxd),
456
    .txd(rs232_1_txd)
457
  );
458
 
459
  dsk dsk1(
460
    .clk(clk),
461
    .reset(reset),
462
    .en(dsk_en),
463
    .wr(dsk_wr),
464
    .addr(dsk_addr[19:2]),
465
    .data_in(dsk_data_in[31:0]),
466
    .data_out(dsk_data_out[31:0]),
467
    .wt(dsk_wt),
468
    .irq(dsk_irq),
469
    .ata_d(pbus_d[15:0]),
470
    .ata_a(pbus_a[2:0]),
471
    .ata_cs0_n(ata_cs0_n),
472
    .ata_cs1_n(ata_cs1_n),
473
    .ata_dior_n(pbus_read_n),
474
    .ata_diow_n(pbus_write_n),
475
    .ata_intrq(ata_intrq),
476
    .ata_dmarq(ata_dmarq),
477
    .ata_dmack_n(ata_dmack_n),
478
    .ata_iordy(ata_iordy)
479
  );
480
 
481
  assign pbus_a[4:3] = 2'b00;
482
  assign slot1_cs_n = 1;
483
  assign slot2_cs_n = 1;
484
  assign ether_cs_n = 1;
485
 
486 190 hellwig
  bio bio1(
487
    .clk(clk),
488
    .reset(reset),
489
    .en(bio_en),
490
    .wr(bio_wr),
491
    .addr(bio_addr),
492
    .data_in(bio_data_in[31:0]),
493
    .data_out(bio_data_out[31:0]),
494 191 hellwig
    .wt(bio_wt),
495 192 hellwig
    .sw1_1(flash_a[19]),
496
    .sw1_2(flash_a[18]),
497
    .sw1_3(sw1_3),
498
    .sw1_4(sw1_4),
499 191 hellwig
    .sw2_n(sw2_n),
500
    .sw3_n(sw3_n)
501 190 hellwig
  );
502
 
503 27 hellwig
endmodule

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