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[/] [eco32/] [tags/] [eco32-0.24/] [fpga/] [src/] [ram/] [ram.v] - Blame information for rev 211

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//
// ram.v -- main memory, using SDRAM
//
 
 
module ram(clk, clk_ok, reset,
           en, wr, size, addr,
           data_in, data_out, wt,
           sdram_cke, sdram_cs_n,
           sdram_ras_n, sdram_cas_n,
           sdram_we_n, sdram_ba, sdram_a,
           sdram_udqm, sdram_ldqm, sdram_dq);
    // internal interface signals
    input clk;
    input clk_ok;
    input reset;
    input en;
    input wr;
    input [1:0] size;
    input [24:0] addr;
    input [31:0] data_in;
    output reg [31:0] data_out;
    output reg wt;
    // SDRAM interface signals
    output sdram_cke;
    output sdram_cs_n;
    output sdram_ras_n;
    output sdram_cas_n;
    output sdram_we_n;
    output [1:0] sdram_ba;
    output [12:0] sdram_a;
    output sdram_udqm;
    output sdram_ldqm;
    inout [15:0] sdram_dq;
 
  reg [3:0] state;
  reg a0;
  reg cntl_read;
  reg cntl_write;
  wire cntl_done;
  wire [23:0] cntl_addr;
  reg [15:0] cntl_din;
  wire [15:0] cntl_dout;
 
  wire sd_out_en;
  wire [15:0] sd_out;
 
//--------------------------------------------------------------
 
  sdramCntl sdramCntl1(
    // clock
    .clk(clk),
    .clk_ok(clk_ok),
    // host side
    .rd(cntl_read & ~cntl_done),
    .wr(cntl_write & ~cntl_done),
    .done(cntl_done),
    .hAddr(cntl_addr),
    .hDIn(cntl_din),
    .hDOut(cntl_dout),
    // SDRAM side
    .cke(sdram_cke),
    .ce_n(sdram_cs_n),
    .ras_n(sdram_ras_n),
    .cas_n(sdram_cas_n),
    .we_n(sdram_we_n),
    .ba(sdram_ba),
    .sAddr(sdram_a),
    .sDIn(sdram_dq),
    .sDOut(sd_out),
    .sDOutEn(sd_out_en),
    .dqmh(sdram_udqm),
    .dqml(sdram_ldqm)
  );
 
  assign sdram_dq = (sd_out_en == 1) ? sd_out : 16'hzzzz;
 
//--------------------------------------------------------------
 
  // the SDRAM is organized in 16-bit halfwords
  // address line 0 is controlled by the state machine
  // (this is necessary for word accesses)
  assign cntl_addr[23:1] = addr[24:2];
  assign cntl_addr[0] = a0;
 
  // state machine for SDRAM access
  always @(posedge clk) begin
    if (reset == 1) begin
      state <= 4'b0000;
      wt <= 1;
    end else begin
      case (state)
        4'b0000:
          // wait for access
          begin
            if (en == 1) begin
              // access
              if (wr == 1) begin
                // write
                if (size[1] == 1) begin
                  // write word
                  state <= 4'b0001;
                end else begin
                  if (size[0] == 1) begin
                    // write halfword
                    state <= 4'b0101;
                  end else begin
                    // write byte
                    state <= 4'b0111;
                  end
                end
              end else begin
                // read
                if (size[1] == 1) begin
                  // read word
                  state <= 4'b0011;
                end else begin
                  if (size[0] == 1) begin
                    // read halfword
                    state <= 4'b0110;
                  end else begin
                    // read byte
                    state <= 4'b1001;
                  end
                end
              end
            end
          end
        4'b0001:
          // write word, upper 16 bits
          begin
            if (cntl_done == 1) begin
              state <= 4'b0010;
            end
          end
        4'b0010:
          // write word, lower 16 bits
          begin
            if (cntl_done == 1) begin
              state <= 4'b1111;
              wt <= 0;
            end
          end
        4'b0011:
          // read word, upper 16 bits
          begin
            if (cntl_done == 1) begin
              state <= 4'b0100;
              data_out[31:16] <= cntl_dout;
            end
          end
        4'b0100:
          // read word, lower 16 bits
          begin
            if (cntl_done == 1) begin
              state <= 4'b1111;
              data_out[15:0] <= cntl_dout;
              wt <= 0;
            end
          end
        4'b0101:
          // write halfword
          begin
            if (cntl_done == 1) begin
              state <= 4'b1111;
              wt <= 0;
            end
          end
        4'b0110:
          // read halfword
          begin
            if (cntl_done == 1) begin
              state <= 4'b1111;
              data_out[31:16] <= 16'h0000;
              data_out[15:0] <= cntl_dout;
              wt <= 0;
            end
          end
        4'b0111:
          // write byte (read halfword cycle)
          begin
            if (cntl_done == 1) begin
              state <= 4'b1000;
              data_out[31:16] <= 16'h0000;
              data_out[15:0] <= cntl_dout;
            end
          end
        4'b1000:
          // write byte (write halfword cycle)
          begin
            if (cntl_done == 1) begin
              state <= 4'b1111;
              wt <= 0;
            end
          end
        4'b1001:
          // read byte
          begin
            if (cntl_done == 1) begin
              state <= 4'b1111;
              data_out[31:8] <= 24'h000000;
              if (addr[0] == 0) begin
                data_out[7:0] <= cntl_dout[15:8];
              end else begin
                data_out[7:0] <= cntl_dout[7:0];
              end
              wt <= 0;
            end
          end
        4'b1111:
          // end of bus cycle
          begin
            state <= 4'b0000;
            wt <= 1;
          end
        default:
          // all other states: reset
          begin
            state <= 4'b0000;
            wt <= 1;
          end
      endcase
    end
  end
 
  // output of state machine
  always @(*) begin
    case (state)
      4'b0000:
        // wait for access
        begin
          a0 = 1'bx;
          cntl_read = 0;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      4'b0001:
        // write word, upper 16 bits
        begin
          a0 = 1'b0;
          cntl_read = 0;
          cntl_write = 1;
          cntl_din = data_in[31:16];
        end
      4'b0010:
        // write word, lower 16 bits
        begin
          a0 = 1'b1;
          cntl_read = 0;
          cntl_write = 1;
          cntl_din = data_in[15:0];
        end
      4'b0011:
        // read word, upper 16 bits
        begin
          a0 = 1'b0;
          cntl_read = 1;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      4'b0100:
        // read word, lower 16 bits
        begin
          a0 = 1'b1;
          cntl_read = 1;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      4'b0101:
        // write halfword
        begin
          a0 = addr[1];
          cntl_read = 0;
          cntl_write = 1;
          cntl_din = data_in[15:0];
        end
      4'b0110:
        // read halfword
        begin
          a0 = addr[1];
          cntl_read = 1;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      4'b0111:
        // write byte (read halfword cycle)
        begin
          a0 = addr[1];
          cntl_read = 1;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      4'b1000:
        // write byte (write halfword cycle)
        begin
          a0 = addr[1];
          cntl_read = 0;
          cntl_write = 1;
          if (addr[0] == 0) begin
            cntl_din = { data_in[7:0], data_out[7:0] };
          end else begin
            cntl_din = { data_out[15:8], data_in[7:0] };
          end
        end
      4'b1001:
        // read byte
        begin
          a0 = addr[1];
          cntl_read = 1;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      4'b1111:
        // end of bus cycle
        begin
          a0 = 1'bx;
          cntl_read = 0;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      default:
        // all other states: reset
        begin
          a0 = 1'bx;
          cntl_read = 0;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
    endcase
  end
 
endmodule

Line No.	Rev	Author	Line
1	119	hellwig	`//`
2			`// ram.v -- main memory, using SDRAM`
3			`//`
4
5
6	27	hellwig	`module ram(clk, clk_ok, reset,`
7			`en, wr, size, addr,`
8			`data_in, data_out, wt,`
9			`sdram_cke, sdram_cs_n,`
10			`sdram_ras_n, sdram_cas_n,`
11	126	hellwig	`sdram_we_n, sdram_ba, sdram_a,`
12			`sdram_udqm, sdram_ldqm, sdram_dq);`
13	119	hellwig	`// internal interface signals`
14	27	hellwig	`input clk;`
15			`input clk_ok;`
16			`input reset;`
17			`input en;`
18			`input wr;`
19			`input [1:0] size;`
20			`input [24:0] addr;`
21			`input [31:0] data_in;`
22			`output reg [31:0] data_out;`
23			`output reg wt;`
24	119	hellwig	`// SDRAM interface signals`
25	27	hellwig	`output sdram_cke;`
26			`output sdram_cs_n;`
27			`output sdram_ras_n;`
28			`output sdram_cas_n;`
29			`output sdram_we_n;`
30			`output [1:0] sdram_ba;`
31			`output [12:0] sdram_a;`
32	126	hellwig	`output sdram_udqm;`
33			`output sdram_ldqm;`
34	27	hellwig	`inout [15:0] sdram_dq;`
35
36			`reg [3:0] state;`
37			`reg a0;`
38			`reg cntl_read;`
39			`reg cntl_write;`
40			`wire cntl_done;`
41			`wire [23:0] cntl_addr;`
42			`reg [15:0] cntl_din;`
43			`wire [15:0] cntl_dout;`
44
45			`wire sd_out_en;`
46			`wire [15:0] sd_out;`
47
48			`//--------------------------------------------------------------`
49
50			`sdramCntl sdramCntl1(`
51			`// clock`
52			`.clk(clk),`
53			`.clk_ok(clk_ok),`
54			`// host side`
55			`.rd(cntl_read & ~cntl_done),`
56			`.wr(cntl_write & ~cntl_done),`
57			`.done(cntl_done),`
58			`.hAddr(cntl_addr),`
59			`.hDIn(cntl_din),`
60			`.hDOut(cntl_dout),`
61			`// SDRAM side`
62			`.cke(sdram_cke),`
63			`.ce_n(sdram_cs_n),`
64			`.ras_n(sdram_ras_n),`
65			`.cas_n(sdram_cas_n),`
66			`.we_n(sdram_we_n),`
67			`.ba(sdram_ba),`
68			`.sAddr(sdram_a),`
69			`.sDIn(sdram_dq),`
70			`.sDOut(sd_out),`
71			`.sDOutEn(sd_out_en),`
72			`.dqmh(sdram_udqm),`
73			`.dqml(sdram_ldqm)`
74			`);`
75
76			`assign sdram_dq = (sd_out_en == 1) ? sd_out : 16'hzzzz;`
77
78			`//--------------------------------------------------------------`
79
80			`// the SDRAM is organized in 16-bit halfwords`
81			`// address line 0 is controlled by the state machine`
82	119	hellwig	`// (this is necessary for word accesses)`
83	27	hellwig	`assign cntl_addr[23:1] = addr[24:2];`
84			`assign cntl_addr[0] = a0;`
85
86			`// state machine for SDRAM access`
87			`always @(posedge clk) begin`
88			`if (reset == 1) begin`
89			`state <= 4'b0000;`
90			`wt <= 1;`
91			`end else begin`
92			`case (state)`
93			`4'b0000:`
94			`// wait for access`
95			`begin`
96			`if (en == 1) begin`
97			`// access`
98			`if (wr == 1) begin`
99			`// write`
100			`if (size[1] == 1) begin`
101			`// write word`
102			`state <= 4'b0001;`
103			`end else begin`
104			`if (size[0] == 1) begin`
105			`// write halfword`
106			`state <= 4'b0101;`
107			`end else begin`
108			`// write byte`
109			`state <= 4'b0111;`
110			`end`
111			`end`
112			`end else begin`
113			`// read`
114			`if (size[1] == 1) begin`
115			`// read word`
116			`state <= 4'b0011;`
117			`end else begin`
118			`if (size[0] == 1) begin`
119			`// read halfword`
120			`state <= 4'b0110;`
121			`end else begin`
122			`// read byte`
123			`state <= 4'b1001;`
124			`end`
125			`end`
126			`end`
127			`end`
128			`end`
129			`4'b0001:`
130			`// write word, upper 16 bits`
131			`begin`
132			`if (cntl_done == 1) begin`
133			`state <= 4'b0010;`
134			`end`
135			`end`
136			`4'b0010:`
137			`// write word, lower 16 bits`
138			`begin`
139			`if (cntl_done == 1) begin`
140			`state <= 4'b1111;`
141			`wt <= 0;`
142			`end`
143			`end`
144			`4'b0011:`
145			`// read word, upper 16 bits`
146			`begin`
147			`if (cntl_done == 1) begin`
148			`state <= 4'b0100;`
149			`data_out[31:16] <= cntl_dout;`
150			`end`
151			`end`
152			`4'b0100:`
153			`// read word, lower 16 bits`
154			`begin`
155			`if (cntl_done == 1) begin`
156			`state <= 4'b1111;`
157			`data_out[15:0] <= cntl_dout;`
158			`wt <= 0;`
159			`end`
160			`end`
161			`4'b0101:`
162			`// write halfword`
163			`begin`
164			`if (cntl_done == 1) begin`
165			`state <= 4'b1111;`
166			`wt <= 0;`
167			`end`
168			`end`
169			`4'b0110:`
170			`// read halfword`
171			`begin`
172			`if (cntl_done == 1) begin`
173			`state <= 4'b1111;`
174			`data_out[31:16] <= 16'h0000;`
175			`data_out[15:0] <= cntl_dout;`
176			`wt <= 0;`
177			`end`
178			`end`
179			`4'b0111:`
180			`// write byte (read halfword cycle)`
181			`begin`
182			`if (cntl_done == 1) begin`
183			`state <= 4'b1000;`
184			`data_out[31:16] <= 16'h0000;`
185			`data_out[15:0] <= cntl_dout;`
186			`end`
187			`end`
188			`4'b1000:`
189			`// write byte (write halfword cycle)`
190			`begin`
191			`if (cntl_done == 1) begin`
192			`state <= 4'b1111;`
193			`wt <= 0;`
194			`end`
195			`end`
196			`4'b1001:`
197			`// read byte`
198			`begin`
199			`if (cntl_done == 1) begin`
200			`state <= 4'b1111;`
201			`data_out[31:8] <= 24'h000000;`
202			`if (addr[0] == 0) begin`
203			`data_out[7:0] <= cntl_dout[15:8];`
204			`end else begin`
205			`data_out[7:0] <= cntl_dout[7:0];`
206			`end`
207			`wt <= 0;`
208			`end`
209			`end`
210			`4'b1111:`
211			`// end of bus cycle`
212			`begin`
213			`state <= 4'b0000;`
214			`wt <= 1;`
215			`end`
216			`default:`
217			`// all other states: reset`
218			`begin`
219			`state <= 4'b0000;`
220			`wt <= 1;`
221			`end`
222			`endcase`
223			`end`
224			`end`
225
226			`// output of state machine`
227			`always @(*) begin`
228			`case (state)`
229			`4'b0000:`
230			`// wait for access`
231			`begin`
232			`a0 = 1'bx;`
233			`cntl_read = 0;`
234			`cntl_write = 0;`
235			`cntl_din = 16'hxxxx;`
236			`end`
237			`4'b0001:`
238			`// write word, upper 16 bits`
239			`begin`
240			`a0 = 1'b0;`
241			`cntl_read = 0;`
242			`cntl_write = 1;`
243			`cntl_din = data_in[31:16];`
244			`end`
245			`4'b0010:`
246			`// write word, lower 16 bits`
247			`begin`
248			`a0 = 1'b1;`
249			`cntl_read = 0;`
250			`cntl_write = 1;`
251			`cntl_din = data_in[15:0];`
252			`end`
253			`4'b0011:`
254			`// read word, upper 16 bits`
255			`begin`
256			`a0 = 1'b0;`
257			`cntl_read = 1;`
258			`cntl_write = 0;`
259			`cntl_din = 16'hxxxx;`
260			`end`
261			`4'b0100:`
262			`// read word, lower 16 bits`
263			`begin`
264			`a0 = 1'b1;`
265			`cntl_read = 1;`
266			`cntl_write = 0;`
267			`cntl_din = 16'hxxxx;`
268			`end`
269			`4'b0101:`
270			`// write halfword`
271			`begin`
272			`a0 = addr[1];`
273			`cntl_read = 0;`
274			`cntl_write = 1;`
275			`cntl_din = data_in[15:0];`
276			`end`
277			`4'b0110:`
278			`// read halfword`
279			`begin`
280			`a0 = addr[1];`
281			`cntl_read = 1;`
282			`cntl_write = 0;`
283			`cntl_din = 16'hxxxx;`
284			`end`
285			`4'b0111:`
286			`// write byte (read halfword cycle)`
287			`begin`
288			`a0 = addr[1];`
289			`cntl_read = 1;`
290			`cntl_write = 0;`
291			`cntl_din = 16'hxxxx;`
292			`end`
293			`4'b1000:`
294			`// write byte (write halfword cycle)`
295			`begin`
296			`a0 = addr[1];`
297			`cntl_read = 0;`
298			`cntl_write = 1;`
299			`if (addr[0] == 0) begin`
300			`cntl_din = { data_in[7:0], data_out[7:0] };`
301			`end else begin`
302			`cntl_din = { data_out[15:8], data_in[7:0] };`
303			`end`
304			`end`
305			`4'b1001:`
306			`// read byte`
307			`begin`
308			`a0 = addr[1];`
309			`cntl_read = 1;`
310			`cntl_write = 0;`
311			`cntl_din = 16'hxxxx;`
312			`end`
313			`4'b1111:`
314			`// end of bus cycle`
315			`begin`
316			`a0 = 1'bx;`
317			`cntl_read = 0;`
318			`cntl_write = 0;`
319			`cntl_din = 16'hxxxx;`
320			`end`
321			`default:`
322			`// all other states: reset`
323			`begin`
324			`a0 = 1'bx;`
325			`cntl_read = 0;`
326			`cntl_write = 0;`
327			`cntl_din = 16'hxxxx;`
328			`end`
329			`endcase`
330			`end`
331
332			`endmodule`

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[/] [eco32/] [tags/] [eco32-0.24/] [fpga/] [src/] [ram/] [ram.v] - Blame information for rev 211