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[/] [eco32/] [tags/] [eco32-0.25/] [fpga/] [src/] [ram/] [ddr/] [ddr_sdram.v] - Blame information for rev 219

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////////////////////////////////////////////////////////////////////////////
//
// Create Date:    02/11/07
// Last Change:    01/22/12
// Design Name:    DDR SDRAM memory controller
// Module Name:    ddr_sdram
// Description:    memory controller for DDR SDRAM
//                 hard coded for 8 Meg x 16 x 4 banks
//
// Revision:
// Revision 0.01 - File Created
//
// Development platform: Spartan-3E Starter kit
//
// Copyright (C) 2007, Rick Huang
//
// Modifications by Hellwig Geisse, 2012
//   - sd_CK_P and sd_CK_N supplied by this module
//   - DDR output registers for sd_CK_P and sd_CK_N added
//   - sd_CLK_O deleted
//   - debug output deleted
//   - burst mode sections of the state machine deleted
//     (have been commented out already)
//   - additional states SD_RD_DONE_1 and SD_WR_DONE_1 inserted
//     (in order to stretch the wACK_O signal, which is to be
//     recognized by external circuits clocked with 50 MHz)
//   - four "write byte" signals added to interface
//     (to allow 8 and 16 bit write operations too)
//   - mask registers UDM_reg_O and LDM_reg_O deleted
//   - DDR output registers for sd_UDM_O and sd_LDM_O added
//   - data_sample_en and its associated multiplexer removed
//     (apparently a debugging vehicle)
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
// MA  02110-1301  USA
//
////////////////////////////////////////////////////////////////////////////
 
module ddr_sdram(sd_CK_P, sd_CK_N,
                 sd_A_O, sd_BA_O, sd_D_IO,
                 sd_RAS_O, sd_CAS_O, sd_WE_O,
                 sd_UDM_O, sd_LDM_O,
                 sd_UDQS_IO, sd_LDQS_IO,
                 sd_CS_O, sd_CKE_O,
                 clk0, clk90,
                 clk180, clk270,
                 reset,
                 wADR_I, wSTB_I, wWE_I, wWRB_I,
                 wDAT_I, wDAT_O, wACK_O);
        // interface to DDR SDRAM memory
        output  sd_CK_P;
        output  sd_CK_N;
        output  [12:0] sd_A_O;
        output  [1:0]  sd_BA_O;
        inout   [15:0] sd_D_IO;
        output  sd_RAS_O;
        output  sd_CAS_O;
        output  sd_WE_O;
        output  sd_UDM_O;
        output  sd_LDM_O;
        inout   sd_UDQS_IO;
        inout   sd_LDQS_IO;
        output  sd_CS_O;
        output  sd_CKE_O;
        // internal interface signals
        input   clk0;
        input   clk90;
        input   clk180;
        input   clk270;
        input   reset;
        // A[25:24] = bank[1:0]
        // A[23:11] = row[12:0]
        // A[10: 2] = col[9:1]
        // (a specific combination of the 2+13+9=24 bits adresses
        // a 32-bit word which is transmitted as a burst of two
        // consecutive 16-bit halfwords in one clock cycle)
        input   [25:2] wADR_I;
        input   wSTB_I;
        input   wWE_I;
        input   [3:0] wWRB_I;
        input   [31:0] wDAT_I;
        output  [31:0] wDAT_O;
        output  wACK_O;
 
        // Local data storage
        reg             [5:0] sd_state;
        reg             [3:0] init_state;
        reg             [5:0] wait_count;
        reg             [14:0] init_wait_count;
        reg             [12:0] sd_A_O;
        reg             [1:0] sd_BA_O;
        reg             [12:0] mode_reg;
        reg             sd_RAS_O;
        reg             sd_CAS_O;
        reg             sd_WE_O;
        reg             sd_CS_O;
        reg             sd_CKE_O;
        reg             wACK_O;
 
        reg             [9:0] refresh_counter;
        reg             [3:0] refresh_queue;     // Number of refresh command to queue
        reg             refresh_now;
        reg             refresh_ack;
 
        reg             [31:0] D_rd_reg;
        reg             DQS_state;
        reg             DQS_oe;                 // 1 for output
        reg             D_oe;                   // 1 for output enable
 
        reg             [31:0] D_wr_reg; // Data write buffer
        reg             [3:0] D_mask_reg;        // data mask buffer
 
 
/***************************************************
 * SD ram clock source
 ***************************************************/
 
        ODDR2 #(
                .DDR_ALIGNMENT("NONE"),
                .INIT(1'b0),
                .SRTYPE("SYNC")
        ) ODDR2_inst_CK_P (
                .Q(sd_CK_P),
                .C0(clk180),
                .C1(clk0),
                .CE(1'b1),
                .D0(1'b1),
                .D1(1'b0),
                .R(1'b0),
                .S(1'b0)
        );
 
        ODDR2 #(
                .DDR_ALIGNMENT("NONE"),
                .INIT(1'b0),
                .SRTYPE("SYNC")
        ) ODDR2_inst_CK_N (
                .Q(sd_CK_N),
                .C0(clk0),
                .C1(clk180),
                .CE(1'b1),
                .D0(1'b1),
                .D1(1'b0),
                .R(1'b0),
                .S(1'b0)
        );
 
/***************************************************
 * De-duplex of the data path
 * For some reason, for read, the output is CL=2.5, not CL=2
 * Thus, catching of the data is 1/2 a cycle late.
 * Flip the clk0 and clk180, 1/2 cycle delay catched
 * on data_mux_latch
 ***************************************************/
 
        // Data from SDRAM will be loaded at {data_mux_out[31:0]}
        wire    [31:0] data_mux_out;
        wire    [15:0] iddr_conn;
        wire    [15:0] oddr_conn;
 
 
        generate
        genvar i;
 
                for(i=0;i<16;i=i+1)
                begin : iou
                        IDDR2 #(
                                .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
                                .INIT_Q0(1'b0),                 // Sets initial state of the Q0 output to 1'b0 or 1'b1
                                .INIT_Q1(1'b0),                 // Sets initial state of the Q1 output to 1'b0 or 1'b1
                                .SRTYPE("SYNC")                 // Specifies "SYNC" or "ASYNC" set/reset
                        ) IDDR2_inst (
                                .Q0(data_mux_out[i]),                           // C0 clock
                                .Q1(data_mux_out[i+16]),                        // C1 clock
                                .C0(clk180),
                                .C1(clk0),
                                .CE(1'b1),                              // Always enabled
                                .D(iddr_conn[i]),               // 1-bit DDR data input
                                .R(1'b0),                               // 1-bit reset input
                                .S(1'b0)                                // 1-bit set input
                        );
 
                        ODDR2 #(
                                .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
                                .INIT(1'b0),                    // Sets initial state of the Q output to 1'b0 or 1'b1
                                .SRTYPE("SYNC")                 // Specifies "SYNC" or "ASYNC" set/reset
                        ) ODDR2_inst (
                                .Q(oddr_conn[i]),               // 1-bit DDR output data
                                .C0(clk90),                     // 1-bit clock input
                                .C1(clk270),            // 1-bit clock input
                                .CE(1'b1),                              // 1-bit clock enable input
                                .D0(D_wr_reg[i]),               // (associated with C0)
                                .D1(D_wr_reg[i+16]),    // (associated with C1)
                                .R(1'b0),                               // 1-bit reset input
                                .S(1'b0)                                // 1-bit set input
                        );
 
                        IOBUF #(
                                .DRIVE(4),                              // Specify the output drive strength
                                .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay
                                .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8"
                                .IOSTANDARD("DEFAULT"), // Specify the I/O standard
                                .SLEW("SLOW")                   // Specify the output slew rate
                        ) IOBUF_inst (
                                .O(iddr_conn[i]),               // Buffer output
                                .IO(sd_D_IO[i]),                // Buffer inout port (connect directly to top-level port)
                                .I(oddr_conn[i]),               // Buffer input
                                .T(~D_oe)                               // 3-state enable input
                        );
                end
        endgenerate
 
 
        wire sd_UDQS_O;
        wire sd_LDQS_O;
 
                ODDR2 #(
                        .DDR_ALIGNMENT("NONE"),
                        .INIT(1'b0),
                        .SRTYPE("SYNC")
                ) ODDR2_inst_UDQS (
                        .Q(sd_UDQS_O),
                        .C0(clk180),
                        .C1(clk0),
                        .CE(1'b1),
                        .D0(DQS_state),
                        .D1(1'b0),
                        .R(1'b0),
                        .S(1'b0)
                );
 
                ODDR2 #(
                        .DDR_ALIGNMENT("NONE"),
                        .INIT(1'b0),
                        .SRTYPE("SYNC")
                ) ODDR2_inst_LDQS (
                        .Q(sd_LDQS_O),
                        .C0(clk180),
                        .C1(clk0),
                        .CE(1'b1),
                        .D0(DQS_state),
                        .D1(1'b0),
                        .R(1'b0),
                        .S(1'b0)
                );
 
                IOBUF #(
                        .DRIVE(4),
                        .IBUF_DELAY_VALUE("0"),
                        .IFD_DELAY_VALUE("AUTO"),
                        .IOSTANDARD("DEFAULT"),
                        .SLEW("SLOW")
                ) IOBUF_inst_UDQS (
                        // .O() intentionally not connected
                        .IO(sd_UDQS_IO),
                        .I(sd_UDQS_O),
                        .T(~DQS_oe)
                );
 
                IOBUF #(
                        .DRIVE(4),
                        .IBUF_DELAY_VALUE("0"),
                        .IFD_DELAY_VALUE("AUTO"),
                        .IOSTANDARD("DEFAULT"),
                        .SLEW("SLOW")
                ) IOBUF_inst_LDQS (
                        // .O() intentionally not connected
                        .IO(sd_LDQS_IO),
                        .I(sd_LDQS_O),
                        .T(~DQS_oe)
                );
 
 
        reg [31:0] data_mux_latch;
        always @ (posedge clk180)
        begin
                data_mux_latch <= data_mux_out;
        end
 
/***************************************************
 * Data bus flow direction control
 ***************************************************/
 
        assign wDAT_O = D_rd_reg[31:0];
 
        // Mask output
 
        wire            UDM_conn;
        wire            LDM_conn;
 
        ODDR2 #(
                .DDR_ALIGNMENT("NONE"),
                .INIT(1'b0),
                .SRTYPE("SYNC")
        ) ODDR2_inst_UDM (
                .Q(UDM_conn),
                .C0(clk90),
                .C1(clk270),
                .CE(1'b1),
                .D0(~D_mask_reg[1]),
                .D1(~D_mask_reg[3]),
                .R(1'b0),
                .S(1'b0)
        );
 
        ODDR2 #(
                .DDR_ALIGNMENT("NONE"),
                .INIT(1'b0),
                .SRTYPE("SYNC")
        ) ODDR2_inst_LDM (
                .Q(LDM_conn),
                .C0(clk90),
                .C1(clk270),
                .CE(1'b1),
                .D0(~D_mask_reg[0]),
                .D1(~D_mask_reg[2]),
                .R(1'b0),
                .S(1'b0)
        );
 
        IOBUF #(
                .DRIVE(4),
                .IBUF_DELAY_VALUE("0"),
                .IFD_DELAY_VALUE("AUTO"),
                .IOSTANDARD("DEFAULT"),
                .SLEW("SLOW")
        ) IOBUF_inst_UDM (
                // .O() intentionally not connected
                .IO(sd_UDM_O),
                .I(UDM_conn),
                .T(1'b0)
        );
 
        IOBUF #(
                .DRIVE(4),
                .IBUF_DELAY_VALUE("0"),
                .IFD_DELAY_VALUE("AUTO"),
                .IOSTANDARD("DEFAULT"),
                .SLEW("SLOW")
        ) IOBUF_inst_LDM (
                // .O() intentionally not connected
                .IO(sd_LDM_O),
                .I(LDM_conn),
                .T(1'b0)
        );
 
 
/***************************************************
 * Main tx/rx state machine
 ***************************************************/
 
        /* Timing */
        parameter WAIT_TIME = 5'd5;
        parameter INIT_WAIT = 15'h3000;
        parameter INIT_CLK_EN_WAIT = 15'h10;
        parameter WAIT_CMD_MAX = 6'b100000;
        parameter REFRESH_WAIT = WAIT_CMD_MAX - 6'd7;
        parameter ACCESS_WAIT = WAIT_CMD_MAX - 6'd1;
        parameter CAS_WAIT = WAIT_CMD_MAX - 6'd3;
        parameter AVG_REFRESH_DUR = 10'd700;
 
        /* Main state machine */
        parameter       SD_IDLE = 0,
                                SD_INIT = 1,
                                SD_INIT_WAIT = 2,
                                SD_PRECHG_ALL = 3,
                                SD_PRECHG_ALL1 = 4,
                                SD_AUTO_REF = 5,
                                SD_AUTO_REF1 = 6,
                                SD_AUTO_REF_ACK = 7,
                                SD_LD_MODE = 8,
                                SD_LD_MODE1 = 9,
                                SD_RD_START = 10,
                                SD_RD_COL = 11,
                                SD_RD_CAS_WAIT = 12,
                                SD_RD_LATCH = 13,
                                SD_RD_LATCH1 = 14,
                                SD_RD_DONE = 15,
                                SD_WR_START = 16,
                                SD_WR_COL = 17,
                                SD_WR_CAS_WAIT = 18,
                                SD_WR_LATCH = 19,
                                SD_WR_LATCH1 = 20,
                                SD_WR_DONE = 21,
                                SD_RD_DONE_1 = 22,
                                SD_WR_DONE_1 = 23;
 
        /* Initialization state machine */
        parameter       SI_START = 0,
                                SI_PRECHG = 1,
                                SI_LOAD_EX_MODE = 2,
                                SI_LOAD_MODE = 3,
                                SI_LOAD_MODE2 = 4,
                                SI_PRECHG2 = 5,
                                SI_AUTO_REF = 6,
                                SI_AUTO_REF2 = 7,
                                SI_DONE = 8;
 
 
always @ (posedge clk0)
begin
        if(reset)
        begin
                sd_state <= SD_INIT;
                init_state <= SI_START;
        end else
        begin
                wait_count <= wait_count + 1;
 
                case (sd_state)
                        SD_INIT:                                                // Initialize, wait until INIT_WAIT
                        begin
                                case (init_state)
                                        SI_START:
                                        begin
                                                sd_state <= SD_INIT_WAIT;
                                                init_state <= SI_PRECHG;
                                                sd_RAS_O <= 1;
                                                sd_CAS_O <= 1;
                                                sd_WE_O <= 1;
                                                sd_CS_O <= 1;
                                                sd_CKE_O <= 0;
                                                init_wait_count <= 16'd0;
                                        end
                                        SI_PRECHG:
                                        begin
                                                sd_state <= SD_PRECHG_ALL;
                                                init_state <= SI_LOAD_EX_MODE;
                                        end
                                        SI_LOAD_EX_MODE:
                                        begin
                                                // Normal operation
                                                mode_reg <= 13'b0000000000000;
                                                sd_BA_O <= 2'b01;
                                                sd_state <= SD_LD_MODE;
                                                init_state <= SI_LOAD_MODE;
                                        end
                                        SI_LOAD_MODE:
                                        begin
                                                // CAS = 2, Reset DLL, Burst = 2, sequential
                                                mode_reg <= {6'b000010, 3'b010, 1'b0, 3'b001};
                                                sd_BA_O <= 2'b00;
                                                sd_state <= SD_LD_MODE;
                                                init_state <= SI_LOAD_MODE2;
                                        end
                                        SI_LOAD_MODE2:
                                        begin
                                                // CAS = 2, NO Reset DLL, Burst = 2, sequential
                                                mode_reg <= {6'b000000, 3'b010, 1'b0, 3'b001};
                                                sd_BA_O <= 2'b00;
                                                sd_state <= SD_LD_MODE;
                                                init_state <= SI_PRECHG2;
                                        end
                                        SI_PRECHG2:
                                        begin
                                                sd_state <= SD_PRECHG_ALL;
                                                init_state <= SI_AUTO_REF;
                                        end
                                        SI_AUTO_REF:
                                        begin
                                                sd_state <= SD_AUTO_REF;
                                                init_state <= SI_AUTO_REF2;
                                        end
                                        SI_AUTO_REF2:
                                        begin
                                                sd_state <= SD_AUTO_REF;
                                                init_state <= SI_DONE;
                                        end
                                        SI_DONE:
                                        begin
                                                init_state <= SI_DONE;
                                                sd_state <= SD_IDLE;
                                        end
                                        default:
                                                init_state <= SI_START;
                                endcase
                        end
                        // ** Waiting for SDRAM waking up *****************************
                        SD_INIT_WAIT:
                        begin
                                init_wait_count <= init_wait_count + 1;
                                if(init_wait_count == INIT_WAIT)
                                begin
                                        sd_state <= SD_INIT;
                                end
                                if(init_wait_count == INIT_CLK_EN_WAIT)
                                begin
                                        sd_CKE_O <= 1;                          // Wake up the SDRAM
                                end
                        end
                        // ** Precharge command ***************************************
                        SD_PRECHG_ALL:
                        begin
                                sd_state <= SD_PRECHG_ALL1;
                                sd_RAS_O <= 0;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 0;
                                sd_CS_O <= 0;
                                sd_A_O[10] <= 1;                                // Command for precharge all
                        end
                        SD_PRECHG_ALL1:
                        begin
                                sd_CS_O <= 1;
                                sd_RAS_O <= 1;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;
                                sd_state <= SD_IDLE;                    // Precharge takes 15nS before next command
                        end
                        // ** Load mode register **************************************
                        SD_LD_MODE:
                        begin
                                sd_state <= SD_LD_MODE1;
                                sd_RAS_O <= 0;
                                sd_CAS_O <= 0;
                                sd_WE_O <= 0;
                                sd_CS_O <= 0;
                                sd_A_O[12:0] <= mode_reg;
                        end
                        SD_LD_MODE1:
                        begin
                                sd_CS_O <= 1;
                                sd_RAS_O <= 1;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;                                   // Load Mode takes 12nS
                                sd_state <= SD_IDLE;                    // Add wait if needed
                        end
                        // ** Auto refresh command ************************************
                        SD_AUTO_REF:
                        begin
                                sd_state <= SD_AUTO_REF1;
                                sd_RAS_O <= 0;
                                sd_CAS_O <= 0;
                                sd_WE_O <= 1;
                                sd_CS_O <= 0;
                                wait_count <= REFRESH_WAIT;
                        end
                        SD_AUTO_REF1:
                        begin
                                sd_CS_O <= 1;                                   // Issue NOP during wait
                                sd_RAS_O <= 1;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;
                                if(wait_count[5] == 1)                  // Time up, return to idle
                                begin
                                        sd_state <= SD_AUTO_REF_ACK;
                                        refresh_ack <= 1;
                                end
                        end
                        SD_AUTO_REF_ACK:                                        // Interlocking state
                        begin
                                sd_state <= SD_IDLE;
                                refresh_ack <= 0;
                        end
                        // ** Read cycle **********************************************
                        SD_RD_START:
                        begin
                                sd_state <= SD_RD_COL;
                                sd_RAS_O <= 0;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;
                                sd_CS_O <= 0;
                                sd_BA_O[1:0] <= wADR_I[25:24];
                                sd_A_O[12:0] <= wADR_I[23:11];
                                wait_count <= ACCESS_WAIT;
                                D_oe <= 0;                                               // Not driving the bus
                                DQS_state <= 0;
                        end
                        SD_RD_COL:
                        begin
                                if(wait_count[5] != 1)
                                begin
                                        sd_CS_O <= 1;                   // NOP command during access wait               
                                        sd_RAS_O <= 1;
                                        sd_CAS_O <= 1;
                                        sd_WE_O <= 1;
                                end else
                                begin
                                        sd_CS_O <= 0;                            // Access column 
                                        sd_RAS_O <= 1;
                                        sd_CAS_O <= 0;
                                        sd_WE_O <= 1;
                                        sd_state <= SD_RD_CAS_WAIT;
                                        sd_A_O[9:1] <= wADR_I[10:2];
                                        sd_A_O[10] <= 1;                        // Use auto-precharge
                                        sd_A_O[0] <= 0;
                                        wait_count <= CAS_WAIT;
                                        DQS_oe <= 0;                     // Set DQS for input
                                end
                        end
                        SD_RD_CAS_WAIT:
                        begin                                                           // Wait until DQS signal there is data
                                if(wait_count[5] != 1)
                                begin
                                        sd_CS_O <= 1;                           // NOP command during access wait               
                                        sd_RAS_O <= 1;
                                        sd_CAS_O <= 1;
                                        sd_WE_O <= 1;
                                end else
                                begin
                                        sd_state <= SD_RD_LATCH;
                                end
                        end
                        SD_RD_LATCH:
                        begin
                                D_rd_reg <= data_mux_latch[31:0];
                                wACK_O <= 1;
                                sd_state <= SD_RD_DONE;
                        end
                        SD_RD_DONE:
                        begin
                                wACK_O <= 1;
                                sd_state <= SD_RD_DONE_1;
                                DQS_state <= 0;
                                DQS_oe <= 1;    // Set DQS back to output
                        end
                        SD_RD_DONE_1:
                        begin
                                wACK_O <= 0;
                                sd_state <= SD_IDLE;
                        end
                        // ** Write cycle *********************************************
                        SD_WR_START:
                        begin                                                   // Open the bank - ACTIVE command
                                sd_state <= SD_WR_COL;
                                sd_RAS_O <= 0;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;
                                sd_CS_O <= 0;
                                sd_BA_O[1:0] <= wADR_I[25:24];
                                sd_A_O[12:0] <= wADR_I[23:11];
                                D_wr_reg <= wDAT_I;
                                D_mask_reg <= wWRB_I;
                                wait_count <= ACCESS_WAIT;
                                DQS_state <= 0;
                        end
                        SD_WR_COL:
                        begin
                                if(wait_count[5] != 1)
                                begin
                                        sd_CS_O <= 1;                   // NOP command during access wait               
                                        sd_RAS_O <= 1;
                                        sd_CAS_O <= 1;
                                        sd_WE_O <= 1;
                                end else
                                begin
                                        sd_CS_O <= 0;                    // Access column 
                                        sd_RAS_O <= 1;
                                        sd_CAS_O <= 0;
                                        sd_WE_O <= 0;
                                        DQS_oe <= 1;
                                        sd_state <= SD_WR_CAS_WAIT;
                                        sd_A_O[9:1] <= wADR_I[10:2];
                                        sd_A_O[10] <= 1;                // Use auto-precharge
                                        sd_A_O[0] <= 0;
                                end
                        end
                        SD_WR_CAS_WAIT:
                        begin                                                   // Wait until DQS signal there is data
                                sd_state <= SD_WR_LATCH;
                                DQS_state <= 1;                 // Start with DQS low
                                D_oe <= 1;                              // Drive the data bus
                                sd_CS_O <= 1;
                                sd_RAS_O <= 1;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;
                        end
                        SD_WR_LATCH:
                        begin
                                sd_state <= SD_WR_LATCH1;
                                DQS_state <= 0;
                        end
                        SD_WR_LATCH1:
                        begin
                                sd_state <= SD_WR_DONE;
                                DQS_state <= 0;
                                wACK_O <= 1;
                        end
                        SD_WR_DONE:
                        begin
                                D_oe <= 0;
                                wACK_O <= 1;
                                sd_state <= SD_WR_DONE_1;
                        end
                        SD_WR_DONE_1:
                        begin
                                wACK_O <= 0;
                                sd_state <= SD_IDLE;
                        end
                    // Wishbone transfer is done during idle time
                        SD_IDLE:                                                /* Idle/sleep process */
                        begin
                                sd_RAS_O <= 1;                          // Set for NOP by default
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;
                                sd_CS_O <= 1;
                                if(init_state != SI_DONE)       // If still in init cycle, go back and work
                                        sd_state <= SD_INIT;
                                else if(wSTB_I && !wWE_I)                               // Start of a read command
                                        sd_state <= SD_RD_START;
                                else if(wSTB_I && wWE_I)        // Start of a write command
                                        sd_state <= SD_WR_START;
                                else if(refresh_now)                                    // Refresh is the last command
                                        sd_state <= SD_AUTO_REF;
                        end
 
                        default:
                                sd_state <= SD_IDLE;
                endcase
        end
end
 
/* Seperate always block for refresh timer */
/* The idea is to queue as many as 8 refresh command as possible if the bus is
 * free */
always @ (posedge clk0)
begin
        if(refresh_ack)
        begin
                refresh_now <= 0;
                refresh_queue <= refresh_queue + 4'd1;
        end else
        if(reset)
        begin
                refresh_counter <= 0;
                refresh_queue <= 4'd0;
        end else
        begin
                refresh_counter <= refresh_counter + 1;
                if(refresh_counter == AVG_REFRESH_DUR)
                begin
                        refresh_counter <= 0;
                        if(refresh_queue != 4'd0)
                                refresh_queue <= refresh_queue - 4'd1;
                end
                if(refresh_queue != 4'd7)
                        refresh_now <= 1;
        end
end
 
endmodule

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[/] [eco32/] [tags/] [eco32-0.25/] [fpga/] [src/] [ram/] [ddr/] [ddr_sdram.v] - Blame information for rev 219

Line No.	Rev	Author	Line
1	219	hellwig	`////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Create Date: 02/11/07`
4			`// Last Change: 01/22/12`
5			`// Design Name: DDR SDRAM memory controller`
6			`// Module Name: ddr_sdram`
7			`// Description: memory controller for DDR SDRAM`
8			`// hard coded for 8 Meg x 16 x 4 banks`
9			`//`
10			`// Revision:`
11			`// Revision 0.01 - File Created`
12			`//`
13			`// Development platform: Spartan-3E Starter kit`
14			`//`
15			`// Copyright (C) 2007, Rick Huang`
16			`//`
17			`// Modifications by Hellwig Geisse, 2012`
18			`// - sd_CK_P and sd_CK_N supplied by this module`
19			`// - DDR output registers for sd_CK_P and sd_CK_N added`
20			`// - sd_CLK_O deleted`
21			`// - debug output deleted`
22			`// - burst mode sections of the state machine deleted`
23			`// (have been commented out already)`
24			`// - additional states SD_RD_DONE_1 and SD_WR_DONE_1 inserted`
25			`// (in order to stretch the wACK_O signal, which is to be`
26			`// recognized by external circuits clocked with 50 MHz)`
27			`// - four "write byte" signals added to interface`
28			`// (to allow 8 and 16 bit write operations too)`
29			`// - mask registers UDM_reg_O and LDM_reg_O deleted`
30			`// - DDR output registers for sd_UDM_O and sd_LDM_O added`
31			`// - data_sample_en and its associated multiplexer removed`
32			`// (apparently a debugging vehicle)`
33			`//`
34			`// This library is free software; you can redistribute it and/or`
35			`// modify it under the terms of the GNU Lesser General Public`
36			`// License as published by the Free Software Foundation; either`
37			`// version 2.1 of the License, or (at your option) any later version.`
38			`//`
39			`// This library is distributed in the hope that it will be useful,`
40			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
41			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
42			`// Lesser General Public License for more details.`
43			`//`
44			`// You should have received a copy of the GNU Lesser General Public`
45			`// License along with this library; if not, write to the Free Software`
46			`// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,`
47			`// MA 02110-1301 USA`
48			`//`
49			`////////////////////////////////////////////////////////////////////////////`
50
51			`module ddr_sdram(sd_CK_P, sd_CK_N,`
52			`sd_A_O, sd_BA_O, sd_D_IO,`
53			`sd_RAS_O, sd_CAS_O, sd_WE_O,`
54			`sd_UDM_O, sd_LDM_O,`
55			`sd_UDQS_IO, sd_LDQS_IO,`
56			`sd_CS_O, sd_CKE_O,`
57			`clk0, clk90,`
58			`clk180, clk270,`
59			`reset,`
60			`wADR_I, wSTB_I, wWE_I, wWRB_I,`
61			`wDAT_I, wDAT_O, wACK_O);`
62			`// interface to DDR SDRAM memory`
63			`output sd_CK_P;`
64			`output sd_CK_N;`
65			`output [12:0] sd_A_O;`
66			`output [1:0] sd_BA_O;`
67			`inout [15:0] sd_D_IO;`
68			`output sd_RAS_O;`
69			`output sd_CAS_O;`
70			`output sd_WE_O;`
71			`output sd_UDM_O;`
72			`output sd_LDM_O;`
73			`inout sd_UDQS_IO;`
74			`inout sd_LDQS_IO;`
75			`output sd_CS_O;`
76			`output sd_CKE_O;`
77			`// internal interface signals`
78			`input clk0;`
79			`input clk90;`
80			`input clk180;`
81			`input clk270;`
82			`input reset;`
83			`// A[25:24] = bank[1:0]`
84			`// A[23:11] = row[12:0]`
85			`// A[10: 2] = col[9:1]`
86			`// (a specific combination of the 2+13+9=24 bits adresses`
87			`// a 32-bit word which is transmitted as a burst of two`
88			`// consecutive 16-bit halfwords in one clock cycle)`
89			`input [25:2] wADR_I;`
90			`input wSTB_I;`
91			`input wWE_I;`
92			`input [3:0] wWRB_I;`
93			`input [31:0] wDAT_I;`
94			`output [31:0] wDAT_O;`
95			`output wACK_O;`
96
97			`// Local data storage`
98			`reg [5:0] sd_state;`
99			`reg [3:0] init_state;`
100			`reg [5:0] wait_count;`
101			`reg [14:0] init_wait_count;`
102			`reg [12:0] sd_A_O;`
103			`reg [1:0] sd_BA_O;`
104			`reg [12:0] mode_reg;`
105			`reg sd_RAS_O;`
106			`reg sd_CAS_O;`
107			`reg sd_WE_O;`
108			`reg sd_CS_O;`
109			`reg sd_CKE_O;`
110			`reg wACK_O;`
111
112			`reg [9:0] refresh_counter;`
113			`reg [3:0] refresh_queue; // Number of refresh command to queue`
114			`reg refresh_now;`
115			`reg refresh_ack;`
116
117			`reg [31:0] D_rd_reg;`
118			`reg DQS_state;`
119			`reg DQS_oe; // 1 for output`
120			`reg D_oe; // 1 for output enable`
121
122			`reg [31:0] D_wr_reg; // Data write buffer`
123			`reg [3:0] D_mask_reg; // data mask buffer`
124
125
126			`/***************************************************`
127			`* SD ram clock source`
128			`***************************************************/`
129
130			`ODDR2 #(`
131			`.DDR_ALIGNMENT("NONE"),`
132			`.INIT(1'b0),`
133			`.SRTYPE("SYNC")`
134			`) ODDR2_inst_CK_P (`
135			`.Q(sd_CK_P),`
136			`.C0(clk180),`
137			`.C1(clk0),`
138			`.CE(1'b1),`
139			`.D0(1'b1),`
140			`.D1(1'b0),`
141			`.R(1'b0),`
142			`.S(1'b0)`
143			`);`
144
145			`ODDR2 #(`
146			`.DDR_ALIGNMENT("NONE"),`
147			`.INIT(1'b0),`
148			`.SRTYPE("SYNC")`
149			`) ODDR2_inst_CK_N (`
150			`.Q(sd_CK_N),`
151			`.C0(clk0),`
152			`.C1(clk180),`
153			`.CE(1'b1),`
154			`.D0(1'b1),`
155			`.D1(1'b0),`
156			`.R(1'b0),`
157			`.S(1'b0)`
158			`);`
159
160			`/***************************************************`
161			`* De-duplex of the data path`
162			`* For some reason, for read, the output is CL=2.5, not CL=2`
163			`* Thus, catching of the data is 1/2 a cycle late.`
164			`* Flip the clk0 and clk180, 1/2 cycle delay catched`
165			`* on data_mux_latch`
166			`***************************************************/`
167
168			`// Data from SDRAM will be loaded at {data_mux_out[31:0]}`
169			`wire [31:0] data_mux_out;`
170			`wire [15:0] iddr_conn;`
171			`wire [15:0] oddr_conn;`
172
173
174			`generate`
175			`genvar i;`
176
177			`for(i=0;i<16;i=i+1)`
178			`begin : iou`
179			`IDDR2 #(`
180			`.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"`
181			`.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1`
182			`.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1`
183			`.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset`
184			`) IDDR2_inst (`
185			`.Q0(data_mux_out[i]), // C0 clock`
186			`.Q1(data_mux_out[i+16]), // C1 clock`
187			`.C0(clk180),`
188			`.C1(clk0),`
189			`.CE(1'b1), // Always enabled`
190			`.D(iddr_conn[i]), // 1-bit DDR data input`
191			`.R(1'b0), // 1-bit reset input`
192			`.S(1'b0) // 1-bit set input`
193			`);`
194
195			`ODDR2 #(`
196			`.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"`
197			`.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1`
198			`.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset`
199			`) ODDR2_inst (`
200			`.Q(oddr_conn[i]), // 1-bit DDR output data`
201			`.C0(clk90), // 1-bit clock input`
202			`.C1(clk270), // 1-bit clock input`
203			`.CE(1'b1), // 1-bit clock enable input`
204			`.D0(D_wr_reg[i]), // (associated with C0)`
205			`.D1(D_wr_reg[i+16]), // (associated with C1)`
206			`.R(1'b0), // 1-bit reset input`
207			`.S(1'b0) // 1-bit set input`
208			`);`
209
210			`IOBUF #(`
211			`.DRIVE(4), // Specify the output drive strength`
212			`.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay`
213			`.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8"`
214			`.IOSTANDARD("DEFAULT"), // Specify the I/O standard`
215			`.SLEW("SLOW") // Specify the output slew rate`
216			`) IOBUF_inst (`
217			`.O(iddr_conn[i]), // Buffer output`
218			`.IO(sd_D_IO[i]), // Buffer inout port (connect directly to top-level port)`
219			`.I(oddr_conn[i]), // Buffer input`
220			`.T(~D_oe) // 3-state enable input`
221			`);`
222			`end`
223			`endgenerate`
224
225
226			`wire sd_UDQS_O;`
227			`wire sd_LDQS_O;`
228
229			`ODDR2 #(`
230			`.DDR_ALIGNMENT("NONE"),`
231			`.INIT(1'b0),`
232			`.SRTYPE("SYNC")`
233			`) ODDR2_inst_UDQS (`
234			`.Q(sd_UDQS_O),`
235			`.C0(clk180),`
236			`.C1(clk0),`
237			`.CE(1'b1),`
238			`.D0(DQS_state),`
239			`.D1(1'b0),`
240			`.R(1'b0),`
241			`.S(1'b0)`
242			`);`
243
244			`ODDR2 #(`
245			`.DDR_ALIGNMENT("NONE"),`
246			`.INIT(1'b0),`
247			`.SRTYPE("SYNC")`
248			`) ODDR2_inst_LDQS (`
249			`.Q(sd_LDQS_O),`
250			`.C0(clk180),`
251			`.C1(clk0),`
252			`.CE(1'b1),`
253			`.D0(DQS_state),`
254			`.D1(1'b0),`
255			`.R(1'b0),`
256			`.S(1'b0)`
257			`);`
258
259			`IOBUF #(`
260			`.DRIVE(4),`
261			`.IBUF_DELAY_VALUE("0"),`
262			`.IFD_DELAY_VALUE("AUTO"),`
263			`.IOSTANDARD("DEFAULT"),`
264			`.SLEW("SLOW")`
265			`) IOBUF_inst_UDQS (`
266			`// .O() intentionally not connected`
267			`.IO(sd_UDQS_IO),`
268			`.I(sd_UDQS_O),`
269			`.T(~DQS_oe)`
270			`);`
271
272			`IOBUF #(`
273			`.DRIVE(4),`
274			`.IBUF_DELAY_VALUE("0"),`
275			`.IFD_DELAY_VALUE("AUTO"),`
276			`.IOSTANDARD("DEFAULT"),`
277			`.SLEW("SLOW")`
278			`) IOBUF_inst_LDQS (`
279			`// .O() intentionally not connected`
280			`.IO(sd_LDQS_IO),`
281			`.I(sd_LDQS_O),`
282			`.T(~DQS_oe)`
283			`);`
284
285
286			`reg [31:0] data_mux_latch;`
287			`always @ (posedge clk180)`
288			`begin`
289			`data_mux_latch <= data_mux_out;`
290			`end`
291
292			`/***************************************************`
293			`* Data bus flow direction control`
294			`***************************************************/`
295
296			`assign wDAT_O = D_rd_reg[31:0];`
297
298			`// Mask output`
299
300			`wire UDM_conn;`
301			`wire LDM_conn;`
302
303			`ODDR2 #(`
304			`.DDR_ALIGNMENT("NONE"),`
305			`.INIT(1'b0),`
306			`.SRTYPE("SYNC")`
307			`) ODDR2_inst_UDM (`
308			`.Q(UDM_conn),`
309			`.C0(clk90),`
310			`.C1(clk270),`
311			`.CE(1'b1),`
312			`.D0(~D_mask_reg[1]),`
313			`.D1(~D_mask_reg[3]),`
314			`.R(1'b0),`
315			`.S(1'b0)`
316			`);`
317
318			`ODDR2 #(`
319			`.DDR_ALIGNMENT("NONE"),`
320			`.INIT(1'b0),`
321			`.SRTYPE("SYNC")`
322			`) ODDR2_inst_LDM (`
323			`.Q(LDM_conn),`
324			`.C0(clk90),`
325			`.C1(clk270),`
326			`.CE(1'b1),`
327			`.D0(~D_mask_reg[0]),`
328			`.D1(~D_mask_reg[2]),`
329			`.R(1'b0),`
330			`.S(1'b0)`
331			`);`
332
333			`IOBUF #(`
334			`.DRIVE(4),`
335			`.IBUF_DELAY_VALUE("0"),`
336			`.IFD_DELAY_VALUE("AUTO"),`
337			`.IOSTANDARD("DEFAULT"),`
338			`.SLEW("SLOW")`
339			`) IOBUF_inst_UDM (`
340			`// .O() intentionally not connected`
341			`.IO(sd_UDM_O),`
342			`.I(UDM_conn),`
343			`.T(1'b0)`
344			`);`
345
346			`IOBUF #(`
347			`.DRIVE(4),`
348			`.IBUF_DELAY_VALUE("0"),`
349			`.IFD_DELAY_VALUE("AUTO"),`
350			`.IOSTANDARD("DEFAULT"),`
351			`.SLEW("SLOW")`
352			`) IOBUF_inst_LDM (`
353			`// .O() intentionally not connected`
354			`.IO(sd_LDM_O),`
355			`.I(LDM_conn),`
356			`.T(1'b0)`
357			`);`
358
359
360			`/***************************************************`
361			`* Main tx/rx state machine`
362			`***************************************************/`
363
364			`/* Timing */`
365			`parameter WAIT_TIME = 5'd5;`
366			`parameter INIT_WAIT = 15'h3000;`
367			`parameter INIT_CLK_EN_WAIT = 15'h10;`
368			`parameter WAIT_CMD_MAX = 6'b100000;`
369			`parameter REFRESH_WAIT = WAIT_CMD_MAX - 6'd7;`
370			`parameter ACCESS_WAIT = WAIT_CMD_MAX - 6'd1;`
371			`parameter CAS_WAIT = WAIT_CMD_MAX - 6'd3;`
372			`parameter AVG_REFRESH_DUR = 10'd700;`
373
374			`/* Main state machine */`
375			`parameter SD_IDLE = 0,`
376			`SD_INIT = 1,`
377			`SD_INIT_WAIT = 2,`
378			`SD_PRECHG_ALL = 3,`
379			`SD_PRECHG_ALL1 = 4,`
380			`SD_AUTO_REF = 5,`
381			`SD_AUTO_REF1 = 6,`
382			`SD_AUTO_REF_ACK = 7,`
383			`SD_LD_MODE = 8,`
384			`SD_LD_MODE1 = 9,`
385			`SD_RD_START = 10,`
386			`SD_RD_COL = 11,`
387			`SD_RD_CAS_WAIT = 12,`
388			`SD_RD_LATCH = 13,`
389			`SD_RD_LATCH1 = 14,`
390			`SD_RD_DONE = 15,`
391			`SD_WR_START = 16,`
392			`SD_WR_COL = 17,`
393			`SD_WR_CAS_WAIT = 18,`
394			`SD_WR_LATCH = 19,`
395			`SD_WR_LATCH1 = 20,`
396			`SD_WR_DONE = 21,`
397			`SD_RD_DONE_1 = 22,`
398			`SD_WR_DONE_1 = 23;`
399
400			`/* Initialization state machine */`
401			`parameter SI_START = 0,`
402			`SI_PRECHG = 1,`
403			`SI_LOAD_EX_MODE = 2,`
404			`SI_LOAD_MODE = 3,`
405			`SI_LOAD_MODE2 = 4,`
406			`SI_PRECHG2 = 5,`
407			`SI_AUTO_REF = 6,`
408			`SI_AUTO_REF2 = 7,`
409			`SI_DONE = 8;`
410
411
412			`always @ (posedge clk0)`
413			`begin`
414			`if(reset)`
415			`begin`
416			`sd_state <= SD_INIT;`
417			`init_state <= SI_START;`
418			`end else`
419			`begin`
420			`wait_count <= wait_count + 1;`
421
422			`case (sd_state)`
423			`SD_INIT: // Initialize, wait until INIT_WAIT`
424			`begin`
425			`case (init_state)`
426			`SI_START:`
427			`begin`
428			`sd_state <= SD_INIT_WAIT;`
429			`init_state <= SI_PRECHG;`
430			`sd_RAS_O <= 1;`
431			`sd_CAS_O <= 1;`
432			`sd_WE_O <= 1;`
433			`sd_CS_O <= 1;`
434			`sd_CKE_O <= 0;`
435			`init_wait_count <= 16'd0;`
436			`end`
437			`SI_PRECHG:`
438			`begin`
439			`sd_state <= SD_PRECHG_ALL;`
440			`init_state <= SI_LOAD_EX_MODE;`
441			`end`
442			`SI_LOAD_EX_MODE:`
443			`begin`
444			`// Normal operation`
445			`mode_reg <= 13'b0000000000000;`
446			`sd_BA_O <= 2'b01;`
447			`sd_state <= SD_LD_MODE;`
448			`init_state <= SI_LOAD_MODE;`
449			`end`
450			`SI_LOAD_MODE:`
451			`begin`
452			`// CAS = 2, Reset DLL, Burst = 2, sequential`
453			`mode_reg <= {6'b000010, 3'b010, 1'b0, 3'b001};`
454			`sd_BA_O <= 2'b00;`
455			`sd_state <= SD_LD_MODE;`
456			`init_state <= SI_LOAD_MODE2;`
457			`end`
458			`SI_LOAD_MODE2:`
459			`begin`
460			`// CAS = 2, NO Reset DLL, Burst = 2, sequential`
461			`mode_reg <= {6'b000000, 3'b010, 1'b0, 3'b001};`
462			`sd_BA_O <= 2'b00;`
463			`sd_state <= SD_LD_MODE;`
464			`init_state <= SI_PRECHG2;`
465			`end`
466			`SI_PRECHG2:`
467			`begin`
468			`sd_state <= SD_PRECHG_ALL;`
469			`init_state <= SI_AUTO_REF;`
470			`end`
471			`SI_AUTO_REF:`
472			`begin`
473			`sd_state <= SD_AUTO_REF;`
474			`init_state <= SI_AUTO_REF2;`
475			`end`
476			`SI_AUTO_REF2:`
477			`begin`
478			`sd_state <= SD_AUTO_REF;`
479			`init_state <= SI_DONE;`
480			`end`
481			`SI_DONE:`
482			`begin`
483			`init_state <= SI_DONE;`
484			`sd_state <= SD_IDLE;`
485			`end`
486			`default:`
487			`init_state <= SI_START;`
488			`endcase`
489			`end`
490			`// Waiting for SDRAM waking up ***************************`
491			`SD_INIT_WAIT:`
492			`begin`
493			`init_wait_count <= init_wait_count + 1;`
494			`if(init_wait_count == INIT_WAIT)`
495			`begin`
496			`sd_state <= SD_INIT;`
497			`end`
498			`if(init_wait_count == INIT_CLK_EN_WAIT)`
499			`begin`
500			`sd_CKE_O <= 1; // Wake up the SDRAM`
501			`end`
502			`end`
503			`// Precharge command *************************************`
504			`SD_PRECHG_ALL:`
505			`begin`
506			`sd_state <= SD_PRECHG_ALL1;`
507			`sd_RAS_O <= 0;`
508			`sd_CAS_O <= 1;`
509			`sd_WE_O <= 0;`
510			`sd_CS_O <= 0;`
511			`sd_A_O[10] <= 1; // Command for precharge all`
512			`end`
513			`SD_PRECHG_ALL1:`
514			`begin`
515			`sd_CS_O <= 1;`
516			`sd_RAS_O <= 1;`
517			`sd_CAS_O <= 1;`
518			`sd_WE_O <= 1;`
519			`sd_state <= SD_IDLE; // Precharge takes 15nS before next command`
520			`end`
521			`// Load mode register ************************************`
522			`SD_LD_MODE:`
523			`begin`
524			`sd_state <= SD_LD_MODE1;`
525			`sd_RAS_O <= 0;`
526			`sd_CAS_O <= 0;`
527			`sd_WE_O <= 0;`
528			`sd_CS_O <= 0;`
529			`sd_A_O[12:0] <= mode_reg;`
530			`end`
531			`SD_LD_MODE1:`
532			`begin`
533			`sd_CS_O <= 1;`
534			`sd_RAS_O <= 1;`
535			`sd_CAS_O <= 1;`
536			`sd_WE_O <= 1; // Load Mode takes 12nS`
537			`sd_state <= SD_IDLE; // Add wait if needed`
538			`end`
539			`// Auto refresh command **********************************`
540			`SD_AUTO_REF:`
541			`begin`
542			`sd_state <= SD_AUTO_REF1;`
543			`sd_RAS_O <= 0;`
544			`sd_CAS_O <= 0;`
545			`sd_WE_O <= 1;`
546			`sd_CS_O <= 0;`
547			`wait_count <= REFRESH_WAIT;`
548			`end`
549			`SD_AUTO_REF1:`
550			`begin`
551			`sd_CS_O <= 1; // Issue NOP during wait`
552			`sd_RAS_O <= 1;`
553			`sd_CAS_O <= 1;`
554			`sd_WE_O <= 1;`
555			`if(wait_count[5] == 1) // Time up, return to idle`
556			`begin`
557			`sd_state <= SD_AUTO_REF_ACK;`
558			`refresh_ack <= 1;`
559			`end`
560			`end`
561			`SD_AUTO_REF_ACK: // Interlocking state`
562			`begin`
563			`sd_state <= SD_IDLE;`
564			`refresh_ack <= 0;`
565			`end`
566			`// Read cycle ********************************************`
567			`SD_RD_START:`
568			`begin`
569			`sd_state <= SD_RD_COL;`
570			`sd_RAS_O <= 0;`
571			`sd_CAS_O <= 1;`
572			`sd_WE_O <= 1;`
573			`sd_CS_O <= 0;`
574			`sd_BA_O[1:0] <= wADR_I[25:24];`
575			`sd_A_O[12:0] <= wADR_I[23:11];`
576			`wait_count <= ACCESS_WAIT;`
577			`D_oe <= 0; // Not driving the bus`
578			`DQS_state <= 0;`
579			`end`
580			`SD_RD_COL:`
581			`begin`
582			`if(wait_count[5] != 1)`
583			`begin`
584			`sd_CS_O <= 1; // NOP command during access wait`
585			`sd_RAS_O <= 1;`
586			`sd_CAS_O <= 1;`
587			`sd_WE_O <= 1;`
588			`end else`
589			`begin`
590			`sd_CS_O <= 0; // Access column`
591			`sd_RAS_O <= 1;`
592			`sd_CAS_O <= 0;`
593			`sd_WE_O <= 1;`
594			`sd_state <= SD_RD_CAS_WAIT;`
595			`sd_A_O[9:1] <= wADR_I[10:2];`
596			`sd_A_O[10] <= 1; // Use auto-precharge`
597			`sd_A_O[0] <= 0;`
598			`wait_count <= CAS_WAIT;`
599			`DQS_oe <= 0; // Set DQS for input`
600			`end`
601			`end`
602			`SD_RD_CAS_WAIT:`
603			`begin // Wait until DQS signal there is data`
604			`if(wait_count[5] != 1)`
605			`begin`
606			`sd_CS_O <= 1; // NOP command during access wait`
607			`sd_RAS_O <= 1;`
608			`sd_CAS_O <= 1;`
609			`sd_WE_O <= 1;`
610			`end else`
611			`begin`
612			`sd_state <= SD_RD_LATCH;`
613			`end`
614			`end`
615			`SD_RD_LATCH:`
616			`begin`
617			`D_rd_reg <= data_mux_latch[31:0];`
618			`wACK_O <= 1;`
619			`sd_state <= SD_RD_DONE;`
620			`end`
621			`SD_RD_DONE:`
622			`begin`
623			`wACK_O <= 1;`
624			`sd_state <= SD_RD_DONE_1;`
625			`DQS_state <= 0;`
626			`DQS_oe <= 1; // Set DQS back to output`
627			`end`
628			`SD_RD_DONE_1:`
629			`begin`
630			`wACK_O <= 0;`
631			`sd_state <= SD_IDLE;`
632			`end`
633			`// Write cycle *******************************************`
634			`SD_WR_START:`
635			`begin // Open the bank - ACTIVE command`
636			`sd_state <= SD_WR_COL;`
637			`sd_RAS_O <= 0;`
638			`sd_CAS_O <= 1;`
639			`sd_WE_O <= 1;`
640			`sd_CS_O <= 0;`
641			`sd_BA_O[1:0] <= wADR_I[25:24];`
642			`sd_A_O[12:0] <= wADR_I[23:11];`
643			`D_wr_reg <= wDAT_I;`
644			`D_mask_reg <= wWRB_I;`
645			`wait_count <= ACCESS_WAIT;`
646			`DQS_state <= 0;`
647			`end`
648			`SD_WR_COL:`
649			`begin`
650			`if(wait_count[5] != 1)`
651			`begin`
652			`sd_CS_O <= 1; // NOP command during access wait`
653			`sd_RAS_O <= 1;`
654			`sd_CAS_O <= 1;`
655			`sd_WE_O <= 1;`
656			`end else`
657			`begin`
658			`sd_CS_O <= 0; // Access column`
659			`sd_RAS_O <= 1;`
660			`sd_CAS_O <= 0;`
661			`sd_WE_O <= 0;`
662			`DQS_oe <= 1;`
663			`sd_state <= SD_WR_CAS_WAIT;`
664			`sd_A_O[9:1] <= wADR_I[10:2];`
665			`sd_A_O[10] <= 1; // Use auto-precharge`
666			`sd_A_O[0] <= 0;`
667			`end`
668			`end`
669			`SD_WR_CAS_WAIT:`
670			`begin // Wait until DQS signal there is data`
671			`sd_state <= SD_WR_LATCH;`
672			`DQS_state <= 1; // Start with DQS low`
673			`D_oe <= 1; // Drive the data bus`
674			`sd_CS_O <= 1;`
675			`sd_RAS_O <= 1;`
676			`sd_CAS_O <= 1;`
677			`sd_WE_O <= 1;`
678			`end`
679			`SD_WR_LATCH:`
680			`begin`
681			`sd_state <= SD_WR_LATCH1;`
682			`DQS_state <= 0;`
683			`end`
684			`SD_WR_LATCH1:`
685			`begin`
686			`sd_state <= SD_WR_DONE;`
687			`DQS_state <= 0;`
688			`wACK_O <= 1;`
689			`end`
690			`SD_WR_DONE:`
691			`begin`
692			`D_oe <= 0;`
693			`wACK_O <= 1;`
694			`sd_state <= SD_WR_DONE_1;`
695			`end`
696			`SD_WR_DONE_1:`
697			`begin`
698			`wACK_O <= 0;`
699			`sd_state <= SD_IDLE;`
700			`end`
701			`// Wishbone transfer is done during idle time`
702			`SD_IDLE: /* Idle/sleep process */`
703			`begin`
704			`sd_RAS_O <= 1; // Set for NOP by default`
705			`sd_CAS_O <= 1;`
706			`sd_WE_O <= 1;`
707			`sd_CS_O <= 1;`
708			`if(init_state != SI_DONE) // If still in init cycle, go back and work`
709			`sd_state <= SD_INIT;`
710			`else if(wSTB_I && !wWE_I) // Start of a read command`
711			`sd_state <= SD_RD_START;`
712			`else if(wSTB_I && wWE_I) // Start of a write command`
713			`sd_state <= SD_WR_START;`
714			`else if(refresh_now) // Refresh is the last command`
715			`sd_state <= SD_AUTO_REF;`
716			`end`
717
718			`default:`
719			`sd_state <= SD_IDLE;`
720			`endcase`
721			`end`
722			`end`
723
724			`/* Seperate always block for refresh timer */`
725			`/* The idea is to queue as many as 8 refresh command as possible if the bus is`
726			`* free */`
727			`always @ (posedge clk0)`
728			`begin`
729			`if(refresh_ack)`
730			`begin`
731			`refresh_now <= 0;`
732			`refresh_queue <= refresh_queue + 4'd1;`
733			`end else`
734			`if(reset)`
735			`begin`
736			`refresh_counter <= 0;`
737			`refresh_queue <= 4'd0;`
738			`end else`
739			`begin`
740			`refresh_counter <= refresh_counter + 1;`
741			`if(refresh_counter == AVG_REFRESH_DUR)`
742			`begin`
743			`refresh_counter <= 0;`
744			`if(refresh_queue != 4'd0)`
745			`refresh_queue <= refresh_queue - 4'd1;`
746			`end`
747			`if(refresh_queue != 4'd7)`
748			`refresh_now <= 1;`
749			`end`
750			`end`
751
752			`endmodule`