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[/] [eco32/] [tags/] [eco32-0.26/] [fpga/] [src/] [fms/] [fms.v] - Blame information for rev 218

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1 218 hellwig
//
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// fms.v -- FM synthesizer
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//
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// NOTE: this is a fake module for now
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//
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module fms(clk, reset,
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           en, wr, addr,
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           data_in, data_out,
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           wt,
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           next, sample_l, sample_r);
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    // internal interface
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    input clk;
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    input reset;
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    input en;
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    input wr;
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    input [11:2] addr;
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    input [31:0] data_in;
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    output [31:0] data_out;
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    output wt;
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    // DAC controller interface
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    input next;
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    output [15:0] sample_l;
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    output [15:0] sample_r;
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  reg [31:0] value;
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  always @(posedge clk) begin
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    if (reset) begin
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      value[31:0] <= 32'h0;
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    end else begin
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      if (en & wr & ~|addr[11:2]) begin
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        value[31:0] <= data_in[31:0];
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      end
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    end
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  end
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  assign data_out[31:0] = value[31:0];
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  assign wt = 0;
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  assign sample_l[15:0] = value[31:16];
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  assign sample_r[15:0] = value[15:0];
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endmodule

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