Subversion Repositories eco32

Instruction Formats

-------------------

RRR (three register operands)

RRS (two registers and a signed half operand)

RRH (two registers and an unsigned half operand)

RHH (one register and a half operand, high-order 16 bits encoded)

RRB (two registers and a 16 bit signed offset operand)

J   (no registers and a 26 bit signed offset operand)

JR  (one register operand)

Instruction Set

---------------

Notation:

  'r[n]'        The bits representing 'r' are padded with zeroes

                to the left (or zeroes are dropped from the left)

                until a width of n bits is reached.

  'a || b'      The bits representing 'a' and 'b' are concatenated;

                'a' occupies the more significant bits.

All numbers are given in decimal (base 10), except when prefixed

with "0x", which means they are given in hexadecimal (base 16).

ADD (add)

  format:       RRR

  coding:       0x00[6] || rs1[5] || rs2[5] || rd[5] || 0[11]

  assembler:    add  rd,rs1,rs2

  example:      add  $1,$2,$3

  operation:    The contents of register rs2 are added to the contents

                of register rs1. The result is stored into register rd.

                Overflow is ignored.

ADDI (add immediate)

  format:       RRS

  coding:       0x01[6] || rs1[5] || rd[5] || simm[16]

  assembler:    add  rd,rs1,simm

  example:      add  $1,$2,1234

  operation:    The sign-extended immediate constant simm is added to

                the contents of register rs1. The result is stored into

                register rd. Overflow is ignored.

SUB (subtract)

  format:       RRR

  coding:       0x02[6] || rs1[5] || rs2[5] || rd[5] || 0[11]

  assembler:    sub  rd,rs1,rs2

  example:      sub  $1,$2,$3

  operation:    The contents of register rs2 are subtracted from the

                contents of register rs1. The result is stored into

                register rd. Overflow is ignored.

SUBI (subtract immediate)

  format:       RRS

  coding:       0x03[6] || rs1[5] || rd[5] || simm[16]

  assembler:    sub  rd,rs1,simm

  example:      add  $1,$2,1234

  operation:    The sign-extended immediate constant simm is subtracted

                from the contents of register rs1. The result is stored

                into register rd. Overflow is ignored.

AND (logical and)

  format:       RRR

  coding:       0x10[6] || rs1[5] || rs2[5] || rd[5] || 0[11]

  assembler:    and  rd,rs1,rs2

  example:      and  $1,$2,$3

  operation:    The contents of register rs2 are bitwise anded with the

                contents of register rs1. The result is stored into

                register rd.

ANDI (logical and immediate)

  format:       RRH

  coding:       0x11[6] || rs1[5] || rd[5] || uimm[16]

  assembler:    and  rd,rs1,uimm

  example:      and  $1,$2,1234

  operation:    The zero-extended immediate constant uimm is bitwise

                anded with the contents of register rs1. The result

                is stored into register rd.

OR (logical or)

  format:       RRR

  coding:       0x12[6] || rs1[5] || rs2[5] || rd[5] || 0[11]

  assembler:    or  rd,rs1,rs2

  example:      or  $1,$2,$3

  operation:    The contents of register rs2 are bitwise ored with the

                contents of register rs1. The result is stored into

                register rd.

ORI (logical or immediate)

  format:       RRH

  coding:       0x13[6] || rs1[5] || rd[5] || uimm[16]

  assembler:    or  rd,rs1,uimm

  example:      or  $1,$2,1234

  operation:    The zero-extended immediate constant uimm is bitwise

                ored with the contents of register rs1. The result

                is stored into register rd.

XOR (logical xor)

  format:       RRR

  coding:       0x14[6] || rs1[5] || rs2[5] || rd[5] || 0[11]

  assembler:    xor  rd,rs1,rs2

  example:      xor  $1,$2,$3

  operation:    The contents of register rs2 are bitwise xored with the

                contents of register rs1. The result is stored into

                register rd.

                Remark: (a xor b) <=> ((a and ~b) or (~a and b))

XORI (logical xor immediate)

  format:       RRH

  coding:       0x15[6] || rs1[5] || rd[5] || uimm[16]

  assembler:    xor  rd,rs1,uimm

  example:      xor  $1,$2,1234

  operation:    The zero-extended immediate constant uimm is bitwise

                xored with the contents of register rs1. The result

                is stored into register rd.

                Remark: (a xor b) <=> ((a and ~b) or (~a and b))

XNOR (logical xnor)

  format:       RRR

  coding:       0x16[6] || rs1[5] || rs2[5] || rd[5] || 0[11]

  assembler:    xnor  rd,rs1,rs2

  example:      xnor  $1,$2,$3

  operation:    The contents of register rs2 are bitwise xnored with the

                contents of register rs1. The result is stored into

                register rd.

                Remark: (a xnor b) <=> ((a and b) or (~a and ~b))

XNORI (logical xnor immediate)

  format:       RRH

  coding:       0x17[6] || rs1[5] || rd[5] || uimm[16]

  assembler:    xnor  rd,rs1,uimm

  example:      xnor  $1,$2,1234

  operation:    The zero-extended immediate constant uimm is bitwise

                xnored with the contents of register rs1. The result

                is stored into register rd.

                Remark: (a xnor b) <=> ((a and b) or (~a and ~b))

LDHI (load high immediate)

  format:       RHH

  coding:       0x1F[6] || 0[5] || rd[5] || uimm[16]

  assembler:    ldhi  rd,uimm

  example:      ldhi  $1,1234

  operation:    The zero-extended immediate constant uimm is shifted

                left by 16 bits. The result is stored into register rd.

BEQ (branch on equal)

  format:       RRB

  coding:       0x20[6] || rs1[5] || rs2[5] || simm[16]

  assembler:    beq  rs1,rs2,target

  example:      beq  $1,$2,label3

  operation:    If the contents of register rs1 are equal to the contents

                of register rs2, the sign-extended immediate constant

                simm is shifted left by two bits and added to the address

                of the instruction following the branch instruction. The

                result is placed into the program counter. If the contents

                differ, the next instruction after the branch is executed.

BNE (branch on not equal)

  format:       RRB

  coding:       0x21[6] || rs1[5] || rs2[5] || simm[16]

  assembler:    bne  rs1,rs2,target

  example:      bne  $1,$2,label3

  operation:    If the contents of register rs1 are not equal to the contents

                of register rs2, the sign-extended immediate constant

                simm is shifted left by two bits and added to the address

                of the instruction following the branch instruction. The

                result is placed into the program counter. If the contents

                are equal, the next instruction after the branch is executed.

BLEU (branch on less or equal unsigned)

  format:       RRB

  coding:       0x23[6] || rs1[5] || rs2[5] || simm[16]

  assembler:    bleu  rs1,rs2,target

  example:      bleu  $1,$2,label3

  operation:    If the contents of register rs1 are less than or equal

                to the contents of register rs2 (both are interpreted as

                unsigned numbers), the sign-extended immediate constant

                simm is shifted left by two bits and added to the address

                of the instruction following the branch instruction. The

                result is placed into the program counter. If the contents

                do not satisfy the condition, the next instruction after

                the branch is executed.

BLTU (branch on less than unsigned)

  format:       RRB

  coding:       0x25[6] || rs1[5] || rs2[5] || simm[16]

  assembler:    bltu  rs1,rs2,target

  example:      bltu  $1,$2,label3

  operation:    If the contents of register rs1 are less than the contents

                of register rs2 (both are interpreted as unsigned numbers),

                the sign-extended immediate constant simm is shifted left

                by two bits and added to the address of the instruction

                following the branch instruction. The result is placed into

                the program counter. If the contents do not satisfy the

                condition, the next instruction after the branch is executed.

BGEU (branch on greater or equal unsigned)

  format:       RRB

  coding:       0x27[6] || rs1[5] || rs2[5] || simm[16]

  assembler:    bgeu  rs1,rs2,target

  example:      bgeu  $1,$2,label3

  operation:    If the contents of register rs1 are greater than or equal

                to the contents of register rs2 (both are interpreted as

                unsigned numbers), the sign-extended immediate constant

                simm is shifted left by two bits and added to the address

                of the instruction following the branch instruction. The

                result is placed into the program counter. If the contents

                do not satisfy the condition, the next instruction after

                the branch is executed.

BGTU (branch on greater than unsigned)

  format:       RRB

  coding:       0x29[6] || rs1[5] || rs2[5] || simm[16]

  assembler:    bgtu  rs1,rs2,target

  example:      bgtu  $1,$2,label3

  operation:    If the contents of register rs1 are greater than the contents

                of register rs2 (both are interpreted as unsigned numbers),

                the sign-extended immediate constant simm is shifted left

                by two bits and added to the address of the instruction

                following the branch instruction. The result is placed into

                the program counter. If the contents do not satisfy the

                condition, the next instruction after the branch is executed.

J (jump)

  format:       J

  coding:       0x2A[6] || simm[26]

  assembler:    j  target

  example:      j  label3

  operation:    The sign-extended immediate constant simm is shifted left

                by two bits and added to the address of the instruction

                following the jump instruction. The result is placed into

                the program counter.

JR (jump register)

  format:       JR

  coding:       0x2B[6] || rs[5] || 0[5] || 0[16]

  assembler:    jr  rs

  example:      jr  $31

  operation:    The contents of register rs are placed into the program

                counter.

JAL (jump and link)

  format:       J

  coding:       0x2C[6] || simm[26]

  assembler:    jal  target

  example:      jal  label3

  operation:    The address of the instruction following the jal instruction

                is placed into register 31. The sign-extended immediate

                constant simm is shifted left by two bits and added to the

                address of the instruction following the jal instruction.

                The result is placed into the program counter.

LDW (load word)

  format:       RRS

  coding:       0x30[6] || rs[5] || rd[5] || simm[16]

  assembler:    ldw  rd,rs,simm

  example:      ldw  $1,$2,1234

  operation:    The sign-extended immediate constant simm is added to the

                contents of register rs to form an effective memory address.

                A word is read from this address and stored into register

                rd.

LDH (load halfword)

  format:       RRS

  coding:       0x31[6] || rs[5] || rd[5] || simm[16]

  assembler:    ldh  rd,rs,simm

  example:      ldh  $1,$2,1234

  operation:    The sign-extended immediate constant simm is added to the

                contents of register rs to form an effective memory address.

                A halfword is read from this address, sign-extended, and

                stored into register rd.

LDHU (load halfword unsigned)

  format:       RRS

  coding:       0x32[6] || rs[5] || rd[5] || simm[16]

  assembler:    ldhu  rd,rs,simm

  example:      ldhu  $1,$2,1234

  operation:    The sign-extended immediate constant simm is added to the

                contents of register rs to form an effective memory address.

                A halfword is read from this address, zero-extended, and

                stored into register rd.

LDB (load byte)

  format:       RRS

  coding:       0x33[6] || rs[5] || rd[5] || simm[16]

  assembler:    ldb  rd,rs,simm

  example:      ldb  $1,$2,1234

  operation:    The sign-extended immediate constant simm is added to the

                contents of register rs to form an effective memory address.

                A byte is read from this address, sign-extended, and stored

                into register rd.

LDBU (load byte unsigned)

  format:       RRS

  coding:       0x34[6] || rs[5] || rd[5] || simm[16]

  assembler:    ldbu  rd,rs,simm

  example:      ldbu  $1,$2,1234

  operation:    The sign-extended immediate constant simm is added to the

                contents of register rs to form an effective memory address.

                A byte is read from this address, zero-extended, and stored

                into register rd.

STW (store word)

  format:       RRS

  coding:       0x35[6] || rs[5] || rd[5] || simm[16]

  assembler:    stw  rd,rs,simm

  example:      stw  $1,$2,1234

  operation:    The sign-extended immediate constant simm is added to the

                contents of register rs to form an effective memory address.

                The contents of register rd (all 32 bits) are stored

                as a word to this address.

STH (store halfword)

  format:       RRS

  coding:       0x36[6] || rs[5] || rd[5] || simm[16]

  assembler:    sth  rd,rs,simm

  example:      sth  $1,$2,1234

  operation:    The sign-extended immediate constant simm is added to the

                contents of register rs to form an effective memory address.

                The contents of register rd (the lower 16 bits) are stored

                as a halfword to this address.

STB (store byte)

  format:       RRS

  coding:       0x37[6] || rs[5] || rd[5] || simm[16]

  assembler:    stb  rd,rs,simm

  example:      stb  $1,$2,1234

  operation:    The sign-extended immediate constant simm is added to the

                contents of register rs to form an effective memory address.

                The contents of register rd (the lowest 8 bits) are stored

                as a byte to this address.

Interrupts and Exceptions

-------------------------

There are neither interrupts nor exceptions in this version of ECO32e.

Unknown opcodes should nevertheless be recognized. A CPU simulation can

then report the execution of an unknown opcode; an implementation may

trap such an execution in a state of its controller which cannot be left

without reset.

Peripherals

-----------

Peripherals are memory-mapped. They need only support word accesses.

A sensible reaction to accesses with smaller widths (halfword or byte)

is not required.

In this version of ECO32e there are only two peripherals: a character

display and a keyboard.

The character display is capable of showing 30 lines with 80 characters

each. Its base address is 0x30100000. Each line occupies 128 words in

the I/O address space, one word for each column (and 48 unusable columns

at the end of the line). Therefore the address to which a character is

written and its location on the screen are related as follows:

    address = 0x30100000 + (line * 128 + column) * 4

The character to be displayed must be written as a word to the corresponding

address with its ASCII code contained in the lowest 8 bits of the word.

The keyboard is represented by two I/O registers. The status register

is located at address 0x30200000. When read (32 bits), its LSB indicates

if a character has been received from the physical keyboard. If this bit

is 1, the character can be read at address 0x30200004, the address of

the data register. By reading this latter address, the LSB of the

status register is automatically reset to 0. The data register must be

read with a word read; the character read is contained in the lowest

8 bits of the word.