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<HTML>
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<HEAD>
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<TITLE>Assembler Short Reference</TITLE>
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</HEAD>
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<BODY>
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<H2>
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ECO32 Instruction Set Architecture
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</H2>
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<TABLE BORDER=1>
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<TR><TH> Format </TH><TH> Description                                                    </TH></TR>
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<TR><TD> N      </TD><TD> no operands                                                    </TD></TR>
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<TR><TD> RH     </TD><TD> one register and the lower 16 bits of a word                   </TD></TR>
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<TR><TD> RHH    </TD><TD> one register and the upper 16 bits of a word                   </TD></TR>
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<TR><TD> RRH    </TD><TD> two registers and a zero-extended halfword                     </TD></TR>
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<TR><TD> RRS    </TD><TD> two registers and a sign-extended halfword                     </TD></TR>
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<TR><TD> RRR    </TD><TD> three registers                                                </TD></TR>
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<TR><TD> RRX    </TD><TD> three registers, or two registers and a zero-extended halfword </TD></TR>
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<TR><TD> RRY    </TD><TD> three registers, or two registers and a sign-extended halfword </TD></TR>
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<TR><TD> RRB    </TD><TD> two registers and a sign-extended 16 bit offset                </TD></TR>
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<TR><TD> J      </TD><TD> no registers and a sign-extended 26 bit offset                 </TD></TR>
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<TR><TD> JR     </TD><TD> one register                                                   </TD></TR>
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</TABLE>
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<BR>
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<TABLE BORDER=1>
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<TR><TH> Mnemonic </TH><TH> Operands         </TH><TH> Description                                      </TH><TH> Format </TH></TR>
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<TR><TD> add      </TD><TD> dst, op1, op2    </TD><TD> dst := op1 + op2                                 </TD><TD> RRY    </TD></TR>
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<TR><TD> sub      </TD><TD> dst, op1, op2    </TD><TD> dst := op1 - op2                                 </TD><TD> RRY    </TD></TR>
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<TR><TD> mul      </TD><TD> dst, op1, op2    </TD><TD> dst := op1 * op2, signed                         </TD><TD> RRY    </TD></TR>
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<TR><TD> mulu     </TD><TD> dst, op1, op2    </TD><TD> dst := op1 * op2, unsigned                       </TD><TD> RRX    </TD></TR>
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<TR><TD> div      </TD><TD> dst, op1, op2    </TD><TD> dst := op1 / op2, signed                         </TD><TD> RRY    </TD></TR>
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<TR><TD> divu     </TD><TD> dst, op1, op2    </TD><TD> dst := op1 / op2, unsigned                       </TD><TD> RRX    </TD></TR>
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<TR><TD> rem      </TD><TD> dst, op1, op2    </TD><TD> dst := remainder of op1/op2, signed              </TD><TD> RRY    </TD></TR>
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<TR><TD> remu     </TD><TD> dst, op1, op2    </TD><TD> dst := remainder of op1/op2, unsigned            </TD><TD> RRX    </TD></TR>
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<TR><TD> and      </TD><TD> dst, op1, op2    </TD><TD> dst := bitwise AND of op1 and op2                </TD><TD> RRX    </TD></TR>
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<TR><TD> or       </TD><TD> dst, op1, op2    </TD><TD> dst := bitwise OR of op1 and op2                 </TD><TD> RRX    </TD></TR>
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<TR><TD> xor      </TD><TD> dst, op1, op2    </TD><TD> dst := bitwise XOR of op1 and op2                </TD><TD> RRX    </TD></TR>
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<TR><TD> xnor     </TD><TD> dst, op1, op2    </TD><TD> dst := bitwise XNOR of op1 and op2               </TD><TD> RRX    </TD></TR>
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<TR><TD> sll      </TD><TD> dst, op1, op2    </TD><TD> dst := shift op1 logically left by op2           </TD><TD> RRX    </TD></TR>
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<TR><TD> slr      </TD><TD> dst, op1, op2    </TD><TD> dst := shift op1 logically right by op2          </TD><TD> RRX    </TD></TR>
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<TR><TD> sar      </TD><TD> dst, op1, op2    </TD><TD> dst := shift op1 arithmetically right by op2     </TD><TD> RRX    </TD></TR>
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<TR><TD> ldhi     </TD><TD> dst, op1         </TD><TD> dst := op1 shifted left by 16 bits               </TD><TD> RHH    </TD></TR>
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<TR><TD> beq      </TD><TD> op1, op2, offset </TD><TD> branch to PC+4+offset*4 if op1 == op2            </TD><TD> RRB    </TD></TR>
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<TR><TD> bne      </TD><TD> op1, op2, offset </TD><TD> branch to PC+4+offset*4 if op1 != op2            </TD><TD> RRB    </TD></TR>
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<TR><TD> ble      </TD><TD> op1, op2, offset </TD><TD> branch to PC+4+offset*4 if op1 <= op2 (signed)   </TD><TD> RRB    </TD></TR>
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<TR><TD> bleu     </TD><TD> op1, op2, offset </TD><TD> branch to PC+4+offset*4 if op1 <= op2 (unsigned) </TD><TD> RRB    </TD></TR>
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<TR><TD> blt      </TD><TD> op1, op2, offset </TD><TD> branch to PC+4+offset*4 if op1 <  op2 (signed)   </TD><TD> RRB    </TD></TR>
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<TR><TD> bltu     </TD><TD> op1, op2, offset </TD><TD> branch to PC+4+offset*4 if op1 <  op2 (unsigned) </TD><TD> RRB    </TD></TR>
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<TR><TD> bge      </TD><TD> op1, op2, offset </TD><TD> branch to PC+4+offset*4 if op1 >= op2 (signed)   </TD><TD> RRB    </TD></TR>
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<TR><TD> bgeu     </TD><TD> op1, op2, offset </TD><TD> branch to PC+4+offset*4 if op1 >= op2 (unsigned) </TD><TD> RRB    </TD></TR>
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<TR><TD> bgt      </TD><TD> op1, op2, offset </TD><TD> branch to PC+4+offset*4 if op1 >  op2 (signed)   </TD><TD> RRB    </TD></TR>
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<TR><TD> bgtu     </TD><TD> op1, op2, offset </TD><TD> branch to PC+4+offset*4 if op1 >  op2 (unsigned) </TD><TD> RRB    </TD></TR>
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<TR><TD> j        </TD><TD> offset           </TD><TD> jump to PC+4+offset*4                            </TD><TD> J      </TD></TR>
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<TR><TD> jr       </TD><TD> register         </TD><TD> jump to register                                 </TD><TD> JR     </TD></TR>
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<TR><TD> jal      </TD><TD> offset           </TD><TD> jump to PC+4+offset*4, store PC+4 in $31         </TD><TD> J      </TD></TR>
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<TR><TD> jalr     </TD><TD> register         </TD><TD> jump to register, store PC+4 in $31              </TD><TD> JR     </TD></TR>
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<TR><TD> trap     </TD><TD> -/-              </TD><TD> cause a trap, store PC in $30                    </TD><TD> N      </TD></TR>
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<TR><TD> rfx      </TD><TD> -/-              </TD><TD> return from exception, restore PC from $30       </TD><TD> N      </TD></TR>
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<TR><TD> ldw      </TD><TD> dst, reg, offset </TD><TD> dst := word @ (reg+offset)                       </TD><TD> RRS    </TD></TR>
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<TR><TD> ldh      </TD><TD> dst, reg, offset </TD><TD> dst := sign-extended halfword @ (reg+offset)     </TD><TD> RRS    </TD></TR>
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<TR><TD> ldhu     </TD><TD> dst, reg, offset </TD><TD> dst := zero-extended halfword @ (reg+offset)     </TD><TD> RRS    </TD></TR>
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<TR><TD> ldb      </TD><TD> dst, reg, offset </TD><TD> dst := sign-extended byte @ (reg+offset)         </TD><TD> RRS    </TD></TR>
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<TR><TD> ldbu     </TD><TD> dst, reg, offset </TD><TD> dst := zero-extended byte @ (reg+offset)         </TD><TD> RRS    </TD></TR>
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<TR><TD> stw      </TD><TD> src, reg, offset </TD><TD> store src word @ (reg+offset)                    </TD><TD> RRS    </TD></TR>
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<TR><TD> sth      </TD><TD> src, reg, offset </TD><TD> store src halfword @ (reg+offset)                </TD><TD> RRS    </TD></TR>
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<TR><TD> stb      </TD><TD> src, reg, offset </TD><TD> store src byte @ (reg+offset)                    </TD><TD> RRS    </TD></TR>
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<TR><TD> mvfs     </TD><TD> dst, special     </TD><TD> dst := contents of special register              </TD><TD> RH     </TD></TR>
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<TR><TD> mvts     </TD><TD> src, special     </TD><TD> contents of special register := src              </TD><TD> RH     </TD></TR>
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<TR><TD> tbs      </TD><TD> -/-              </TD><TD> TLB search                                       </TD><TD> N      </TD></TR>
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<TR><TD> tbwr     </TD><TD> -/-              </TD><TD> TLB write random                                 </TD><TD> N      </TD></TR>
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<TR><TD> tbri     </TD><TD> -/-              </TD><TD> TLB read index                                   </TD><TD> N      </TD></TR>
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<TR><TD> tbwi     </TD><TD> -/-              </TD><TD> TLB write index                                  </TD><TD> N      </TD></TR>
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</TABLE>
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<BR>
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<TABLE BORDER=1>
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<TR><TH COLSPAN=8> Integer Registers </TH></TR>
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<TR>
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<TD> $0  </TD> <TD> always zero                      </TD>
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<TD> $8  </TD> <TD> temporary register (caller-save) </TD>
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<TD> $16 </TD> <TD> register variable  (callee-save) </TD>
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<TD> $24 </TD> <TD> temporary register (caller-save) </TD>
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</TR>
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<TR>
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<TD> $1  </TD> <TD> reserved for assembler           </TD>
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<TD> $9  </TD> <TD> temporary register (caller-save) </TD>
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<TD> $17 </TD> <TD> register variable  (callee-save) </TD>
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<TD> $25 </TD> <TD> temporary register (caller-save) </TD>
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</TR>
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<TR>
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<TD> $2  </TD> <TD> func return value                </TD>
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<TD> $10 </TD> <TD> temporary register (caller-save) </TD>
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<TD> $18 </TD> <TD> register variable  (callee-save) </TD>
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<TD> $26 </TD> <TD> reserved for OS kernel           </TD>
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</TR>
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<TR>
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<TD> $3  </TD> <TD> func return value                </TD>
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<TD> $11 </TD> <TD> temporary register (caller-save) </TD>
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<TD> $19 </TD> <TD> register variable  (callee-save) </TD>
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<TD> $27 </TD> <TD> reserved for OS kernel           </TD>
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</TR>
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<TR>
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<TD> $4  </TD> <TD> proc/func argument               </TD>
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<TD> $12 </TD> <TD> temporary register (caller-save) </TD>
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<TD> $20 </TD> <TD> register variable  (callee-save) </TD>
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<TD> $28 </TD> <TD> reserved for OS kernel           </TD>
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</TR>
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<TR>
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<TD> $5  </TD> <TD> proc/func argument               </TD>
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<TD> $13 </TD> <TD> temporary register (caller-save) </TD>
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<TD> $21 </TD> <TD> register variable  (callee-save) </TD>
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<TD> $29 </TD> <TD> stack pointer                    </TD>
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</TR>
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<TR>
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<TD> $6  </TD> <TD> proc/func argument               </TD>
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<TD> $14 </TD> <TD> temporary register (caller-save) </TD>
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<TD> $22 </TD> <TD> register variable  (callee-save) </TD>
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<TD> $30 </TD> <TD> interrupt return address         </TD>
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</TR>
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<TR>
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<TD> $7  </TD> <TD> proc/func argument               </TD>
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<TD> $15 </TD> <TD> temporary register (caller-save) </TD>
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<TD> $23 </TD> <TD> register variable  (callee-save) </TD>
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<TD> $31 </TD> <TD> proc/func return address         </TD>
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</TR>
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</TABLE>
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<BR>
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<TABLE BORDER=1>
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<TR><TH COLSPAN=8> Special Registers </TH></TR>
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<TR>
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<TD>0</TD><TD> Processor Status </TD>
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</TR>
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<TR>
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<TD>1</TD><TD> TLB Index        </TD>
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<TD>2</TD><TD> TLB Entry High   </TD>
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<TD>3</TD><TD> TLB Entry Low    </TD>
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<TD>4</TD><TD> TLB Bad Address  </TD>
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</TR>
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</TABLE>
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<BR>
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<TABLE BORDER=1>
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<TR>
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        <TH COLSPAN=9> Processor Status Register </TH>
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</TR><TR>
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        <TD> 31 .. 27 </TD>
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        <TD> 26 </TD><TD> 25 </TD><TD> 24 </TD>
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        <TD> 23 </TD><TD> 22 </TD><TD> 21 </TD>
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        <TD> 20 .. 16 </TD>
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        <TD> 15 .. 0 </TD>
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</TR><TR>
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        <TD></TD>
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        <TD COLSPAN=3> User Mode </TD>
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        <TD COLSPAN=3> Interrupt Enable </TD>
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        <TD> Priority </TD>
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        <TD> Interupt Mask </TD>
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</TR><TR>
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        <TD></TD>
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        <TD> Cur </TD><TD> Prv </TD><TD> Old </TD>
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        <TD> Cur </TD><TD> Prv </TD><TD> Old </TD>
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        <TD> 0 .. 31 </TD>
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        <TD></TD>
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</TR>
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</TABLE>
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