The ECO32 is a general-purpose 32-bit RISC soft-core microprocessor, to be
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implemented on an FPGA. It was originally designed to understand the RISC
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architecture as described by Hennessy and Patterson in their books. The
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current version is a simple, albeit slow implementation of the instruction
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set architecture described in this manual. Future versions will include
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various optimizations to make the ECO32 feasible for real-world projects.
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\section{Features}
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The \eco supports the following features:
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\begin{itemize}
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\item Soft-core processor to be implemented on an FPGA
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\item 32 general-purpose registers, each 32 bits wide
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\item 32-bit ALU, shifter, multiplication and division units
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\item load/store architecture
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\item 32-bit unified instruction and data address space
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\item 16 external interrupt lines
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\item two privilege modes to execute both trusted and untrusted code
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\item paged virtual memory with a page size of 4K
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\item assembler, instruction-set simulator, and C compiler support
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\end{itemize}
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\section{Requirements}
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So far, the \eco has only been implemented on a Xilinx Spartan-3 FPGA. Implementing it on other FPGAs may cause problems if the \eco uses device primitives that are not supported on the target platform.
