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\section{Computation Instructions}
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\newcommand{\rdivzero}{\effect if $R_y=0$ then trigger a \name{Division by Zero Fault}}
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\newcommand{\idivzero}{\effect if $y=0$ then trigger a \name{Division by Zero Fault}}
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The computation instructions compute a function of register values and/or immediate values, and store their result in a general-purpose register.
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\subsection{ADD}
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The ADD instruction computes the sum of two 32-bit register operands, truncated to 32 bits.\\
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\rrrformat{000000}
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\regeffects{truncate_{32}(R_x + R_y)}
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\subsection{ADDI}
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The ADDI instruction computes the sum of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\
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\rriformat{000001}
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\regeffects{truncate_{32}(R_x + signext_{32}(y))}
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\subsection{SUB}
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The SUB instruction computes the difference of two 32-bit register operands, truncated to 32 bits.\\
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\rrrformat{000010}
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\regeffects{truncate_{32}(R_x - R_y)}
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\subsection{SUBI}
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The SUBI instruction computes the difference of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\
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\rriformat{000011}
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\regeffects{truncate_{32}(R_x - signext_{32}(y))}
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\subsection{MUL}
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The MUL instruction computes the signed product of two 32-bit register operands, truncated to 32 bits.\\
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\rrrformat{000100}
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\regeffects{truncate_{32}(R_x *_{signed} R_y)}
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\subsection{MULI}
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The MULI instruction computes the signed product of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\
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\rriformat{000101}
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\regeffects{truncate_{32}(R_x *_{signed} signext_{32}(y))}
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\subsection{MULU}
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The MULU instruction computes the unsigned product of two 32-bit register operands, truncated to 32 bits.\\
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\rrrformat{000110}
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\regeffects{truncate_{32}(R_x *_{unsigned} R_y)}
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\subsection{MULUI}
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The MULUI instruction computes the unsigned product of a 32-bit register operand and a zero-extended 16-bit immediate operand, truncated to 32 bits.\\
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\rriformat{000111}
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\regeffects{truncate_{32}(R_x *_{unsigned} zeroext_{32}(y))}
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\subsection{DIV}
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The DIV instruction computes the signed quotient of two 32-bit register operands, truncated to 32 bits.\\
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\rrrformat{001000}
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\begin{effectize}
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\rdivzero
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\regeffect{truncate_{32}(R_x /_{signed} R_y)}
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\end{effectize}
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\subsection{DIVI}
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The DIVI instruction computes the signed quotient of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\
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\rrrformat{001001}
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\begin{effectize}
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\idivzero
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\regeffect{truncate_{32}(R_x /_{signed} signext_{32}(y))}
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\end{effectize}
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\subsection{DIVU}
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The DIVU instruction computes the unsigned quotient of two unsigned 32-bit register operands, truncated to 32 bits.\\
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\rrrformat{001010}
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\begin{effectize}
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\rdivzero
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\regeffect{truncate_{32}(R_x /_{unsigned} R_y)}
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\end{effectize}
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\subsection{DIVUI}
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The DIVUI instruction computes the unsigned quotient of a 32-bit register operand and a zero-extended 16-bit immediate operand, truncated to 32 bits.\\
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\rrrformat{001011}
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\begin{effectize}
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\idivzero
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\regeffect{truncate_{32}(R_x /_{unsigned} zeroext_{32}(y))}
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\end{effectize}
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\subsection{REM}
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The REM instruction computes the signed remainder of two 32-bit register operands, truncated to 32 bits.\\
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\rrrformat{001100}
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\begin{effectize}
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\rdivzero
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\regeffect{truncate_{32}(R_x MOD_{signed} R_y)}
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\end{effectize}
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\subsection{REMI}
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The REMI instruction computes the signed remainder of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\
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\rrrformat{001101}
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\begin{effectize}
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\idivzero
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\regeffect{truncate_{32}(R_x MOD_{signed} signext_{32}(y))}
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\end{effectize}
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\subsection{REMU}
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The REMU instruction computes the unsigned remainder of two unsigned 32-bit register operands, truncated to 32 bits.\\
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\rrrformat{001110}
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\begin{effectize}
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\rdivzero
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\regeffect{truncate_{32}(R_x MOD_{unsigned} R_y)}
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\end{effectize}
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\subsection{REMUI}
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The REMUI instruction computes the unsigned remainder of a 32-bit register operand and a zero-extended 16-bit immediate operand, truncated to 32 bits.\\
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\rrrformat{001111}
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\begin{effectize}
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\idivzero
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\regeffect{truncate_{32}(R_x MOD_{unsigned} zeroext_{32}(y))}
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\end{effectize}
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\subsection{AND}
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The AND instruction computes the bitwise AND of two 32-bit register operands.\\
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\rrrformat{010000}
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\bitregeffects{R_{x,i} \wedge R_{y,i}}
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\subsection{ANDI}
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The ANDI instruction computes the bitwise AND of a 32-bit register operand and a zero-extended 16-bit immediate operand.\\
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\rriformat{010001}
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\bitregeffects{R_{x,i} \wedge zeroext_{32}(y)_i}
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\subsection{OR}
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The OR instruction computes the bitwise OR of two 32-bit register operands.\\
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\rrrformat{010010}
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\bitregeffects{R_{x,i} \vee R_{y,i}}
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\subsection{ORI}
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The ORI instruction computes the bitwise OR of a 32-bit register operand and a zero-extended 16-bit immediate operand.\\
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\rriformat{010011}
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\bitregeffects{R_{x,i} \vee zeroext_{32}(y)_i}
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\subsection{XOR}
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The XOR instruction computes the bitwise XOR of two 32-bit register operands.\\
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\rrrformat{010100}
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\bitregeffects{R_{x,i} \oplus R_{y,i}}
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\subsection{XORI}
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The XORI instruction computes the bitwise XOR of a 32-bit register operand and a zero-extended 16-bit immediate operand.\\
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\rriformat{010101}
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\bitregeffects{R_{x,i} \oplus zeroext_{32}(y)_i}
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\subsection{XNOR}
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The XNOR instruction computes the bitwise XNOR of two 32-bit register operands.\\
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\rrrformat{010110}
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\bitregeffects{\overline{R_{x,i} \oplus R_{y,i}}}
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\subsection{XNORI}
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The XNORI instruction computes the bitwise XNOR of a 32-bit register operand and a zero-extended 16-bit immediate operand.\\
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\rriformat{010111}
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\bitregeffects{\overline{R_{x,i} \oplus zeroext_{32}(y)_i}}
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\subsection{SLL}
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The SLL instruction computes the result of shifting the first 32-bit register operand to the left by a number of bits specified by the 5 least significant bits of the second 32-bit register operand, and filling up with 0 bits.\\
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\rrrformat{011000}
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\begin{effectize}
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\effect $shift \leftarrow unsigned(R_{y,4..0})$
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\effect $temp_i \leftarrow R_{x,i-shift}$ if $i \geq shift$
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\effect $temp_i \leftarrow 0$ if $i < shift$
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\effect $R_r \leftarrow temp$
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\end{effectize}
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\subsection{SLLI}
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The SLLI instruction computes the result of shifting the 32-bit register operand to the left by a number of bits specified by the 5 least significant bits of the immediate operand, and filling up with 0 bits.\\
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\rriformat{011001}
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\begin{effectize}
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\effect $shift \leftarrow unsigned(y_{4..0})$
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\effect $temp_i \leftarrow R_{x,i-shift}$ if $i \geq shift$
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\effect $temp_i \leftarrow 0$ if $i < shift$
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\effect $R_r \leftarrow temp$
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\end{effectize}
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\subsection{SLR}
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The SLR instruction computes the result of shifting the first 32-bit register operand to the right by a number of bits specified by the 5 least significant bits of the second 32-bit register operand, and filling up with 0 bits.\\
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\rrrformat{011010}
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\begin{effectize}
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\effect $shift \leftarrow unsigned(R_{y,4..0})$
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\effect $temp_i \leftarrow R_{x,i+shift}$ if $i + shift < 32$
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\effect $temp_i \leftarrow 0$ if $i + shift \geq 32$
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\effect $R_r \leftarrow temp$
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\end{effectize}
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\subsection{SLRI}
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The SLRI instruction computes the result of shifting the 32-bit register operand to the right by a number of bits specified by the 5 least significant bits of the immediate operand, and filling up with 0 bits.\\
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\rriformat{011011}
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\begin{effectize}
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\effect $shift \leftarrow unsigned(y_{4..0})$
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\effect $temp_i \leftarrow R_{x,i+shift}$ if $i + shift < 32$
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\effect $temp_i \leftarrow 0$ if $i + shift \geq 32$
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\effect $R_r \leftarrow temp$
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\end{effectize}
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\subsection{SAR}
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The SAR instruction computes the result of shifting the first 32-bit register operand to the right by a number of bits specified by the 5 least significant bits of the second 32-bit register operand, and replicating the topmost (sign) bit.\\
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\rrrformat{011100}
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\begin{effectize}
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\effect $shift \leftarrow unsigned(R_{y,4..0})$
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\effect $temp_i \leftarrow R_{x,i+shift}$ if $i + shift < 32$
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\effect $temp_i \leftarrow R_{x,31}$ if $i + shift \geq 32$
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\effect $R_r \leftarrow temp$
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\end{effectize}
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\subsection{SARI}
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The SARI instruction computes the result of shifting the 32-bit register operand to the right by a number of bits specified by the 5 least significant bits of the immediate operand, and replicating the topmost (sign) bit.\\
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\rriformat{011101}
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\begin{effectize}
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\effect $shift \leftarrow unsigned(y_{4..0})$
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\effect $temp_i \leftarrow R_{x,i+shift}$ if $i + shift < 32$
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\effect $temp_i \leftarrow R_{x,31}$ if $i + shift \geq 32$
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\effect $R_r \leftarrow temp$
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\end{effectize}
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\subsection{LDHI}
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The LDHI instruction is used to generate large constants. The upper 16 bits of the result are taken from the 16-bit immediate operand. The lower 16 bits of the result are 0.\\
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\rriformat{011111}
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\begin{effectize}
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\effect $R_{r,31..16} \leftarrow y_{15..0}$
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\effect $R_{r,15..0} \leftarrow 0$
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\end{effectize}

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