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\section{Computation Instructions}
 
\newcommand{\rdivzero}{\effect if $R_y=0$ then trigger a \name{Division by Zero Fault}}
\newcommand{\idivzero}{\effect if $y=0$ then trigger a \name{Division by Zero Fault}}
 
The computation instructions compute a function of register values and/or immediate values, and store their result in a general-purpose register.
 
\subsection{ADD}
 
The ADD instruction computes the sum of two 32-bit register operands, truncated to 32 bits.\\
 
\rrrformat{000000}
 
\regeffects{truncate_{32}(R_x + R_y)}
 
\subsection{ADDI}
 
The ADDI instruction computes the sum of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\
 
\rriformat{000001}
 
\regeffects{truncate_{32}(R_x + signext_{32}(y))}
 
\subsection{SUB}
 
The SUB instruction computes the difference of two 32-bit register operands, truncated to 32 bits.\\
 
\rrrformat{000010}
 
\regeffects{truncate_{32}(R_x - R_y)}
 
\subsection{SUBI}
 
The SUBI instruction computes the difference of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\
 
\rriformat{000011}
 
\regeffects{truncate_{32}(R_x - signext_{32}(y))}
 
\subsection{MUL}
 
The MUL instruction computes the signed product of two 32-bit register operands, truncated to 32 bits.\\
 
\rrrformat{000100}
 
\regeffects{truncate_{32}(R_x *_{signed} R_y)}
 
\subsection{MULI}
 
The MULI instruction computes the signed product of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\
 
\rriformat{000101}
 
\regeffects{truncate_{32}(R_x *_{signed} signext_{32}(y))}
 
\subsection{MULU}
 
The MULU instruction computes the unsigned product of two 32-bit register operands, truncated to 32 bits.\\
 
\rrrformat{000110}
 
\regeffects{truncate_{32}(R_x *_{unsigned} R_y)}
 
\subsection{MULUI}
 
The MULUI instruction computes the unsigned product of a 32-bit register operand and a zero-extended 16-bit immediate operand, truncated to 32 bits.\\
 
\rriformat{000111}
 
\regeffects{truncate_{32}(R_x *_{unsigned} zeroext_{32}(y))}
 
\subsection{DIV}
 
The DIV instruction computes the signed quotient of two 32-bit register operands, truncated to 32 bits.\\
 
\rrrformat{001000}
 
\begin{effectize}
\rdivzero
\regeffect{truncate_{32}(R_x /_{signed} R_y)}
\end{effectize}
 
\subsection{DIVI}
 
The DIVI instruction computes the signed quotient of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\
 
\rrrformat{001001}
 
\begin{effectize}
\idivzero
\regeffect{truncate_{32}(R_x /_{signed} signext_{32}(y))}
\end{effectize}
 
\subsection{DIVU}
 
The DIVU instruction computes the unsigned quotient of two unsigned 32-bit register operands, truncated to 32 bits.\\
 
\rrrformat{001010}
 
\begin{effectize}
\rdivzero
\regeffect{truncate_{32}(R_x /_{unsigned} R_y)}
\end{effectize}
 
\subsection{DIVUI}
 
The DIVUI instruction computes the unsigned quotient of a 32-bit register operand and a zero-extended 16-bit immediate operand, truncated to 32 bits.\\
 
\rrrformat{001011}
 
\begin{effectize}
\idivzero
\regeffect{truncate_{32}(R_x /_{unsigned} zeroext_{32}(y))}
\end{effectize}
 
\subsection{REM}
 
The REM instruction computes the signed remainder of two 32-bit register operands, truncated to 32 bits.\\
 
\rrrformat{001100}
 
\begin{effectize}
\rdivzero
\regeffect{truncate_{32}(R_x MOD_{signed} R_y)}
\end{effectize}
 
\subsection{REMI}
 
The REMI instruction computes the signed remainder of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\
 
\rrrformat{001101}
 
\begin{effectize}
\idivzero
\regeffect{truncate_{32}(R_x MOD_{signed} signext_{32}(y))}
\end{effectize}
 
\subsection{REMU}
 
The REMU instruction computes the unsigned remainder of two unsigned 32-bit register operands, truncated to 32 bits.\\
 
\rrrformat{001110}
 
\begin{effectize}
\rdivzero
\regeffect{truncate_{32}(R_x MOD_{unsigned} R_y)}
\end{effectize}
 
\subsection{REMUI}
 
The REMUI instruction computes the unsigned remainder of a 32-bit register operand and a zero-extended 16-bit immediate operand, truncated to 32 bits.\\
 
\rrrformat{001111}
 
\begin{effectize}
\idivzero
\regeffect{truncate_{32}(R_x MOD_{unsigned} zeroext_{32}(y))}
\end{effectize}
 
\subsection{AND}
 
The AND instruction computes the bitwise AND of two 32-bit register operands.\\
 
\rrrformat{010000}
 
\bitregeffects{R_{x,i} \wedge R_{y,i}}
 
\subsection{ANDI}
 
The ANDI instruction computes the bitwise AND of a 32-bit register operand and a zero-extended 16-bit immediate operand.\\
 
\rriformat{010001}
 
\bitregeffects{R_{x,i} \wedge zeroext_{32}(y)_i}
 
\subsection{OR}
 
The OR instruction computes the bitwise OR of two 32-bit register operands.\\
 
\rrrformat{010010}
 
\bitregeffects{R_{x,i} \vee R_{y,i}}
 
\subsection{ORI}
 
The ORI instruction computes the bitwise OR of a 32-bit register operand and a zero-extended 16-bit immediate operand.\\
 
\rriformat{010011}
 
\bitregeffects{R_{x,i} \vee zeroext_{32}(y)_i}
 
\subsection{XOR}
 
The XOR instruction computes the bitwise XOR of two 32-bit register operands.\\
 
\rrrformat{010100}
 
\bitregeffects{R_{x,i} \oplus R_{y,i}}
 
\subsection{XORI}
 
The XORI instruction computes the bitwise XOR of a 32-bit register operand and a zero-extended 16-bit immediate operand.\\
 
\rriformat{010101}
 
\bitregeffects{R_{x,i} \oplus zeroext_{32}(y)_i}
 
\subsection{XNOR}
 
The XNOR instruction computes the bitwise XNOR of two 32-bit register operands.\\
 
\rrrformat{010110}
 
\bitregeffects{\overline{R_{x,i} \oplus R_{y,i}}}
 
\subsection{XNORI}
 
The XNORI instruction computes the bitwise XNOR of a 32-bit register operand and a zero-extended 16-bit immediate operand.\\
 
\rriformat{010111}
 
\bitregeffects{\overline{R_{x,i} \oplus zeroext_{32}(y)_i}}
 
\subsection{SLL}
 
The SLL instruction computes the result of shifting the first 32-bit register operand to the left by a number of bits specified by the 5 least significant bits of the second 32-bit register operand, and filling up with 0 bits.\\
 
\rrrformat{011000}
 
\begin{effectize}
\effect $shift \leftarrow unsigned(R_{y,4..0})$
\effect $temp_i \leftarrow R_{x,i-shift}$ if $i \geq shift$
\effect $temp_i \leftarrow 0$ if $i < shift$
\effect $R_r \leftarrow temp$
\end{effectize}
 
\subsection{SLLI}
 
The SLLI instruction computes the result of shifting the 32-bit register operand to the left by a number of bits specified by the 5 least significant bits of the immediate operand, and filling up with 0 bits.\\
 
\rriformat{011001}
 
\begin{effectize}
\effect $shift \leftarrow unsigned(y_{4..0})$
\effect $temp_i \leftarrow R_{x,i-shift}$ if $i \geq shift$
\effect $temp_i \leftarrow 0$ if $i < shift$
\effect $R_r \leftarrow temp$
\end{effectize}
 
\subsection{SLR}
 
The SLR instruction computes the result of shifting the first 32-bit register operand to the right by a number of bits specified by the 5 least significant bits of the second 32-bit register operand, and filling up with 0 bits.\\
 
\rrrformat{011010}
 
\begin{effectize}
\effect $shift \leftarrow unsigned(R_{y,4..0})$
\effect $temp_i \leftarrow R_{x,i+shift}$ if $i + shift < 32$
\effect $temp_i \leftarrow 0$ if $i + shift \geq 32$
\effect $R_r \leftarrow temp$
\end{effectize}
 
\subsection{SLRI}
 
The SLRI instruction computes the result of shifting the 32-bit register operand to the right by a number of bits specified by the 5 least significant bits of the immediate operand, and filling up with 0 bits.\\
 
\rriformat{011011}
 
\begin{effectize}
\effect $shift \leftarrow unsigned(y_{4..0})$
\effect $temp_i \leftarrow R_{x,i+shift}$ if $i + shift < 32$
\effect $temp_i \leftarrow 0$ if $i + shift \geq 32$
\effect $R_r \leftarrow temp$
\end{effectize}
 
\subsection{SAR}
 
The SAR instruction computes the result of shifting the first 32-bit register operand to the right by a number of bits specified by the 5 least significant bits of the second 32-bit register operand, and replicating the topmost (sign) bit.\\
 
\rrrformat{011100}
 
\begin{effectize}
\effect $shift \leftarrow unsigned(R_{y,4..0})$
\effect $temp_i \leftarrow R_{x,i+shift}$ if $i + shift < 32$
\effect $temp_i \leftarrow R_{x,31}$ if $i + shift \geq 32$
\effect $R_r \leftarrow temp$
\end{effectize}
 
\subsection{SARI}
 
The SARI instruction computes the result of shifting the 32-bit register operand to the right by a number of bits specified by the 5 least significant bits of the immediate operand, and replicating the topmost (sign) bit.\\
 
\rriformat{011101}
 
\begin{effectize}
\effect $shift \leftarrow unsigned(y_{4..0})$
\effect $temp_i \leftarrow R_{x,i+shift}$ if $i + shift < 32$
\effect $temp_i \leftarrow R_{x,31}$ if $i + shift \geq 32$
\effect $R_r \leftarrow temp$
\end{effectize}
 
\subsection{LDHI}
 
The LDHI instruction is used to generate large constants. The upper 16 bits of the result are taken from the 16-bit immediate operand. The lower 16 bits of the result are 0.\\
 
\rriformat{011111}
 
\begin{effectize}
\effect $R_{r,31..16} \leftarrow y_{15..0}$
\effect $R_{r,15..0} \leftarrow 0$
\end{effectize}

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[/] [eco32/] [trunk/] [doc/] [manual/] [isa/] [comp.tex] - Blame information for rev 224

Line No.	Rev	Author	Line
1	22	hellwig	`\section{Computation Instructions}`
2
3			`\newcommand{\rdivzero}{\effect if $R_y=0$ then trigger a \name{Division by Zero Fault}}`
4			`\newcommand{\idivzero}{\effect if $y=0$ then trigger a \name{Division by Zero Fault}}`
5
6			`The computation instructions compute a function of register values and/or immediate values, and store their result in a general-purpose register.`
7
8			`\subsection{ADD}`
9
10			`The ADD instruction computes the sum of two 32-bit register operands, truncated to 32 bits.\\`
11
12			`\rrrformat{000000}`
13
14			`\regeffects{truncate_{32}(R_x + R_y)}`
15
16			`\subsection{ADDI}`
17
18			`The ADDI instruction computes the sum of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\`
19
20			`\rriformat{000001}`
21
22			`\regeffects{truncate_{32}(R_x + signext_{32}(y))}`
23
24			`\subsection{SUB}`
25
26			`The SUB instruction computes the difference of two 32-bit register operands, truncated to 32 bits.\\`
27
28			`\rrrformat{000010}`
29
30			`\regeffects{truncate_{32}(R_x - R_y)}`
31
32			`\subsection{SUBI}`
33
34			`The SUBI instruction computes the difference of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\`
35
36			`\rriformat{000011}`
37
38			`\regeffects{truncate_{32}(R_x - signext_{32}(y))}`
39
40			`\subsection{MUL}`
41
42			`The MUL instruction computes the signed product of two 32-bit register operands, truncated to 32 bits.\\`
43
44			`\rrrformat{000100}`
45
46			`\regeffects{truncate_{32}(R_x *_{signed} R_y)}`
47
48			`\subsection{MULI}`
49
50			`The MULI instruction computes the signed product of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\`
51
52			`\rriformat{000101}`
53
54			`\regeffects{truncate_{32}(R_x *_{signed} signext_{32}(y))}`
55
56			`\subsection{MULU}`
57
58			`The MULU instruction computes the unsigned product of two 32-bit register operands, truncated to 32 bits.\\`
59
60			`\rrrformat{000110}`
61
62			`\regeffects{truncate_{32}(R_x *_{unsigned} R_y)}`
63
64			`\subsection{MULUI}`
65
66			`The MULUI instruction computes the unsigned product of a 32-bit register operand and a zero-extended 16-bit immediate operand, truncated to 32 bits.\\`
67
68			`\rriformat{000111}`
69
70			`\regeffects{truncate_{32}(R_x *_{unsigned} zeroext_{32}(y))}`
71
72			`\subsection{DIV}`
73
74			`The DIV instruction computes the signed quotient of two 32-bit register operands, truncated to 32 bits.\\`
75
76			`\rrrformat{001000}`
77
78			`\begin{effectize}`
79			`\rdivzero`
80			`\regeffect{truncate_{32}(R_x /_{signed} R_y)}`
81			`\end{effectize}`
82
83			`\subsection{DIVI}`
84
85			`The DIVI instruction computes the signed quotient of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\`
86
87			`\rrrformat{001001}`
88
89			`\begin{effectize}`
90			`\idivzero`
91			`\regeffect{truncate_{32}(R_x /_{signed} signext_{32}(y))}`
92			`\end{effectize}`
93
94			`\subsection{DIVU}`
95
96			`The DIVU instruction computes the unsigned quotient of two unsigned 32-bit register operands, truncated to 32 bits.\\`
97
98			`\rrrformat{001010}`
99
100			`\begin{effectize}`
101			`\rdivzero`
102			`\regeffect{truncate_{32}(R_x /_{unsigned} R_y)}`
103			`\end{effectize}`
104
105			`\subsection{DIVUI}`
106
107			`The DIVUI instruction computes the unsigned quotient of a 32-bit register operand and a zero-extended 16-bit immediate operand, truncated to 32 bits.\\`
108
109			`\rrrformat{001011}`
110
111			`\begin{effectize}`
112			`\idivzero`
113			`\regeffect{truncate_{32}(R_x /_{unsigned} zeroext_{32}(y))}`
114			`\end{effectize}`
115
116			`\subsection{REM}`
117
118			`The REM instruction computes the signed remainder of two 32-bit register operands, truncated to 32 bits.\\`
119
120			`\rrrformat{001100}`
121
122			`\begin{effectize}`
123			`\rdivzero`
124			`\regeffect{truncate_{32}(R_x MOD_{signed} R_y)}`
125			`\end{effectize}`
126
127			`\subsection{REMI}`
128
129			`The REMI instruction computes the signed remainder of a 32-bit register operand and a sign-extended 16-bit immediate operand, truncated to 32 bits.\\`
130
131			`\rrrformat{001101}`
132
133			`\begin{effectize}`
134			`\idivzero`
135			`\regeffect{truncate_{32}(R_x MOD_{signed} signext_{32}(y))}`
136			`\end{effectize}`
137
138			`\subsection{REMU}`
139
140			`The REMU instruction computes the unsigned remainder of two unsigned 32-bit register operands, truncated to 32 bits.\\`
141
142			`\rrrformat{001110}`
143
144			`\begin{effectize}`
145			`\rdivzero`
146			`\regeffect{truncate_{32}(R_x MOD_{unsigned} R_y)}`
147			`\end{effectize}`
148
149			`\subsection{REMUI}`
150
151			`The REMUI instruction computes the unsigned remainder of a 32-bit register operand and a zero-extended 16-bit immediate operand, truncated to 32 bits.\\`
152
153			`\rrrformat{001111}`
154
155			`\begin{effectize}`
156			`\idivzero`
157			`\regeffect{truncate_{32}(R_x MOD_{unsigned} zeroext_{32}(y))}`
158			`\end{effectize}`
159
160			`\subsection{AND}`
161
162			`The AND instruction computes the bitwise AND of two 32-bit register operands.\\`
163
164			`\rrrformat{010000}`
165
166			`\bitregeffects{R_{x,i} \wedge R_{y,i}}`
167
168			`\subsection{ANDI}`
169
170			`The ANDI instruction computes the bitwise AND of a 32-bit register operand and a zero-extended 16-bit immediate operand.\\`
171
172			`\rriformat{010001}`
173
174			`\bitregeffects{R_{x,i} \wedge zeroext_{32}(y)_i}`
175
176			`\subsection{OR}`
177
178			`The OR instruction computes the bitwise OR of two 32-bit register operands.\\`
179
180			`\rrrformat{010010}`
181
182			`\bitregeffects{R_{x,i} \vee R_{y,i}}`
183
184			`\subsection{ORI}`
185
186			`The ORI instruction computes the bitwise OR of a 32-bit register operand and a zero-extended 16-bit immediate operand.\\`
187
188			`\rriformat{010011}`
189
190			`\bitregeffects{R_{x,i} \vee zeroext_{32}(y)_i}`
191
192			`\subsection{XOR}`
193
194			`The XOR instruction computes the bitwise XOR of two 32-bit register operands.\\`
195
196			`\rrrformat{010100}`
197
198			`\bitregeffects{R_{x,i} \oplus R_{y,i}}`
199
200			`\subsection{XORI}`
201
202			`The XORI instruction computes the bitwise XOR of a 32-bit register operand and a zero-extended 16-bit immediate operand.\\`
203
204			`\rriformat{010101}`
205
206			`\bitregeffects{R_{x,i} \oplus zeroext_{32}(y)_i}`
207
208			`\subsection{XNOR}`
209
210			`The XNOR instruction computes the bitwise XNOR of two 32-bit register operands.\\`
211
212			`\rrrformat{010110}`
213
214			`\bitregeffects{\overline{R_{x,i} \oplus R_{y,i}}}`
215
216			`\subsection{XNORI}`
217
218			`The XNORI instruction computes the bitwise XNOR of a 32-bit register operand and a zero-extended 16-bit immediate operand.\\`
219
220			`\rriformat{010111}`
221
222			`\bitregeffects{\overline{R_{x,i} \oplus zeroext_{32}(y)_i}}`
223
224			`\subsection{SLL}`
225
226			`The SLL instruction computes the result of shifting the first 32-bit register operand to the left by a number of bits specified by the 5 least significant bits of the second 32-bit register operand, and filling up with 0 bits.\\`
227
228			`\rrrformat{011000}`
229
230			`\begin{effectize}`
231			`\effect $shift \leftarrow unsigned(R_{y,4..0})$`
232			`\effect $temp_i \leftarrow R_{x,i-shift}$ if $i \geq shift$`
233			`\effect $temp_i \leftarrow 0$ if $i < shift$`
234			`\effect $R_r \leftarrow temp$`
235			`\end{effectize}`
236
237			`\subsection{SLLI}`
238
239			`The SLLI instruction computes the result of shifting the 32-bit register operand to the left by a number of bits specified by the 5 least significant bits of the immediate operand, and filling up with 0 bits.\\`
240
241			`\rriformat{011001}`
242
243			`\begin{effectize}`
244			`\effect $shift \leftarrow unsigned(y_{4..0})$`
245			`\effect $temp_i \leftarrow R_{x,i-shift}$ if $i \geq shift$`
246			`\effect $temp_i \leftarrow 0$ if $i < shift$`
247			`\effect $R_r \leftarrow temp$`
248			`\end{effectize}`
249
250			`\subsection{SLR}`
251
252			`The SLR instruction computes the result of shifting the first 32-bit register operand to the right by a number of bits specified by the 5 least significant bits of the second 32-bit register operand, and filling up with 0 bits.\\`
253
254			`\rrrformat{011010}`
255
256			`\begin{effectize}`
257			`\effect $shift \leftarrow unsigned(R_{y,4..0})$`
258			`\effect $temp_i \leftarrow R_{x,i+shift}$ if $i + shift < 32$`
259			`\effect $temp_i \leftarrow 0$ if $i + shift \geq 32$`
260			`\effect $R_r \leftarrow temp$`
261			`\end{effectize}`
262
263			`\subsection{SLRI}`
264
265			`The SLRI instruction computes the result of shifting the 32-bit register operand to the right by a number of bits specified by the 5 least significant bits of the immediate operand, and filling up with 0 bits.\\`
266
267			`\rriformat{011011}`
268
269			`\begin{effectize}`
270			`\effect $shift \leftarrow unsigned(y_{4..0})$`
271			`\effect $temp_i \leftarrow R_{x,i+shift}$ if $i + shift < 32$`
272			`\effect $temp_i \leftarrow 0$ if $i + shift \geq 32$`
273			`\effect $R_r \leftarrow temp$`
274			`\end{effectize}`
275
276			`\subsection{SAR}`
277
278			`The SAR instruction computes the result of shifting the first 32-bit register operand to the right by a number of bits specified by the 5 least significant bits of the second 32-bit register operand, and replicating the topmost (sign) bit.\\`
279
280			`\rrrformat{011100}`
281
282			`\begin{effectize}`
283			`\effect $shift \leftarrow unsigned(R_{y,4..0})$`
284			`\effect $temp_i \leftarrow R_{x,i+shift}$ if $i + shift < 32$`
285			`\effect $temp_i \leftarrow R_{x,31}$ if $i + shift \geq 32$`
286			`\effect $R_r \leftarrow temp$`
287			`\end{effectize}`
288
289			`\subsection{SARI}`
290
291			`The SARI instruction computes the result of shifting the 32-bit register operand to the right by a number of bits specified by the 5 least significant bits of the immediate operand, and replicating the topmost (sign) bit.\\`
292
293			`\rriformat{011101}`
294
295			`\begin{effectize}`
296			`\effect $shift \leftarrow unsigned(y_{4..0})$`
297			`\effect $temp_i \leftarrow R_{x,i+shift}$ if $i + shift < 32$`
298			`\effect $temp_i \leftarrow R_{x,31}$ if $i + shift \geq 32$`
299			`\effect $R_r \leftarrow temp$`
300			`\end{effectize}`
301
302			`\subsection{LDHI}`
303
304			`The LDHI instruction is used to generate large constants. The upper 16 bits of the result are taken from the 16-bit immediate operand. The lower 16 bits of the result are 0.\\`
305
306			`\rriformat{011111}`
307
308			`\begin{effectize}`
309			`\effect $R_{r,31..16} \leftarrow y_{15..0}$`
310			`\effect $R_{r,15..0} \leftarrow 0$`
311			`\end{effectize}`