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hellwig |
\newenvironment{effectize}{Effect: \begin{itemize}}{\end{itemize}}
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\newcommand{\effect}{\item[]}
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\newenvironment{effectblock}{\begin{itemize}}{\end{itemize}}
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\newcommand{\regeffect}[1]{\effect $R_r \leftarrow #1$}
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\newcommand{\regeffects}[1]{\begin{effectize}\regeffect{#1}\end{effectize}}
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\newcommand{\bitregeffect}[1]{\effect $R_{r,i} \leftarrow #1$}
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\newcommand{\bitregeffects}[1]{\begin{effectize}\bitregeffect{#1}\end{effectize}}
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\newcommand{\priveffect}{\effect if $U_C = 1$ then trigger a \name{Privileged Instruction Fault}}
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\newcommand{\rrrformat}[1]{
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Format:
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\begin{tabular}{|c|c|c|c|c|c|}
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\hline
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Bits & 31..26 & 25..21 & 20..16 & 15..11 & 10..0\\
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\hline
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Value & #1 & x & y & r & (ignored)\\
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\hline
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\end{tabular}
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}
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\newcommand{\rriformat}[1]{
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Format:
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\begin{tabular}{|c|c|c|c|c|}
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\hline
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Bits & 31..26 & 25..21 & 20..16 & 15..0\\
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\hline
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Value & #1 & x & r & y\\
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\hline
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\end{tabular}
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}
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\newcommand{\jformat}[1]{
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Format:
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\begin{tabular}{|c|c|c|}
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\hline
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Bits & 31..26 & 25..0\\
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\hline
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Value & #1 & offset\\
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\hline
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\end{tabular}
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}
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\newcommand{\jrformat}[1]{
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Format:
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\begin{tabular}{|c|c|c|c|}
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\hline
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Bits & 31..26 & 25..21 & 20..0\\
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\hline
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Value & #1 & dest & (ignored)\\
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\hline
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\end{tabular}
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}
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\newcommand{\brformat}[1]{
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Format:
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\begin{tabular}{|c|c|c|c|c|}
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\hline
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Bits & 31..26 & 25..21 & 20..16 & 15..0\\
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\hline
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Value & #1 & x & y & offset\\
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\hline
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\end{tabular}
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}
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\newcommand{\ldstformat}[1]{
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Format:
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\begin{tabular}{|c|c|c|c|c|}
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\hline
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Bits & 31..26 & 25..21 & 20..16 & 15..0\\
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\hline
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Value & #1 & x & r & y\\
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\hline
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\end{tabular}
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}
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\newcommand{\noargformat}[1]{
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Format:
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\begin{tabular}{|c|c|c|}
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\hline
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Bits & 31..26 & 25..0\\
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\hline
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Value & #1 & (ignored)\\
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\hline
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\end{tabular}
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}
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\newcommand{\mvspformat}[1]{
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Format:
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\begin{tabular}{|c|c|c|c|c|}
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\hline
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Bits & 31..26 & 25..21 & 20..16 & 15..0\\
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\hline
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Value & #1 & (ignored) & r & z\\
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\hline
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\end{tabular}
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}
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\chapter{Instruction Set}
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The instructions of the \eco operate directly on the functional components described in the previous chapter. They can be subdivided into groups of instructions that work in a similar way:
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\begin{itemize}
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\item {\it Computation}: These instructions compute a function of values stored in general-purpose registers or encoded directly into the instruction and store the result in a general-purpose register.
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\item {\it Control Flow}: These instructions affect the \pc in various ways.
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\item {\it Load/Store}: These instructions transfer data from or to RAM locations or peripheral device registers.
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\item {\it System}: Special instructions for \pswx, \mmux, or exception operation.
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\end{itemize}
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\section{Definitions}
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Some definitions are useful when explaining the effect of an instruction: An \definition{immediate} value is a value encoded directly into the instruction. A \definition{register value} is a 32-bit value taken from a general-purpose register. The interpretation of such values is up to the instruction.
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A register value is referred to by an instruction by an immediate value that denotes the register number. If $x$ is a 5-bit immediate value, then $R_x$ shall denote the corresponding register value, and $R_x \leftarrow ...$ shall denote an assignment to this register. Similarly, $S_i$ denotes special purpose register \#i. $R_{i,j}$ and $S_{i,j}$ denote specific bits of a register. As a special rule, an assignment to $R_0$ has no effect since that register is not writeable.
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\section{General Execution Loop}
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The \eco executes the following loop to perform its task:
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\begin{itemize}
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\item Remember the current value of the \pc register. If any exception occurs before the instruction is finished, this value is placed in register \#30 such that the current instruction can be restarted.
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\item Load the current instruction from the virtual address stored in the \pcx. If that address is not word-aligned, then an \name{Invalid Address Exception} occurs. Otherwise, if it is a privileged address and the CPU is in user mode, then a \name{Privileged Address Exception} occurs. Otherwise, it is mapped to a physical address by the \mmux, which may trigger a \name{TLB Miss Exception} or a \name{TLB Invalid Exception}. All these exceptions cause the faulting \pc value to be stored in the \name{TLB Bad Address Register}. Note that a \name{TLB Write Exception} cannot occur since the instruction fetch is a read access.
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\item Increase the \pc by 4.
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\item If the opcode in the instruction word does not denote a valid instruction, then an \name{Illegal Instruction Fault} is triggered.
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\item Decode and execute the instruction. Any fault triggered during this step immediately stops execution of the current instruction and transfers control to the fault service routine.
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\item Remember the new value of the \pc register. If any interrupt occurs in the next step, this value is placed in register \#30 such that control can return to the next instruction.
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\item Test for interrupts. If an interrupt is signalled and admitted (\myref{2}{ien}), then control is transferred to the service routine (\myref{2}{accept_exception}).
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\end{itemize}
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\input{isa/comp}
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\input{isa/jump}
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\input{isa/ldst}
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\input{isa/system}
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