OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [fp/] [implementation/] [mmix/] [deluxe.mmconfig] - Blame information for rev 168

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 hellwig
% configuration for basic tests --- still under construction
2
memaddresstime 3
3
memreadtime 10 memwritetime 10
4
membusbytes 16
5
branchpredictbits 2
6
branchaddressbits 6
7
branchhistorybits 3
8
branchdualbits 3
9
memchunksmax 100
10
hashprime 127
11
Scache blocksize 64
12
Scache setsize 2048
13
Scache associativity 4 pseudolru
14
Scache accesstime 2
15
Dcache blocksize 32
16
Dcache setsize 512
17
Dcache victimsize 8
18
Icache blocksize 32
19
Icache setsize 256
20
Icache victimsize 4
21
DTcache associativity 4 lru
22
unit BIT1 000000000000000000000000000000000000000000000000ffff00ff00ffc004
23
unit ALU1 00000000ffffffffffffffffffffffff0000000300000003fffffffffffffffe
24
unit ALU2 00000000ffffffffffffffffffffffff0000000300000003fffffffffffffffe
25
unit ALU3 00000000ffffffffffffffffffffffff0000000300000003fffffffffffffffe
26
unit ALU4 00000000ffffffffffffffffffffffff0000000300000003fffffffffffffffe
27
unit ALU5 00000000ffffffffffffffffffffffff0000000300000003fffffffffffffffe
28
unit ALU6 00000000ffffffffffffffffffffffff0000000300000003fffffffffffffffe
29
unit LSU1 00000000000000000000000000000000fffffffcfffffffc0000000000000000
30
unit LSU2 00000000000000000000000000000000fffffffcfffffffc0000000000000000
31
unit LSU3 00000000000000000000000000000000fffffffcfffffffc0000000000000000
32
unit MUL1 000080f000000000000000000000000000000000000000000000000000000000
33
unit DIV1 00000c0f00000000000000000000000000000000000000000000000000000000
34
unit FPU1 7fff730000000000000000000000000000000000000000000000000000000000
35
dispatchmax 3
36
commitmax 3
37
fetchmax 4
38
memslots 8
39
renameregs 20
40
reorderbuffer 40
41
Dcache writeallocate 1
42
Scache writeallocate 1
43
Dcache writeback 1
44
Scache writeback 1
45
Dcache ports 2
46
DTcache ports 2
47
writebuffer 8
48
writeholdingtime 3
49
mul0 1
50
mul1 2
51
mul2 2 2 1
52
mul3 2 2 2 1
53
mul4 2 2 2 2 2
54
mul5 2 2 2 2 2
55
mul6 2 2 2 2 2
56
mul7 2 2 2 2 2
57
mul8 2 2 2 2 2
58
div 10 10 10 10 10 10
59
fadd 1 1 1 1
60
fmul 1 1 1 1
61
fdiv 10 10 10 10
62
fsqrt 10 10 10 10
63
feps 1 1 1 1
64
fix 1 1
65
flot 1 1
66
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.