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[/] [eco32/] [trunk/] [fpga/] [experiments/] [memctrl/] [sim/] [memctrl-0/] [memtest.cfg] - Blame information for rev 312

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Line No. Rev Author Line
1 312 hellwig 
[timestart] 0
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[size] 1280 725
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[pos] -1 -1
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*-16.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] memtest.
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[treeopen] memtest.ramctrl_1.
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@28
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memtest.clk
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memtest.rst_in
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memtest.rst
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@200
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--- INST RD --
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@28
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memtest.inst_stb
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@22
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memtest.inst_addr[25:0]
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memtest.inst_to_cache[63:0]
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@28
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memtest.inst_ack
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memtest.inst_timeout
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@200
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--- DATA RD/WR --
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@28
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memtest.data_stb
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memtest.data_we
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@22
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memtest.data_addr[25:0]
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memtest.data_to_mctrl[63:0]
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memtest.data_to_cache[63:0]
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@28
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memtest.data_ack
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memtest.data_timeout
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@200
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--- TEST RESULT --
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@28
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memtest.test_ended
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memtest.test_error
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@200
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---- RAM CHIP --
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@28
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memtest.ramctrl_1.ram_stb
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memtest.ramctrl_1.ram_we
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@22
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memtest.ramctrl_1.ram_addr[22:0]
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memtest.ramctrl_1.ram_dout[31:0]
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memtest.ramctrl_1.ram_din[31:0]
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@28
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memtest.ramctrl_1.ram_ack

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