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[/] [eco32/] [trunk/] [fpga/] [experiments/] [memctrl/] [sim/] [memctrl-0/] [ramctrl/] [ramctrl.v] - Blame information for rev 312

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//
// ramctrl.v -- RAM controller
//
 
 
`include "ramctrl/ram.v"
 
 
`timescale 1ns/10ps
`default_nettype none
 
 
module ramctrl(clk, rst,
               inst_stb, inst_addr,
               inst_dout, inst_ack,
               inst_timeout,
               data_stb, data_we,
               data_addr, data_din,
               data_dout, data_ack,
               data_timeout);
    input clk;
    input rst;
    input inst_stb;
    input [25:0] inst_addr;
    output [63:0] inst_dout;
    output reg inst_ack;
    output reg inst_timeout;
    input data_stb;
    input data_we;
    input [25:0] data_addr;
    input [63:0] data_din;
    output [63:0] data_dout;
    output reg data_ack;
    output reg data_timeout;
 
  reg ram_stb;
  reg ram_we;
  wire [22:0] ram_addr;
  wire [31:0] ram_dout;
  wire [31:0] ram_din;
  wire ram_ack;
 
  wire inst_addr_out_of_range;
  wire data_addr_out_of_range;
 
  reg ram_as;
  reg ram_a0;
 
  reg ram_ds;
 
  reg [63:0] data;
  reg data_wh;
  reg data_wl;
 
  reg [3:0] state;
  reg [3:0] next_state;
 
  //
  // create ram instance
  //
 
  ram ram_1(
    .clk(clk),
    .rst(rst),
    .stb(ram_stb),
    .we(ram_we),
    .addr(ram_addr[22:0]),
    .data_in(ram_dout[31:0]),
    .data_out(ram_din[31:0]),
    .ack(ram_ack)
  );
 
  //
  // address range check
  //
 
  assign inst_addr_out_of_range = | inst_addr[25:22];
  assign data_addr_out_of_range = | data_addr[25:22];
 
  //
  // address output to ram
  //
 
  assign ram_addr[22:0] =
    ~ram_as ? { inst_addr[21:0], ram_a0 } :
              { data_addr[21:0], ram_a0 };
 
  //
  // data output to ram
  //
 
  assign ram_dout[31:0] =
    ~ram_ds ? data_din[63:32] : data_din[31:0];
 
  //
  // data output to cache
  //
 
  always @(posedge clk) begin
    if (data_wh) begin
      data[63:32] <= ram_din[31:0];
    end
    if (data_wl) begin
      data[31: 0] <= ram_din[31:0];
    end
  end
 
  assign inst_dout[63:0] = data[63:0];
  assign data_dout[63:0] = data[63:0];
 
  //
  // ramctrl state machine
  //
 
  always @(posedge clk) begin
    if (rst) begin
      state <= 0;
    end else begin
      state <= next_state;
    end
  end
 
  always @(*) begin
    case (state)
      4'd0:
        // idle, request arbitration
        begin
          inst_ack = 1'b0;
          inst_timeout = 1'b0;
          data_ack = 1'b0;
          data_timeout = 1'b0;
          ram_stb = 1'b0;
          ram_we = 1'b0;
          ram_as = 1'bx;
          ram_a0 = 1'bx;
          ram_ds = 1'bx;
          data_wh = 1'b0;
          data_wl = 1'b0;
          if (data_stb) begin
            if (data_addr_out_of_range) begin
              // illegal data address
              next_state = 4'd11;
            end else begin
              // data address is ok
              if (data_we) begin
                // data write request
                next_state = 4'd7;
              end else begin
                // data read request
                next_state = 4'd4;
              end
            end
          end else begin
            if (inst_stb) begin
              if (inst_addr_out_of_range) begin
                // illegal inst address
                next_state = 4'd10;
              end else begin
                // inst address is ok
                // inst read request
                next_state = 4'd1;
              end
            end else begin
              // no request
              next_state = 4'd0;
            end
          end
        end
      4'd1:
        // inst read, phase 1
        begin
          inst_ack = 1'b0;
          inst_timeout = 1'b0;
          data_ack = 1'b0;
          data_timeout = 1'b0;
          ram_stb = 1'b1;
          ram_we = 1'b0;
          ram_as = 1'b0;
          ram_a0 = 1'b0;
          ram_ds = 1'bx;
          data_wh = ram_ack;
          data_wl = 1'b0;
          if (ram_ack) begin
            next_state = 4'd2;
          end else begin
            next_state = 4'd1;
          end
        end
      4'd2:
        // inst read, phase 2
        begin
          inst_ack = 1'b0;
          inst_timeout = 1'b0;
          data_ack = 1'b0;
          data_timeout = 1'b0;
          ram_stb = 1'b1;
          ram_we = 1'b0;
          ram_as = 1'b0;
          ram_a0 = 1'b1;
          ram_ds = 1'bx;
          data_wh = 1'b0;
          data_wl = ram_ack;
          if (ram_ack) begin
            next_state = 4'd3;
          end else begin
            next_state = 4'd2;
          end
        end
      4'd3:
        // inst read, phase 3
        begin
          inst_ack = 1'b1;
          inst_timeout = 1'b0;
          data_ack = 1'b0;
          data_timeout = 1'b0;
          ram_stb = 1'b0;
          ram_we = 1'b0;
          ram_as = 1'bx;
          ram_a0 = 1'bx;
          ram_ds = 1'bx;
          data_wh = 1'b0;
          data_wl = 1'b0;
          next_state = 4'd0;
        end
      4'd4:
        // data read, phase 1
        begin
          inst_ack = 1'b0;
          inst_timeout = 1'b0;
          data_ack = 1'b0;
          data_timeout = 1'b0;
          ram_stb = 1'b1;
          ram_we = 1'b0;
          ram_as = 1'b1;
          ram_a0 = 1'b0;
          ram_ds = 1'bx;
          data_wh = ram_ack;
          data_wl = 1'b0;
          if (ram_ack) begin
            next_state = 4'd5;
          end else begin
            next_state = 4'd4;
          end
        end
      4'd5:
        // data read, phase 2
        begin
          inst_ack = 1'b0;
          inst_timeout = 1'b0;
          data_ack = 1'b0;
          data_timeout = 1'b0;
          ram_stb = 1'b1;
          ram_we = 1'b0;
          ram_as = 1'b1;
          ram_a0 = 1'b1;
          ram_ds = 1'bx;
          data_wh = 1'b0;
          data_wl = ram_ack;
          if (ram_ack) begin
            next_state = 4'd6;
          end else begin
            next_state = 4'd5;
          end
        end
      4'd6:
        // data read, phase 3
        begin
          inst_ack = 1'b0;
          inst_timeout = 1'b0;
          data_ack = 1'b1;
          data_timeout = 1'b0;
          ram_stb = 1'b0;
          ram_we = 1'b0;
          ram_as = 1'bx;
          ram_a0 = 1'bx;
          ram_ds = 1'bx;
          data_wh = 1'b0;
          data_wl = 1'b0;
          next_state = 4'd0;
        end
      4'd7:
        // data write, phase 1
        begin
          inst_ack = 1'b0;
          inst_timeout = 1'b0;
          data_ack = 1'b0;
          data_timeout = 1'b0;
          ram_stb = 1'b1;
          ram_we = 1'b1;
          ram_as = 1'b1;
          ram_a0 = 1'b0;
          ram_ds = 1'b0;
          data_wh = 1'b0;
          data_wl = 1'b0;
          if (ram_ack) begin
            next_state = 4'd8;
          end else begin
            next_state = 4'd7;
          end
        end
      4'd8:
        // data write, phase 2
        begin
          inst_ack = 1'b0;
          inst_timeout = 1'b0;
          data_ack = 1'b0;
          data_timeout = 1'b0;
          ram_stb = 1'b1;
          ram_we = 1'b1;
          ram_as = 1'b1;
          ram_a0 = 1'b1;
          ram_ds = 1'b1;
          data_wh = 1'b0;
          data_wl = 1'b0;
          if (ram_ack) begin
            next_state = 4'd9;
          end else begin
            next_state = 4'd8;
          end
        end
      4'd9:
        // data write, phase 3
        begin
          inst_ack = 1'b0;
          inst_timeout = 1'b0;
          data_ack = 1'b1;
          data_timeout = 1'b0;
          ram_stb = 1'b0;
          ram_we = 1'b0;
          ram_as = 1'bx;
          ram_a0 = 1'bx;
          ram_ds = 1'bx;
          data_wh = 1'b0;
          data_wl = 1'b0;
          next_state = 4'd0;
        end
      4'd10:
        // illegal inst address
        begin
          inst_ack = 1'b0;
          inst_timeout = 1'b1;
          data_ack = 1'b0;
          data_timeout = 1'b0;
          ram_stb = 1'b0;
          ram_we = 1'b0;
          ram_as = 1'bx;
          ram_a0 = 1'bx;
          ram_ds = 1'bx;
          data_wh = 1'b0;
          data_wl = 1'b0;
          next_state = 4'd0;
        end
      4'd11:
        // illegal data address
        begin
          inst_ack = 1'b0;
          inst_timeout = 1'b0;
          data_ack = 1'b0;
          data_timeout = 1'b1;
          ram_stb = 1'b0;
          ram_we = 1'b0;
          ram_as = 1'bx;
          ram_a0 = 1'bx;
          ram_ds = 1'bx;
          data_wh = 1'b0;
          data_wl = 1'b0;
          next_state = 4'd0;
        end
      default:
        // not used
        begin
          inst_ack = 1'b0;
          inst_timeout = 1'b0;
          data_ack = 1'b0;
          data_timeout = 1'b0;
          ram_stb = 1'b0;
          ram_we = 1'b0;
          ram_as = 1'bx;
          ram_a0 = 1'bx;
          ram_ds = 1'bx;
          data_wh = 1'b0;
          data_wl = 1'b0;
          next_state = 4'd0;
        end
    endcase
  end
 
endmodule

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[/] [eco32/] [trunk/] [fpga/] [experiments/] [memctrl/] [sim/] [memctrl-0/] [ramctrl/] [ramctrl.v] - Blame information for rev 312

Line No.	Rev	Author	Line
1	312	hellwig	`//`
2			`// ramctrl.v -- RAM controller`
3			`//`
4
5
6			`include "ramctrl/ram.v"
7
8
9			`timescale 1ns/10ps
10			`default_nettype none
11
12
13			`module ramctrl(clk, rst,`
14			`inst_stb, inst_addr,`
15			`inst_dout, inst_ack,`
16			`inst_timeout,`
17			`data_stb, data_we,`
18			`data_addr, data_din,`
19			`data_dout, data_ack,`
20			`data_timeout);`
21			`input clk;`
22			`input rst;`
23			`input inst_stb;`
24			`input [25:0] inst_addr;`
25			`output [63:0] inst_dout;`
26			`output reg inst_ack;`
27			`output reg inst_timeout;`
28			`input data_stb;`
29			`input data_we;`
30			`input [25:0] data_addr;`
31			`input [63:0] data_din;`
32			`output [63:0] data_dout;`
33			`output reg data_ack;`
34			`output reg data_timeout;`
35
36			`reg ram_stb;`
37			`reg ram_we;`
38			`wire [22:0] ram_addr;`
39			`wire [31:0] ram_dout;`
40			`wire [31:0] ram_din;`
41			`wire ram_ack;`
42
43			`wire inst_addr_out_of_range;`
44			`wire data_addr_out_of_range;`
45
46			`reg ram_as;`
47			`reg ram_a0;`
48
49			`reg ram_ds;`
50
51			`reg [63:0] data;`
52			`reg data_wh;`
53			`reg data_wl;`
54
55			`reg [3:0] state;`
56			`reg [3:0] next_state;`
57
58			`//`
59			`// create ram instance`
60			`//`
61
62			`ram ram_1(`
63			`.clk(clk),`
64			`.rst(rst),`
65			`.stb(ram_stb),`
66			`.we(ram_we),`
67			`.addr(ram_addr[22:0]),`
68			`.data_in(ram_dout[31:0]),`
69			`.data_out(ram_din[31:0]),`
70			`.ack(ram_ack)`
71			`);`
72
73			`//`
74			`// address range check`
75			`//`
76
77			`assign inst_addr_out_of_range = \| inst_addr[25:22];`
78			`assign data_addr_out_of_range = \| data_addr[25:22];`
79
80			`//`
81			`// address output to ram`
82			`//`
83
84			`assign ram_addr[22:0] =`
85			`~ram_as ? { inst_addr[21:0], ram_a0 } :`
86			`{ data_addr[21:0], ram_a0 };`
87
88			`//`
89			`// data output to ram`
90			`//`
91
92			`assign ram_dout[31:0] =`
93			`~ram_ds ? data_din[63:32] : data_din[31:0];`
94
95			`//`
96			`// data output to cache`
97			`//`
98
99			`always @(posedge clk) begin`
100			`if (data_wh) begin`
101			`data[63:32] <= ram_din[31:0];`
102			`end`
103			`if (data_wl) begin`
104			`data[31: 0] <= ram_din[31:0];`
105			`end`
106			`end`
107
108			`assign inst_dout[63:0] = data[63:0];`
109			`assign data_dout[63:0] = data[63:0];`
110
111			`//`
112			`// ramctrl state machine`
113			`//`
114
115			`always @(posedge clk) begin`
116			`if (rst) begin`
117			`state <= 0;`
118			`end else begin`
119			`state <= next_state;`
120			`end`
121			`end`
122
123			`always @(*) begin`
124			`case (state)`
125			`4'd0:`
126			`// idle, request arbitration`
127			`begin`
128			`inst_ack = 1'b0;`
129			`inst_timeout = 1'b0;`
130			`data_ack = 1'b0;`
131			`data_timeout = 1'b0;`
132			`ram_stb = 1'b0;`
133			`ram_we = 1'b0;`
134			`ram_as = 1'bx;`
135			`ram_a0 = 1'bx;`
136			`ram_ds = 1'bx;`
137			`data_wh = 1'b0;`
138			`data_wl = 1'b0;`
139			`if (data_stb) begin`
140			`if (data_addr_out_of_range) begin`
141			`// illegal data address`
142			`next_state = 4'd11;`
143			`end else begin`
144			`// data address is ok`
145			`if (data_we) begin`
146			`// data write request`
147			`next_state = 4'd7;`
148			`end else begin`
149			`// data read request`
150			`next_state = 4'd4;`
151			`end`
152			`end`
153			`end else begin`
154			`if (inst_stb) begin`
155			`if (inst_addr_out_of_range) begin`
156			`// illegal inst address`
157			`next_state = 4'd10;`
158			`end else begin`
159			`// inst address is ok`
160			`// inst read request`
161			`next_state = 4'd1;`
162			`end`
163			`end else begin`
164			`// no request`
165			`next_state = 4'd0;`
166			`end`
167			`end`
168			`end`
169			`4'd1:`
170			`// inst read, phase 1`
171			`begin`
172			`inst_ack = 1'b0;`
173			`inst_timeout = 1'b0;`
174			`data_ack = 1'b0;`
175			`data_timeout = 1'b0;`
176			`ram_stb = 1'b1;`
177			`ram_we = 1'b0;`
178			`ram_as = 1'b0;`
179			`ram_a0 = 1'b0;`
180			`ram_ds = 1'bx;`
181			`data_wh = ram_ack;`
182			`data_wl = 1'b0;`
183			`if (ram_ack) begin`
184			`next_state = 4'd2;`
185			`end else begin`
186			`next_state = 4'd1;`
187			`end`
188			`end`
189			`4'd2:`
190			`// inst read, phase 2`
191			`begin`
192			`inst_ack = 1'b0;`
193			`inst_timeout = 1'b0;`
194			`data_ack = 1'b0;`
195			`data_timeout = 1'b0;`
196			`ram_stb = 1'b1;`
197			`ram_we = 1'b0;`
198			`ram_as = 1'b0;`
199			`ram_a0 = 1'b1;`
200			`ram_ds = 1'bx;`
201			`data_wh = 1'b0;`
202			`data_wl = ram_ack;`
203			`if (ram_ack) begin`
204			`next_state = 4'd3;`
205			`end else begin`
206			`next_state = 4'd2;`
207			`end`
208			`end`
209			`4'd3:`
210			`// inst read, phase 3`
211			`begin`
212			`inst_ack = 1'b1;`
213			`inst_timeout = 1'b0;`
214			`data_ack = 1'b0;`
215			`data_timeout = 1'b0;`
216			`ram_stb = 1'b0;`
217			`ram_we = 1'b0;`
218			`ram_as = 1'bx;`
219			`ram_a0 = 1'bx;`
220			`ram_ds = 1'bx;`
221			`data_wh = 1'b0;`
222			`data_wl = 1'b0;`
223			`next_state = 4'd0;`
224			`end`
225			`4'd4:`
226			`// data read, phase 1`
227			`begin`
228			`inst_ack = 1'b0;`
229			`inst_timeout = 1'b0;`
230			`data_ack = 1'b0;`
231			`data_timeout = 1'b0;`
232			`ram_stb = 1'b1;`
233			`ram_we = 1'b0;`
234			`ram_as = 1'b1;`
235			`ram_a0 = 1'b0;`
236			`ram_ds = 1'bx;`
237			`data_wh = ram_ack;`
238			`data_wl = 1'b0;`
239			`if (ram_ack) begin`
240			`next_state = 4'd5;`
241			`end else begin`
242			`next_state = 4'd4;`
243			`end`
244			`end`
245			`4'd5:`
246			`// data read, phase 2`
247			`begin`
248			`inst_ack = 1'b0;`
249			`inst_timeout = 1'b0;`
250			`data_ack = 1'b0;`
251			`data_timeout = 1'b0;`
252			`ram_stb = 1'b1;`
253			`ram_we = 1'b0;`
254			`ram_as = 1'b1;`
255			`ram_a0 = 1'b1;`
256			`ram_ds = 1'bx;`
257			`data_wh = 1'b0;`
258			`data_wl = ram_ack;`
259			`if (ram_ack) begin`
260			`next_state = 4'd6;`
261			`end else begin`
262			`next_state = 4'd5;`
263			`end`
264			`end`
265			`4'd6:`
266			`// data read, phase 3`
267			`begin`
268			`inst_ack = 1'b0;`
269			`inst_timeout = 1'b0;`
270			`data_ack = 1'b1;`
271			`data_timeout = 1'b0;`
272			`ram_stb = 1'b0;`
273			`ram_we = 1'b0;`
274			`ram_as = 1'bx;`
275			`ram_a0 = 1'bx;`
276			`ram_ds = 1'bx;`
277			`data_wh = 1'b0;`
278			`data_wl = 1'b0;`
279			`next_state = 4'd0;`
280			`end`
281			`4'd7:`
282			`// data write, phase 1`
283			`begin`
284			`inst_ack = 1'b0;`
285			`inst_timeout = 1'b0;`
286			`data_ack = 1'b0;`
287			`data_timeout = 1'b0;`
288			`ram_stb = 1'b1;`
289			`ram_we = 1'b1;`
290			`ram_as = 1'b1;`
291			`ram_a0 = 1'b0;`
292			`ram_ds = 1'b0;`
293			`data_wh = 1'b0;`
294			`data_wl = 1'b0;`
295			`if (ram_ack) begin`
296			`next_state = 4'd8;`
297			`end else begin`
298			`next_state = 4'd7;`
299			`end`
300			`end`
301			`4'd8:`
302			`// data write, phase 2`
303			`begin`
304			`inst_ack = 1'b0;`
305			`inst_timeout = 1'b0;`
306			`data_ack = 1'b0;`
307			`data_timeout = 1'b0;`
308			`ram_stb = 1'b1;`
309			`ram_we = 1'b1;`
310			`ram_as = 1'b1;`
311			`ram_a0 = 1'b1;`
312			`ram_ds = 1'b1;`
313			`data_wh = 1'b0;`
314			`data_wl = 1'b0;`
315			`if (ram_ack) begin`
316			`next_state = 4'd9;`
317			`end else begin`
318			`next_state = 4'd8;`
319			`end`
320			`end`
321			`4'd9:`
322			`// data write, phase 3`
323			`begin`
324			`inst_ack = 1'b0;`
325			`inst_timeout = 1'b0;`
326			`data_ack = 1'b1;`
327			`data_timeout = 1'b0;`
328			`ram_stb = 1'b0;`
329			`ram_we = 1'b0;`
330			`ram_as = 1'bx;`
331			`ram_a0 = 1'bx;`
332			`ram_ds = 1'bx;`
333			`data_wh = 1'b0;`
334			`data_wl = 1'b0;`
335			`next_state = 4'd0;`
336			`end`
337			`4'd10:`
338			`// illegal inst address`
339			`begin`
340			`inst_ack = 1'b0;`
341			`inst_timeout = 1'b1;`
342			`data_ack = 1'b0;`
343			`data_timeout = 1'b0;`
344			`ram_stb = 1'b0;`
345			`ram_we = 1'b0;`
346			`ram_as = 1'bx;`
347			`ram_a0 = 1'bx;`
348			`ram_ds = 1'bx;`
349			`data_wh = 1'b0;`
350			`data_wl = 1'b0;`
351			`next_state = 4'd0;`
352			`end`
353			`4'd11:`
354			`// illegal data address`
355			`begin`
356			`inst_ack = 1'b0;`
357			`inst_timeout = 1'b0;`
358			`data_ack = 1'b0;`
359			`data_timeout = 1'b1;`
360			`ram_stb = 1'b0;`
361			`ram_we = 1'b0;`
362			`ram_as = 1'bx;`
363			`ram_a0 = 1'bx;`
364			`ram_ds = 1'bx;`
365			`data_wh = 1'b0;`
366			`data_wl = 1'b0;`
367			`next_state = 4'd0;`
368			`end`
369			`default:`
370			`// not used`
371			`begin`
372			`inst_ack = 1'b0;`
373			`inst_timeout = 1'b0;`
374			`data_ack = 1'b0;`
375			`data_timeout = 1'b0;`
376			`ram_stb = 1'b0;`
377			`ram_we = 1'b0;`
378			`ram_as = 1'bx;`
379			`ram_a0 = 1'bx;`
380			`ram_ds = 1'bx;`
381			`data_wh = 1'b0;`
382			`data_wl = 1'b0;`
383			`next_state = 4'd0;`
384			`end`
385			`endcase`
386			`end`
387
388			`endmodule`