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[/] [eco32/] [trunk/] [fpga/] [experiments/] [memctrl/] [sim/] [memctrl-0/] [ramtest/] [ramtest.v] - Blame information for rev 313

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1 312 hellwig 
//
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// ramtest.v -- RAM test generator
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//
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`timescale 1ns/10ps
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`default_nettype none
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`define SIMULATE
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`define VERBOSE
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`define INST_PERIOD     31
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`define INST_PHASE      19
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`define DATA_PERIOD     17
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`define DATA_PHASE      7
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//
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// memory test generator
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//
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// Algorithm: Three independent address/data generators
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// produce exactly the same sequence of address/data pairs,
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// although at different times: data write, data read, and
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// instruction read. Three out of four data cycles are writes,
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// one is a read. Instruction reads are also less frequent
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// than data writes: 1/31 < 1/17 * 3/4. The writing process
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// is therefore always ahead of the reading processes, with
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// an increasing gap in between.
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//
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module ramtest(clk, rst,
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               inst_stb, inst_addr,
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               inst_din, inst_ack,
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               data_stb, data_we, data_addr,
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               data_dout, data_din, data_ack,
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               test_ended, test_error);
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    input clk;
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    input rst;
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    output reg inst_stb;
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    output [25:0] inst_addr;
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    input [63:0] inst_din;
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    input inst_ack;
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    output reg data_stb;
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    output reg data_we;
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    output [25:0] data_addr;
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    output [63:0] data_dout;
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    input [63:0] data_din;
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    input data_ack;
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    output test_ended;
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    output test_error;
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  reg [4:0] inst_timer;
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  reg [4:0] data_timer;
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  reg [9:0] data_counter;
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  wire ir_next;
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  wire [21:0] ir_a;
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  wire [63:0] ir_d;
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  wire dw_next;
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  wire [21:0] dw_a;
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  wire [63:0] dw_d;
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  wire dr_next;
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  wire [21:0] dr_a;
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  wire [63:0] dr_d;
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`ifdef SIMULATE
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  reg error_1;
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  reg error_3;
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`endif
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  reg error_2;
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  reg error_4;
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  always @(posedge clk) begin
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    if (rst) begin
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      inst_timer <= 0;
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      inst_stb <= 0;
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`ifdef SIMULATE
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      error_1 <= 0;
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`endif
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      error_2 <= 0;
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    end else begin
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      if (~test_ended) begin
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        if (~inst_stb) begin
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          if (inst_timer == `INST_PERIOD - 1) begin
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            inst_timer <= 0;
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          end else begin
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            inst_timer <= inst_timer + 1;
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          end
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          if (inst_timer == `INST_PHASE) begin
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            inst_stb <= 1;
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          end
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        end else begin
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          if (inst_ack) begin
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            inst_stb <= 0;
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`ifdef SIMULATE
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`ifdef VERBOSE
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            $display("%t: inst read  @ 0x%h", $realtime, ir_a);
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            $display("                   value = 0x%h", inst_din);
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`endif
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            if (^inst_din[63:0] === 1'bx) begin
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              $display("Warning: Input data has don't cares at %t",
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                       $realtime);
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              error_1 <= 1;
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            end
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`endif
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            if (inst_din[63:0] != ir_d[63:0]) begin
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              error_2 <= 1;
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            end
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          end
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        end
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      end
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    end
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  end
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  adgen adgen_ir(
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    .clk(clk),
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    .rst(rst),
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    .next(ir_next),
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    .addr(ir_a),
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    .data(ir_d)
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  );
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  assign ir_next = inst_ack;
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  assign inst_addr[25:0] = { 4'h0, ir_a[21:0] };
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  always @(posedge clk) begin
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    if (rst) begin
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      data_timer <= 0;
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      data_stb <= 0;
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      data_we <= 0;
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      data_counter <= 0;
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`ifdef SIMULATE
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      error_3 <= 0;
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`endif
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      error_4 <= 0;
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    end else begin
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      if (~test_ended) begin
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        if (~data_stb) begin
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          if (data_timer == `DATA_PERIOD - 1) begin
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            data_timer <= 0;
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          end else begin
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            data_timer <= data_timer + 1;
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          end
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          if (data_timer == `DATA_PHASE) begin
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            data_stb <= 1;
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            data_we <= ~&data_counter[1:0];
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          end
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        end else begin
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          if (data_ack) begin
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            data_stb <= 0;
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            data_we <= 0;
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            data_counter <= data_counter + 1;
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`ifdef SIMULATE
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`ifdef VERBOSE
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            if (data_we == 1) begin
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              $display("%t: data write @ 0x%h", $realtime, dw_a);
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              $display("                   value = 0x%h", dw_d);
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            end else begin
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              $display("%t: data read  @ 0x%h", $realtime, dr_a);
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              $display("                   value = 0x%h", data_din);
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            end
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`endif
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            if (data_we == 0 &&
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                ^data_din[63:0] === 1'bx) begin
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              $display("Warning: Input data has don't cares at %t",
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                       $realtime);
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              error_3 <= 1;
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            end
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`endif
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            if (data_we == 0 &&
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                data_din[63:0] != dr_d[63:0]) begin
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              error_4 <= 1;
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            end
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          end
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        end
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      end
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    end
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  end
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  adgen adgen_dw(
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    .clk(clk),
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    .rst(rst),
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    .next(dw_next),
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    .addr(dw_a),
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    .data(dw_d)
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  );
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  adgen adgen_dr(
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    .clk(clk),
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    .rst(rst),
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    .next(dr_next),
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    .addr(dr_a),
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    .data(dr_d)
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  );
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  assign dw_next = data_ack & data_we;
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  assign dr_next = data_ack & ~data_we;
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  assign data_addr[25:0] = { 4'h0, data_we ? dw_a[21:0] : dr_a[21:0] };
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  assign data_dout[63:0] = dw_d[63:0];
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  assign test_ended = &data_counter[9:0];
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`ifdef SIMULATE
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  assign test_error = error_1 | error_2 | error_3 | error_4;
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`else
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  assign test_error = error_2 | error_4;
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`endif
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endmodule
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//
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// address & data generator
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//
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// compute pseudo-random 32-bit address
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// and 64-bit data on request
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//
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module adgen(clk, rst,
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             next, addr, data);
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    input clk;
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    input rst;
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    input next;
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    output [21:0] addr;
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    output [63:0] data;
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  reg [31:0] a;
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  reg [63:0] d;
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  always @(posedge clk) begin
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    if (rst) begin
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      a[31: 0] <= 32'hC70337DB;
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      d[63:32] <= 32'h7F4D514F;
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      d[31: 0] <= 32'h75377599;
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    end else begin
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      if (next) begin
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        if (a[0] == 0) begin
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          a[31:0] <= a[31:0] >> 1;
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        end else begin
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          a[31:0] <= (a[31:0] >> 1) ^ 32'hD0000001;
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        end
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        if (d[32] == 0) begin
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          d[63:32] <= d[63:32] >> 1;
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        end else begin
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          d[63:32] <= (d[63:32] >> 1) ^ 32'hD0000001;
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        end
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        if (d[0] == 0) begin
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          d[31:0] <= d[31:0] >> 1;
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        end else begin
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          d[31:0] <= (d[31:0] >> 1) ^ 32'hD0000001;
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        end
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      end
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    end
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  end
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  assign addr[21:0] = a[21:0];
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  assign data[63:0] = d[63:0];
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endmodule

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