URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [fpga/] [experiments/] [memctrl/] [sim/] [memctrl-1/] [memtest.cfg] - Blame information for rev 313

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[timestart] 0
[size] 1280 725
[pos] -1 -1
*-16.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] memtest.
[treeopen] memtest.ramctrl_1.
@28
memtest.clk
memtest.clk_ok
memtest.rst
@200
--- INST RD --
@28
memtest.inst_stb
@22
memtest.inst_addr[25:0]
memtest.inst_to_cache[63:0]
@28
memtest.inst_ack
memtest.inst_timeout
@200
--- DATA RD/WR --
@28
memtest.data_stb
memtest.data_we
@22
memtest.data_addr[25:0]
memtest.data_to_mctrl[63:0]
memtest.data_to_cache[63:0]
@28
memtest.data_ack
memtest.data_timeout
@200
--- TEST RESULT --
@28
memtest.test_ended
memtest.test_error
@200
--- SDRAM CHIP --
@28
memtest.ramctrl_1.sdram_clk
memtest.ramctrl_1.sdram_cke
memtest.ramctrl_1.sdram_cs_n
memtest.ramctrl_1.sdram_ras_n
memtest.ramctrl_1.sdram_cas_n
memtest.ramctrl_1.sdram_we_n
memtest.ramctrl_1.sdram_ba[1:0]
@22
memtest.ramctrl_1.sdram_a[12:0]
@28
memtest.ramctrl_1.sdram_dqm[1:0]
@22
memtest.ramctrl_1.sdram_dq[15:0]
@200
--- SDRAM CTRL --
@28
memtest.ramctrl_1.ram_cnt[1:0]
@22
memtest.ramctrl_1.ram_dout[15:0]
@28
memtest.ramctrl_1.ram_de
@22
memtest.ramctrl_1.data[63:0]
@28
memtest.ramctrl_1.data_ld
memtest.ramctrl_1.ram_cmd[2:0]
@22
memtest.ramctrl_1.count[13:0]
memtest.ramctrl_1.state[4:0]
memtest.ramctrl_1.refcnt[9:0]
@28
memtest.ramctrl_1.refflg
memtest.ramctrl_1.refrst

Line No.	Rev	Author	Line
1	313	hellwig	`[timestart] 0`
2			`[size] 1280 725`
3			`[pos] -1 -1`
4			`*-16.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1`
5			`[treeopen] memtest.`
6			`[treeopen] memtest.ramctrl_1.`
7			`@28`
8			`memtest.clk`
9			`memtest.clk_ok`
10			`memtest.rst`
11			`@200`
12			`--- INST RD --`
13			`@28`
14			`memtest.inst_stb`
15			`@22`
16			`memtest.inst_addr[25:0]`
17			`memtest.inst_to_cache[63:0]`
18			`@28`
19			`memtest.inst_ack`
20			`memtest.inst_timeout`
21			`@200`
22			`--- DATA RD/WR --`
23			`@28`
24			`memtest.data_stb`
25			`memtest.data_we`
26			`@22`
27			`memtest.data_addr[25:0]`
28			`memtest.data_to_mctrl[63:0]`
29			`memtest.data_to_cache[63:0]`
30			`@28`
31			`memtest.data_ack`
32			`memtest.data_timeout`
33			`@200`
34			`--- TEST RESULT --`
35			`@28`
36			`memtest.test_ended`
37			`memtest.test_error`
38			`@200`
39			`--- SDRAM CHIP --`
40			`@28`
41			`memtest.ramctrl_1.sdram_clk`
42			`memtest.ramctrl_1.sdram_cke`
43			`memtest.ramctrl_1.sdram_cs_n`
44			`memtest.ramctrl_1.sdram_ras_n`
45			`memtest.ramctrl_1.sdram_cas_n`
46			`memtest.ramctrl_1.sdram_we_n`
47			`memtest.ramctrl_1.sdram_ba[1:0]`
48			`@22`
49			`memtest.ramctrl_1.sdram_a[12:0]`
50			`@28`
51			`memtest.ramctrl_1.sdram_dqm[1:0]`
52			`@22`
53			`memtest.ramctrl_1.sdram_dq[15:0]`
54			`@200`
55			`--- SDRAM CTRL --`
56			`@28`
57			`memtest.ramctrl_1.ram_cnt[1:0]`
58			`@22`
59			`memtest.ramctrl_1.ram_dout[15:0]`
60			`@28`
61			`memtest.ramctrl_1.ram_de`
62			`@22`
63			`memtest.ramctrl_1.data[63:0]`
64			`@28`
65			`memtest.ramctrl_1.data_ld`
66			`memtest.ramctrl_1.ram_cmd[2:0]`
67			`@22`
68			`memtest.ramctrl_1.count[13:0]`
69			`memtest.ramctrl_1.state[4:0]`
70			`memtest.ramctrl_1.refcnt[9:0]`
71			`@28`
72			`memtest.ramctrl_1.refflg`
73			`memtest.ramctrl_1.refrst`

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Subversion Repositories eco32

[/] [eco32/] [trunk/] [fpga/] [experiments/] [memctrl/] [sim/] [memctrl-1/] [memtest.cfg] - Blame information for rev 313