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/*=============================================================================
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* Copyright(c) Samsung Electronics Co., 1997,1998. All rights reseved.
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*
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* Verilog Behavioral Model of Synchronous 256 SDRAM
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*
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* Description : This is a synchrounous high data rate DRAM,
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* fabricated with SAMSUNG's high performance
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* CMOS technology.
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*
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* Revision No. : V4.5
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* date : Jan. 21. 2002
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*
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*===============================================================================*/
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`define M256
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`define LVTTL
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`define NBANK4
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`define X16
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`define S75
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`define v
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`ifdef LVTTL //M256+G6
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`ifdef X16
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`ifdef S75
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`define tCCmin 7.5 // clock minimum cycle time
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`define tCCmax 1000 // clock maximun cycle time
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`define tCC3 7.5 // clock minimun cycle time at cas latency=3
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`define tCC2 10 // clock minimun cycle time at cas latency=2
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`define tCH 2.5 // clock high pulse width
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`define tCL 2.5 // clock low pulse width
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`define tSS 1.5 // input setup time
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`define tSH 0.8 // input hold time
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`define tRRD 15 // row to row delay(min)
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`define tRCD 20 // ras to cas delay(min)
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`define tRP 20 // row precharge time(min)
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`define tRASmin 45 // row active minimum time
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`define tRASmax 100000 // row active maximum time
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`define tRC 65 // row cycle time(min)
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`define tCCD 7.5 // col. address to col. address delay:
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`define tSAC2 6
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`define tSAC3 5.4
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`define tSHZ2 6
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`define tSHZ3 5.4
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`endif //end of S75
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`ifdef S60
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`define tCCmin 6 // clock minimum cycle time
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`define tCCmax 1000 // clock maximun cycle time
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`define tCC3 6 // clock minimun cycle time at cas latency=3
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`define tCH 2.5 // clock high pulse width
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`define tCL 2.5 // clock low pulse width
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`define tSS 1.5 // input setup time
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`define tSH 1 // input hold time
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`define tRRD 12 // row to row delay(min)
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`define tRCD 18 // ras to cas delay(min)
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`define tRP 18 // row precharge time(min)
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`define tRASmin 42 // row active minimum time
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`define tRASmax 100000 // row active maximum time
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`define tRC 60 // row cycle time(min)
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`define tCCD 6 // col. address to col. address delay:
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`define tSAC3 5
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`define tSHZ3 5
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`endif //end of S60
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`endif //end of X16
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`ifdef X8
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`ifdef S75
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`define tCCmin 7.5 // clock minimum cycle time
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`define tCCmax 1000 // clock maximun cycle time
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`define tCC3 7.5 // clock minimun cycle time at cas latency=3
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`define tCC2 10 // clock minimun cycle time at cas latency=2
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`define tCH 2.5 // clock high pulse width
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`define tCL 2.5 // clock low pulse width
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`define tSS 1.5 // input setup time
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`define tSH 0.8 // input hold time
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`define tRRD 15 // row to row delay(min)
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`define tRCD 20 // ras to cas delay(min)
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`define tRP 20 // row precharge time(min)
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`define tRASmin 45 // row active minimum time
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`define tRASmax 100000 // row active maximum time
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`define tRC 65 // row cycle time(min)
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`define tCCD 7.5 // col. address to col. address delay:
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`define tSAC2 6
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`define tSAC3 5.4
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`define tSHZ2 6
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`define tSHZ3 5.4
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`endif //end of S75
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`endif //end of X8
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`ifdef X4
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`ifdef S75
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`define tCCmin 7.5 // clock minimum cycle time
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`define tCCmax 1000 // clock maximun cycle time
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`define tCC3 7.5 // clock minimun cycle time at cas latency=3
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`define tCC2 10 // clock minimun cycle time at cas latency=2
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`define tCH 2.5 // clock high pulse width
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`define tCL 2.5 // clock low pulse width
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`define tSS 1.5 // input setup time
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`define tSH 0.8 // input hold time
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`define tRRD 15 // row to row delay(min)
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`define tRCD 20 // ras to cas delay(min)
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`define tRP 20 // row precharge time(min)
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`define tRASmin 45 // row active minimum time
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`define tRASmax 100000 // row active maximum time
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`define tRC 65 // row cycle time(min)
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`define tCCD 7.5 // col. address to col. address delay:
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`define tSAC2 6
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`define tSAC3 5.4
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`define tSHZ2 6
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`define tSHZ3 5.4
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`endif //end of S75
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`endif //end of X4
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`endif //end of LVTTL
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/*==================================================================
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* Copyright(c) Samsung Electronics Co., 1997,1998. All rights reseved.
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*
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* Verilog Behavioral Model of Synchronous DRAM
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*
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* Device: - 16M SDRAM(2nd Gen., 3rd Gen., 4th Gen., 5th Gen.)
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* - 64M SDRAM(2nd Gen., 3rd Gen., 4th Gen., 5th Gen.)
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* - 128M SDRAM(1st Gen., 2nd Gen.,)
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* - 256M SDRAM(2nd Gen.)
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*
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* Description : This is a synchrounous high data rate DRAM,
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* fabricated with SAMSUNG's high performance
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* CMOS technology.
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*
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* Developer : Jae-Ha Kim.
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* CAE Team. Semiconductor R&D Centor.
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* Semiconductor Division. Samsung Electronics Co.
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*
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* Revision : Yong-Cheol Bae. ( e-mail: jjbae@samsung.co.kr )
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* 1.0~2.3 DRAM2 Design. Semiconductor R&D Centor.
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* Semiconductor Division. Samsung Electronics Co.
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* Revision : Kyung-Woo Nam. ( e-mail: aboverim@samsung.co.kr )
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* 3.0~ DRAM2 Design. Semiconductor R&D Centor.
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* Semiconductor Division. Samsung Electronics Co.
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*==================================================================
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* Revision No. : V2.3
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* date : Aug. 20. 1997
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* : Oct. 22. 1997
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* : Jan. 15. 1998 - 16M 4Gen. & 64M 3Gen. spec update
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* : Jun. 30. 1998 - 16M 4Gen. & 64M 3Gen. & 2Mx32 &
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* 128M 1Gen. & 256M 2Gen. AC spec update
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* : Oct. 08. 1998 - all-bank precharge revision
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* bank note change: ba0=MSB,ba1=LSB @ 4banks
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* : Nov. 18. 1998 - option set for verbose (e.g. +define+v )
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* 128M 2Gen. AC spec added.
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* conformed model through verilog-XL 2.6.27
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* Revision No. : V3.0
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* date : Apr. 07. 1999 - tRDL=2
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* 1. parameterize auto-precharge address : ADDR_AP
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* 2. divide auto-precharge process read/write
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* 3. divide precharge_flag_kill process normal/read_autopre/write_autopre
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* 4. generate wr_autoprecharge2 process excuting when tRDL=2
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* 5. modify same-bank-autoprecharge-disable function
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* (disable gapless, other bank interrupt case)
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* Revision No. : V3.1
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* date : May. 19. 1999
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* 1. Add 16M 5th Gen. LVTTL(-10,-8,-8.7,-7,-6)
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* 2. Modify 2Mx32 5th Gen. tSAC value
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* Revision No. : V3.2
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* date : Jun. 11. 1999
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* 1. Modify -A AC parameter(64M 5th, 128M 2th, 256M 2th)
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* Revision No. : V3.3
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* date : Jun. 24. 1999
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* 1. After 64MSD3, auto_flagx signal is not used,
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* let auto_flagx be not enabled to device which is after 64MSD3
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* 2. compile new versions
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* verilog-xl : 2.7.17, NC-verilog : 2.1., VCS : 5.0.1a
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* Revision No. : V3.4
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* date : Jul. 12. 1999
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* 1. To prevent roundoff error in AC parameter violation check procedure,
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* define MARGIN paramter. (MARGIN=0.1ns now)
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* Revision No. : V3.5
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* date : Sep. 28. 1999
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* 1. Warning message 'tCCmax violation' is appeared during self refresh operation.
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* When self refresh or precharge-power down, clk can be don't care state. (can stay 'low' or 'high'-level)
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* Therefore tCCmax violation should not be checked during self refresh or prech. power down.
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* Revision No. : V3.6
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* date : Dec. 14. 1999
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* 1. Make MODELSIM version and add partial REF./VREFi change function for NOKIA
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* Revision No. : V3.7
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* date : Jul. 11. 2000
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* 1. Add dynamic memory allocation function using VERILOG-XL PLI,
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* then you must build verilog-XL excutable file containing PLI, and use +define+DYMEM option.
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* Revision No. : V3.8
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* date : Jul. 13. 2000
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* 1. Add 128M SDRAM 3rd/4th Gen., 256M SDRAM 3rd Gen.
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* Revision No. : V3.9
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* date : Feb. 5. 2001
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* 1. remove CL2 parameter at -A, -7,... when violated, error messages are printed.
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* Revision No. : V4.0
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* date : Jun. 11. 2001
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* 1. 128M SDRAM X32 MCP (64M SDRAM X16 7th) parameter added
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* Revision No. : V4.1
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* date : Jun. 23. 2001
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* 1. 256M SDRAM 4th parameters are added
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* Revision No. : V4.2
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* date : Jul. 31. 2001
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* 1. because array of reg is not work at vcs 6.0, change array of reg to real variable (TRAS_PP, TPRE_P)
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* Revision No. : V4.3
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* date : Aug. 09. 2001
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* 1. There is an error that use "<" instead of ">", in tRASmax violation check routine.
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* Revision No. : V4.4
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* date : Oct. 05. 2001
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* 1. Add 128M Mobile SDRAM 5th Gen. (8Mx16, D-die)
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* 2. Add 64M Mobile SDRAM 7th Gen. (2Mx32, F-die)
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* Revision No. : V4.5
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* date : Nov. 23. 2001
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* 1. Add mobile function (EMRS:PASR/TCSR/DSC, DPD:pin/cmd control)
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* Revision No. : V4.6
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* date : Jan. 15. 2002
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* 1. Add 512M SDRAM
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* Revision No. : V4.6
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* date : Aug. 27. 2002
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* 1. Add 128M X32 SDRAM
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* Revision No. : V4.7
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* date : Nov. 25. 2003
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* 1. Add 256M X32 SDRAM
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* 2. Add 512M X32 SDRAM (DDP)
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* 3. Add 512M X16 SDRAM (DDP: 2CS)
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* 4. Add 1GM X4 SDRAM (DDP: 2CS)
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* 5. Add 1GM X8 SDRAM (DDP: 2CS, 2CKE)
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*==================================================================
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*/
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`timescale 1ns / 10ps
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`default_nettype none
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`define K1 1024
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`define M1 1048576
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`define BYTE 8
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`ifdef CS2
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`ifdef DPD_PIN
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module sdram_cs2(clk, csb, cke, ba, ad, rasb, casb, web, dqm, dqi, dpdb);
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`else
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module sdram_cs2(clk, csb, cke, ba, ad, rasb, casb, web, dqm, dqi);
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`endif
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`else
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`ifdef DPD_PIN
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module sdram(clk, csb, cke, ba, ad, rasb, casb, web, dqm, dqi, dpdb);
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`else
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module sdram(clk, csb, cke, ba, ad, rasb, casb, web, dqm, dqi); //default port name
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`endif
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`endif
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`ifdef M16
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`define TBITS 16*`M1
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`define nBank 2
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`define ADDRTOP 10
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`define ADDR_AP 10
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`ifdef G2
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`define M16G2_M641G
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`else
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`define M16G3_M64G2
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`define M64G3_M128_M256
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`endif
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`endif
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`ifdef M64
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`define TBITS 64*`M1
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`define ADDR_AP 10
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`ifdef NBANK2
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`define nBank 2
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`ifdef X32
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`define ADDRTOP 11
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`else
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`define ADDRTOP 12
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`endif
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`endif
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`ifdef NBANK4
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`define nBank 4
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`ifdef X32
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`define ADDRTOP 10
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`else
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`define ADDRTOP 11
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`endif
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`endif
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`define M64_M128_M256 // for prech_reg
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`ifdef G1
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`define M16G2_M641G
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`else
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`ifdef G2
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`define M16G3_M64G2
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`else
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`define M16G4_M64G3
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`define M64G3_M128_M256
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`endif
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`endif
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`endif
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`ifdef M128
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`define TBITS 128*`M1
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`ifdef NBANK4
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`define nBank 4
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`define ADDRTOP 11
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`endif
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`define ADDR_AP 10
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`define M64_M128_M256 // for prech_reg
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`define M128_M256 // RFU, c_addr 10->11
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`define M64G3_M128_M256 // from M64G3
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`define M16G4_M64G3
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`endif
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`ifdef M256
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`define TBITS 256*`M1
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`define nBank 4
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`ifdef X32
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`define ADDRTOP 11
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`else
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|
|
`define ADDRTOP 12
|
| 313 |
|
|
`endif
|
| 314 |
|
|
`define ADDR_AP 10
|
| 315 |
|
|
`define M64_M128_M256 // for prech_reg
|
| 316 |
|
|
`define M128_M256 // RFU, c_addr 10->11
|
| 317 |
|
|
`define M64G3_M128_M256 // from M64G3
|
| 318 |
|
|
`define M16G4_M64G3
|
| 319 |
|
|
`endif
|
| 320 |
|
|
|
| 321 |
|
|
`ifdef M512
|
| 322 |
|
|
`define TBITS 512*`M1
|
| 323 |
|
|
`define nBank 4
|
| 324 |
|
|
`define ADDRTOP 12
|
| 325 |
|
|
`define ADDR_AP 10
|
| 326 |
|
|
`define M64_M128_M256 // for prech_reg
|
| 327 |
|
|
//`define M128_M256 // RFU, c_addr 10->11
|
| 328 |
|
|
`define M64G3_M128_M256 // from M64G3
|
| 329 |
|
|
`define M16G4_M64G3
|
| 330 |
|
|
`endif
|
| 331 |
|
|
|
| 332 |
|
|
`ifdef M1024
|
| 333 |
|
|
`define TBITS 1024*`M1
|
| 334 |
|
|
`define nBank 4
|
| 335 |
|
|
`define ADDRTOP 12
|
| 336 |
|
|
`define ADDR_AP 10
|
| 337 |
|
|
`define M64_M128_M256 // for prech_reg
|
| 338 |
|
|
//`define M128_M256 // RFU, c_addr 10->11
|
| 339 |
|
|
`define M64G3_M128_M256 // from M64G3
|
| 340 |
|
|
`define M16G4_M64G3
|
| 341 |
|
|
`endif
|
| 342 |
|
|
|
| 343 |
|
|
`ifdef M1024
|
| 344 |
|
|
`ifdef X4
|
| 345 |
|
|
`define M512_M1024_X4
|
| 346 |
|
|
`define B 4
|
| 347 |
|
|
`define nCOL 12
|
| 348 |
|
|
`define PAGEDEPTH 4096
|
| 349 |
|
|
`define nDQM 1
|
| 350 |
|
|
`endif
|
| 351 |
|
|
`ifdef X8
|
| 352 |
|
|
`define M512_M1024_X8
|
| 353 |
|
|
`define B 8
|
| 354 |
|
|
`define nCOL 11
|
| 355 |
|
|
`define PAGEDEPTH 2048
|
| 356 |
|
|
`define nDQM 1
|
| 357 |
|
|
`endif
|
| 358 |
|
|
`else
|
| 359 |
|
|
|
| 360 |
|
|
`ifdef M512
|
| 361 |
|
|
`ifdef X4
|
| 362 |
|
|
`define M512_M1024_X4
|
| 363 |
|
|
`define B 4
|
| 364 |
|
|
`define nCOL 12
|
| 365 |
|
|
`define PAGEDEPTH 4096
|
| 366 |
|
|
`define nDQM 1
|
| 367 |
|
|
`endif
|
| 368 |
|
|
`ifdef X8
|
| 369 |
|
|
`define M512_M1024_X8
|
| 370 |
|
|
`define B 8
|
| 371 |
|
|
`define nCOL 11
|
| 372 |
|
|
`define PAGEDEPTH 2048
|
| 373 |
|
|
`define nDQM 1
|
| 374 |
|
|
`endif
|
| 375 |
|
|
`ifdef X16
|
| 376 |
|
|
`define B 16
|
| 377 |
|
|
`ifdef CS2
|
| 378 |
|
|
`define nCOL 9
|
| 379 |
|
|
`define PAGEDEPTH 512
|
| 380 |
|
|
`else
|
| 381 |
|
|
`define nCOL 10
|
| 382 |
|
|
`define PAGEDEPTH 1024
|
| 383 |
|
|
`endif
|
| 384 |
|
|
`define nDQM 2
|
| 385 |
|
|
`endif
|
| 386 |
|
|
`ifdef X32
|
| 387 |
|
|
`define B 32
|
| 388 |
|
|
`define nCOL 9
|
| 389 |
|
|
`define PAGEDEPTH 512
|
| 390 |
|
|
`define nDQM 4
|
| 391 |
|
|
`endif
|
| 392 |
|
|
`else
|
| 393 |
|
|
`ifdef M256
|
| 394 |
|
|
`ifdef X4
|
| 395 |
|
|
`define M128_M256_X4 // 98.6.30 BYC
|
| 396 |
|
|
`define B 4 // number of bit(x4)
|
| 397 |
|
|
`define nCOL 11
|
| 398 |
|
|
`define PAGEDEPTH 2048
|
| 399 |
|
|
`define nDQM 1
|
| 400 |
|
|
`endif
|
| 401 |
|
|
`ifdef X8
|
| 402 |
|
|
`define B 8 // number of bit(x8)
|
| 403 |
|
|
`define nCOL 10
|
| 404 |
|
|
`define PAGEDEPTH 1024
|
| 405 |
|
|
`define nDQM 1
|
| 406 |
|
|
`endif
|
| 407 |
|
|
`ifdef X16
|
| 408 |
|
|
`define B 16 // number of bit(x16)
|
| 409 |
|
|
`define nCOL 9
|
| 410 |
|
|
`define PAGEDEPTH 512
|
| 411 |
|
|
`define nDQM 2
|
| 412 |
|
|
`endif
|
| 413 |
|
|
`ifdef X32
|
| 414 |
|
|
`define B 32 // number of bit(x32)
|
| 415 |
|
|
`define nCOL 9
|
| 416 |
|
|
`define PAGEDEPTH 512
|
| 417 |
|
|
`define nDQM 4
|
| 418 |
|
|
`endif
|
| 419 |
|
|
`else
|
| 420 |
|
|
`ifdef M128
|
| 421 |
|
|
`ifdef X4
|
| 422 |
|
|
`define M128_M256_X4 // 98.6.30 BYC
|
| 423 |
|
|
`define B 4 // number of bit(x4)
|
| 424 |
|
|
`define nCOL 11
|
| 425 |
|
|
`define PAGEDEPTH 2048
|
| 426 |
|
|
`define nDQM 1
|
| 427 |
|
|
`endif
|
| 428 |
|
|
`ifdef X8
|
| 429 |
|
|
`define B 8 // number of bit(x8)
|
| 430 |
|
|
`define nCOL 10
|
| 431 |
|
|
`define PAGEDEPTH 1024
|
| 432 |
|
|
`define nDQM 1
|
| 433 |
|
|
`endif
|
| 434 |
|
|
`ifdef X16
|
| 435 |
|
|
`define B 16 // number of bit(x16)
|
| 436 |
|
|
`define nCOL 9
|
| 437 |
|
|
`define PAGEDEPTH 512
|
| 438 |
|
|
`define nDQM 2
|
| 439 |
|
|
`endif
|
| 440 |
|
|
`ifdef X32
|
| 441 |
|
|
`define B 32 // number of bit(x32)
|
| 442 |
|
|
`define nCOL 8
|
| 443 |
|
|
`define PAGEDEPTH 256
|
| 444 |
|
|
`define nDQM 4
|
| 445 |
|
|
`endif
|
| 446 |
|
|
`else // 64M & 16M
|
| 447 |
|
|
`ifdef X4
|
| 448 |
|
|
`define B 4 // number of bit(x4)
|
| 449 |
|
|
`define nCOL 10
|
| 450 |
|
|
`define PAGEDEPTH 1024
|
| 451 |
|
|
`define nDQM 1
|
| 452 |
|
|
`endif
|
| 453 |
|
|
`ifdef X8
|
| 454 |
|
|
`define B 8 // number of bit(x8)
|
| 455 |
|
|
`define nCOL 9
|
| 456 |
|
|
`define PAGEDEPTH 512
|
| 457 |
|
|
`define nDQM 1
|
| 458 |
|
|
`endif
|
| 459 |
|
|
`ifdef X16
|
| 460 |
|
|
`define B 16 // number of bit(x16)
|
| 461 |
|
|
`define nCOL 8
|
| 462 |
|
|
`define PAGEDEPTH 256
|
| 463 |
|
|
`define nDQM 2
|
| 464 |
|
|
`endif
|
| 465 |
|
|
`ifdef X32
|
| 466 |
|
|
`define B 32 // number of bit(x32)
|
| 467 |
|
|
`define nCOL 8
|
| 468 |
|
|
`define PAGEDEPTH 256
|
| 469 |
|
|
`define nDQM 4
|
| 470 |
|
|
`endif
|
| 471 |
|
|
`endif
|
| 472 |
|
|
`endif
|
| 473 |
|
|
`endif
|
| 474 |
|
|
`endif
|
| 475 |
|
|
|
| 476 |
|
|
`ifdef tCC1
|
| 477 |
|
|
`else
|
| 478 |
|
|
`define NO_CL1
|
| 479 |
|
|
`endif
|
| 480 |
|
|
`ifdef tSAC1
|
| 481 |
|
|
`else
|
| 482 |
|
|
`define NO_CL1
|
| 483 |
|
|
`endif
|
| 484 |
|
|
`ifdef tSHZ1
|
| 485 |
|
|
`else
|
| 486 |
|
|
`define NO_CL1
|
| 487 |
|
|
`endif
|
| 488 |
|
|
`ifdef tCC2
|
| 489 |
|
|
`else
|
| 490 |
|
|
`define NO_CL2
|
| 491 |
|
|
`endif
|
| 492 |
|
|
`ifdef tSAC2
|
| 493 |
|
|
`else
|
| 494 |
|
|
`define NO_CL2
|
| 495 |
|
|
`endif
|
| 496 |
|
|
`ifdef tSHZ2
|
| 497 |
|
|
`else
|
| 498 |
|
|
`define NO_CL2
|
| 499 |
|
|
`endif
|
| 500 |
|
|
`ifdef tCC3
|
| 501 |
|
|
`else
|
| 502 |
|
|
`define NO_CL3
|
| 503 |
|
|
`endif
|
| 504 |
|
|
`ifdef tSAC3
|
| 505 |
|
|
`else
|
| 506 |
|
|
`define NO_CL3
|
| 507 |
|
|
`endif
|
| 508 |
|
|
`ifdef tSHZ3
|
| 509 |
|
|
`else
|
| 510 |
|
|
`define NO_CL3
|
| 511 |
|
|
`endif
|
| 512 |
|
|
|
| 513 |
|
|
`ifdef tRDL
|
| 514 |
|
|
`else
|
| 515 |
|
|
`define tRDL 1
|
| 516 |
|
|
`endif
|
| 517 |
|
|
|
| 518 |
|
|
`ifdef DPD_CMD
|
| 519 |
|
|
`define DPD
|
| 520 |
|
|
`endif
|
| 521 |
|
|
`ifdef DPD_PIN
|
| 522 |
|
|
`define DPD
|
| 523 |
|
|
`endif
|
| 524 |
|
|
|
| 525 |
|
|
`define HB `B/2
|
| 526 |
|
|
`define BIT `B-1:0
|
| 527 |
|
|
`define BIT_C `nCOL-1:0
|
| 528 |
|
|
`define BIT_T `nCOL+`ADDRTOP:0
|
| 529 |
|
|
`define nWORD `TBITS/`B/`nBank
|
| 530 |
|
|
`define WORD `nWORD-1:0
|
| 531 |
|
|
|
| 532 |
|
|
inout [`BIT] dqi;
|
| 533 |
|
|
input [`nBank/2-1:0] ba;
|
| 534 |
|
|
input [`ADDRTOP:0] ad;
|
| 535 |
|
|
input rasb,casb,web;
|
| 536 |
|
|
input clk,cke,csb;
|
| 537 |
|
|
input [`nDQM-1:0] dqm;
|
| 538 |
|
|
`ifdef DPD_PIN
|
| 539 |
|
|
input dpdb;
|
| 540 |
|
|
`endif
|
| 541 |
|
|
|
| 542 |
|
|
/*
|
| 543 |
|
|
`ifdef M64
|
| 544 |
|
|
`include "m64.ac"
|
| 545 |
|
|
`endif
|
| 546 |
|
|
`ifdef M16
|
| 547 |
|
|
`include "m16.ac"
|
| 548 |
|
|
`endif
|
| 549 |
|
|
`ifdef M128
|
| 550 |
|
|
`include "m128.ac"
|
| 551 |
|
|
`endif
|
| 552 |
|
|
`ifdef M256
|
| 553 |
|
|
`include "m256.ac"
|
| 554 |
|
|
`endif
|
| 555 |
|
|
*/
|
| 556 |
|
|
|
| 557 |
|
|
parameter pwrup_time = 200000, pwrup_check = 1;
|
| 558 |
|
|
|
| 559 |
|
|
wire [`nBank/2 + `ADDRTOP : 0] addr;
|
| 560 |
|
|
assign addr = {ba, ad};
|
| 561 |
|
|
|
| 562 |
|
|
wire [`BIT] dqi;
|
| 563 |
|
|
`ifdef DYMEM
|
| 564 |
|
|
initial begin
|
| 565 |
|
|
$damem_declare("mem_a", `B-1, 0, `nWORD-1, 0);
|
| 566 |
|
|
$damem_declare("mem_b", `B-1, 0, `nWORD-1, 0);
|
| 567 |
|
|
end
|
| 568 |
|
|
`else
|
| 569 |
|
|
reg [`BIT] mem_a[`WORD]; // memory cell array of a bank
|
| 570 |
|
|
reg [`BIT] mem_b[`WORD]; // memory cell array of b bank
|
| 571 |
|
|
`endif
|
| 572 |
|
|
`ifdef NBANK4
|
| 573 |
|
|
`ifdef DYMEM
|
| 574 |
|
|
initial begin
|
| 575 |
|
|
$damem_declare("mem_c", `B-1, 0, `nWORD-1, 0);
|
| 576 |
|
|
$damem_declare("mem_d", `B-1, 0, `nWORD-1, 0);
|
| 577 |
|
|
end
|
| 578 |
|
|
`else
|
| 579 |
|
|
reg [`BIT] mem_c[`WORD]; // memory cell array of c bank
|
| 580 |
|
|
reg [`BIT] mem_d[`WORD]; // memory cell array of d bank
|
| 581 |
|
|
`endif
|
| 582 |
|
|
`endif
|
| 583 |
|
|
|
| 584 |
|
|
reg [`BIT] dqo, t_dqo; // output temp. register declaration
|
| 585 |
|
|
reg [`ADDRTOP:0] r_addr_[`nBank-1:0];
|
| 586 |
|
|
reg [`ADDRTOP:0] r_addr;
|
| 587 |
|
|
reg [`BIT_C] c_addr; // column address
|
| 588 |
|
|
reg [`BIT_T] m_addr; // merge row and column address
|
| 589 |
|
|
reg [`BIT] dout_reg[`PAGEDEPTH:0];
|
| 590 |
|
|
reg [`BIT] din_rega[`PAGEDEPTH:0]; // din register for a bank
|
| 591 |
|
|
reg [`BIT] din_regb[`PAGEDEPTH:0]; // din register for b bank
|
| 592 |
|
|
`ifdef NBANK4
|
| 593 |
|
|
reg [`BIT] din_regc[`PAGEDEPTH:0]; // din register for c bank
|
| 594 |
|
|
reg [`BIT] din_regd[`PAGEDEPTH:0]; // din register for d bank
|
| 595 |
|
|
`endif
|
| 596 |
|
|
reg [`BIT] clk_dq;
|
| 597 |
|
|
reg ptr;
|
| 598 |
|
|
|
| 599 |
|
|
reg [`BIT] ZDATA;
|
| 600 |
|
|
reg [7:0] ZBYTE;
|
| 601 |
|
|
|
| 602 |
|
|
|
| 603 |
|
|
// define mode dependency flag
|
| 604 |
|
|
`define INITIAL 0 // no bank precharge
|
| 605 |
|
|
/*
|
| 606 |
|
|
`define IDLE_AB 1 // both bank precharge
|
| 607 |
|
|
`define ACT_A 2 // a bank active and b bank precharge
|
| 608 |
|
|
`define ACT_B 3 // b bank active and a bank precharge
|
| 609 |
|
|
`define ACT_AB 4 // a & b bank active
|
| 610 |
|
|
`define IDLE_A 5 // only a bank prechage
|
| 611 |
|
|
`define IDLE_B 6 // only b bank prechage
|
| 612 |
|
|
*/
|
| 613 |
|
|
|
| 614 |
|
|
`define TRUE 1
|
| 615 |
|
|
`define FALSE 0
|
| 616 |
|
|
`define HIGH 1
|
| 617 |
|
|
`define LOW 0
|
| 618 |
|
|
`define MARGIN 0.1
|
| 619 |
|
|
|
| 620 |
|
|
//parameter pwrup_time = 200000, pwrup_check = 1;
|
| 621 |
|
|
|
| 622 |
|
|
/*
|
| 623 |
|
|
*-----------------------------------------------------
|
| 624 |
|
|
* We know the phase of external signal
|
| 625 |
|
|
* by examining the state of its flag.
|
| 626 |
|
|
*-----------------------------------------------------
|
| 627 |
|
|
*/
|
| 628 |
|
|
|
| 629 |
|
|
reg r_bank_addr; // row bank check flag
|
| 630 |
|
|
reg [`nBank/2-1:0] c_bank_addr; // column bank check flag
|
| 631 |
|
|
reg [`nBank-1:0] auto_flag; // auto precharge flag
|
| 632 |
|
|
reg burst_type, // burst type flag
|
| 633 |
|
|
auto_flagx,
|
| 634 |
|
|
self_flag; // auto & self refresh flag
|
| 635 |
|
|
integer kill_bank, wr_kill_bank, rd_kill_bank;
|
| 636 |
|
|
integer k;
|
| 637 |
|
|
reg [`nBank-1:0] precharge_flag; // precharge each bank check flag
|
| 638 |
|
|
reg [`nBank/2:0] prech_reg; // precharge mode (addr[13:12] && addr[10])
|
| 639 |
|
|
reg [`nBank/2-1:0] rd_autoprech_reg;
|
| 640 |
|
|
reg [`nBank/2-1:0] wr_autoprech_reg;
|
| 641 |
|
|
reg [`nBank/2-1:0] wr_autoprech_reg2;
|
| 642 |
|
|
reg [`nBank/2-1:0] prev_ba; // bank address of previous command
|
| 643 |
|
|
reg pwrup_done;
|
| 644 |
|
|
reg [`nBank-1 : 0] first_pre;
|
| 645 |
|
|
//reg [8*8 : 1] str;
|
| 646 |
|
|
integer auto_cnt;
|
| 647 |
|
|
integer i;
|
| 648 |
|
|
|
| 649 |
|
|
`ifdef M16
|
| 650 |
|
|
wire [3:0] RFU = {addr[11:10], addr[8], addr[7]};
|
| 651 |
|
|
`endif
|
| 652 |
|
|
|
| 653 |
|
|
`ifdef M64
|
| 654 |
|
|
`ifdef NBANK2
|
| 655 |
|
|
wire [3:0] RFU = {addr[11:10], addr[8], addr[7]};
|
| 656 |
|
|
`endif
|
| 657 |
|
|
`ifdef NBANK4
|
| 658 |
|
|
`ifdef X32
|
| 659 |
|
|
wire [4:0] RFU = {addr[12:10], addr[8], addr[7]};
|
| 660 |
|
|
`else
|
| 661 |
|
|
wire [5:0] RFU = {addr[13:10], addr[8], addr[7]};
|
| 662 |
|
|
`endif
|
| 663 |
|
|
`endif
|
| 664 |
|
|
`endif
|
| 665 |
|
|
|
| 666 |
|
|
`ifdef M128
|
| 667 |
|
|
`ifdef NBANK4
|
| 668 |
|
|
wire [5:0] RFU = {addr[13:10], addr[8], addr[7]};
|
| 669 |
|
|
`endif
|
| 670 |
|
|
`endif
|
| 671 |
|
|
|
| 672 |
|
|
`ifdef M256
|
| 673 |
|
|
`ifdef X32
|
| 674 |
|
|
wire [5:0] RFU = {addr[13:10], addr[8], addr[7]};
|
| 675 |
|
|
`else
|
| 676 |
|
|
wire [6:0] RFU = {addr[14:10], addr[8], addr[7]};
|
| 677 |
|
|
`endif
|
| 678 |
|
|
`endif
|
| 679 |
|
|
|
| 680 |
|
|
`ifdef M512 // 98.6.30 BYC
|
| 681 |
|
|
wire [6:0] RFU = {addr[14:10], addr[8], addr[7]};
|
| 682 |
|
|
`endif
|
| 683 |
|
|
|
| 684 |
|
|
`ifdef M1024
|
| 685 |
|
|
wire [6:0] RFU = {addr[14:10], addr[8], addr[7]};
|
| 686 |
|
|
`endif
|
| 687 |
|
|
|
| 688 |
|
|
reg [`nBank-1:0] Mode; // check mode dependency
|
| 689 |
|
|
reg [`nBank-1:0] md;
|
| 690 |
|
|
reg rd_reautoprecharge, wr_reautoprecharge;
|
| 691 |
|
|
`ifdef NOKIA
|
| 692 |
|
|
reg REF16M_MODE, REF32M_MODE;
|
| 693 |
|
|
`endif
|
| 694 |
|
|
`ifdef DPD
|
| 695 |
|
|
`define tDPDEXIT 200000
|
| 696 |
|
|
reg D_POWERDOWN, D_PDOWN_EXIT;
|
| 697 |
|
|
integer PROC_DPDEXIT;
|
| 698 |
|
|
`endif
|
| 699 |
|
|
`ifdef MOBILE
|
| 700 |
|
|
reg REF4BANK, REF2BANK, REF1BANK;
|
| 701 |
|
|
`endif
|
| 702 |
|
|
integer BL, WBL, CL; // burst length & cas latency
|
| 703 |
|
|
real tSHZ; // clk to output in hi-Z
|
| 704 |
|
|
real tSAC; // clk to valid output
|
| 705 |
|
|
reg write_event;//KyW ... 0408 for VCS
|
| 706 |
|
|
|
| 707 |
|
|
event
|
| 708 |
|
|
active, // main operation of SDRAM
|
| 709 |
|
|
modeset,
|
| 710 |
|
|
read,
|
| 711 |
|
|
dqo_event,
|
| 712 |
|
|
write,
|
| 713 |
|
|
flush_write,
|
| 714 |
|
|
precharge,
|
| 715 |
|
|
rd_autoprecharge,
|
| 716 |
|
|
wr_autoprecharge,
|
| 717 |
|
|
wr_autoprecharge2,
|
| 718 |
|
|
precharge_start,
|
| 719 |
|
|
precharge_flag_kill,
|
| 720 |
|
|
wr_precharge_flag_kill,
|
| 721 |
|
|
rd_precharge_flag_kill,
|
| 722 |
|
|
autorefresh,
|
| 723 |
|
|
autostart,
|
| 724 |
|
|
selfrefresh,
|
| 725 |
|
|
`ifdef DPD
|
| 726 |
|
|
deeppowerdown,
|
| 727 |
|
|
d_pdown_exit,
|
| 728 |
|
|
`endif
|
| 729 |
|
|
selfexit;
|
| 730 |
|
|
|
| 731 |
|
|
`protect
|
| 732 |
|
|
|
| 733 |
|
|
// initialize each flag
|
| 734 |
|
|
initial
|
| 735 |
|
|
begin
|
| 736 |
|
|
for (i = 0; i < `nBank; i = i + 1)
|
| 737 |
|
|
auto_flag[i] = `FALSE;
|
| 738 |
|
|
auto_flagx = `FALSE;
|
| 739 |
|
|
rd_reautoprecharge =`FALSE;
|
| 740 |
|
|
wr_reautoprecharge =`FALSE;
|
| 741 |
|
|
self_flag = `FALSE;
|
| 742 |
|
|
pwrup_done = `FALSE;
|
| 743 |
|
|
Mode = `nBank'b0;
|
| 744 |
|
|
|
| 745 |
|
|
for(i = 0; i < `nBank; i = i + 1)
|
| 746 |
|
|
begin
|
| 747 |
|
|
first_pre[i] = `TRUE;
|
| 748 |
|
|
precharge_flag[i] = `FALSE;
|
| 749 |
|
|
end
|
| 750 |
|
|
|
| 751 |
|
|
ZBYTE = 8'bz;
|
| 752 |
|
|
for (i = 0; i < `B; i = i + 1) begin
|
| 753 |
|
|
ZDATA[i] = 1'bz;
|
| 754 |
|
|
end
|
| 755 |
|
|
end
|
| 756 |
|
|
|
| 757 |
|
|
//--------------------------------------------------------------
|
| 758 |
|
|
//--------- TIMING VIOLATION CHECK ROUTINE
|
| 759 |
|
|
//--------------------------------------------------------------
|
| 760 |
|
|
|
| 761 |
|
|
real CUR_TIME, TCKE, TADDR, TRASB, TCASB, TCSB, TWEB, TDQI, TCLK_H, TCLK_L,
|
| 762 |
|
|
TCC_P, pclk_high, last_read, last_rw;
|
| 763 |
|
|
|
| 764 |
|
|
reg [63:0] TDQM[`nDQM-1:0];
|
| 765 |
|
|
|
| 766 |
|
|
//real TRAS_P, TCAS_P, TRASA_P, TRASB_P, TPREA_P, TPREB_P, TSELF, TSEXIT;
|
| 767 |
|
|
// 4 bank
|
| 768 |
|
|
real TRAS_P, TCAS_P, TSELF, TSEXIT;
|
| 769 |
|
|
//reg [63:0] TRAS_PP [`nBank-1:0];
|
| 770 |
|
|
//reg [63:0] TPRE_P [`nBank-1:0];
|
| 771 |
|
|
real TRAS_PP0, TRAS_PP1, TRAS_PP2, TRAS_PP3;
|
| 772 |
|
|
real TPRE_P0, TPRE_P1, TPRE_P2, TPRE_P3;
|
| 773 |
|
|
|
| 774 |
|
|
reg CKE_FLAG, CSB_FLAG, RASB_FLAG, CASB_FLAG, WEB_FLAG;
|
| 775 |
|
|
|
| 776 |
|
|
//event MRS, ACTIVE;
|
| 777 |
|
|
reg MRS_SET, WRITE_MODE, READ_MODE, UNMODE, POWERDOWN_MODE, POWERDOWN_MODE1,//KyW ... 0928 for NOKIA claim
|
| 778 |
|
|
SUSPEND_MODE, AUTOREF_MODE, SELFREF_MODE;
|
| 779 |
|
|
reg PWR, INIT;
|
| 780 |
|
|
|
| 781 |
|
|
|
| 782 |
|
|
`define NOP (RASB_FLAG == `HIGH && CASB_FLAG == `HIGH && WEB_FLAG == `HIGH)
|
| 783 |
|
|
`define NOP1 (RASB_FLAG == `HIGH && CASB_FLAG == `HIGH)
|
| 784 |
|
|
/*
|
| 785 |
|
|
*-----------------------------------------------------
|
| 786 |
|
|
* wire declaration
|
| 787 |
|
|
*-----------------------------------------------------
|
| 788 |
|
|
*/
|
| 789 |
|
|
|
| 790 |
|
|
reg pcke;
|
| 791 |
|
|
reg [`nDQM-1:0] dqm_r;
|
| 792 |
|
|
reg [`nDQM-1:0] dqm_ri;
|
| 793 |
|
|
|
| 794 |
|
|
reg data_read;
|
| 795 |
|
|
reg tdata_read;
|
| 796 |
|
|
reg [`BIT] clkh_dq;
|
| 797 |
|
|
reg [2:0] prev_com;
|
| 798 |
|
|
reg rw_dqm;
|
| 799 |
|
|
reg gapless;
|
| 800 |
|
|
wire pclk = pcke & clk;
|
| 801 |
|
|
wire [2:0] com = {RASB_FLAG, CASB_FLAG, WEB_FLAG};
|
| 802 |
|
|
wire #(TCC_P+0.02) data_read_delay = data_read; // 98.6.29 BYC
|
| 803 |
|
|
`endprotect
|
| 804 |
|
|
|
| 805 |
|
|
`ifdef X32
|
| 806 |
|
|
assign #(tSAC, tSAC, tSHZ) dqi[`B-1:`B-8]= ( data_read & ~dqm_r[3] & ~rw_dqm)?dqo[`B-1:`B-8]:ZBYTE;
|
| 807 |
|
|
assign #(tSAC, tSAC, tSHZ) dqi[`B-9:`B-16] = ( data_read & ~dqm_r[2] & ~rw_dqm)?dqo[`B-9:`B-16]:ZBYTE;
|
| 808 |
|
|
assign #(tSAC, tSAC, tSHZ) dqi[`B-17:`B-24]= ( data_read & ~dqm_r[1] & ~rw_dqm)?dqo[`B-17:`B-24]:ZBYTE;
|
| 809 |
|
|
assign #(tSAC, tSAC, tSHZ) dqi[`B-25:0] = ( data_read & ~dqm_r[0] & ~rw_dqm)?dqo[`B-25:0]:ZBYTE;
|
| 810 |
|
|
`endif
|
| 811 |
|
|
`ifdef X16
|
| 812 |
|
|
assign #(tSAC, tSAC, tSHZ) dqi[`B-1:`B-8]= ( data_read & ~dqm_r[1] & ~rw_dqm)?dqo[`B-1:`B-8]:ZBYTE;
|
| 813 |
|
|
assign #(tSAC, tSAC, tSHZ) dqi[`HB-1:0] = ( data_read & ~dqm_r[0] & ~rw_dqm)?dqo[`B-9:0]:ZBYTE;
|
| 814 |
|
|
`endif
|
| 815 |
|
|
`ifdef X8
|
| 816 |
|
|
assign #(tSAC, tSAC, tSHZ) dqi[`B-1:0] = ( data_read & ~dqm_r & ~rw_dqm)?dqo[`B-1:0]:ZDATA;
|
| 817 |
|
|
`endif
|
| 818 |
|
|
`ifdef X4
|
| 819 |
|
|
assign #(tSAC, tSAC, tSHZ) dqi[`B-1:0] = ( data_read & ~dqm_r & ~rw_dqm)?dqo[`B-1:0]:ZDATA;
|
| 820 |
|
|
`endif
|
| 821 |
|
|
|
| 822 |
|
|
`protect
|
| 823 |
|
|
always @(posedge pclk) begin
|
| 824 |
|
|
pclk_high <= #0.01 $realtime;
|
| 825 |
|
|
clkh_dq <= #0.01 dqi;
|
| 826 |
|
|
end
|
| 827 |
|
|
|
| 828 |
|
|
|
| 829 |
|
|
always @(READ_MODE) begin
|
| 830 |
|
|
// data_read <= repeat(CL-1) @(posedge pclk) READ_MODE;
|
| 831 |
|
|
// VCS does not support above statement. However Verilog-XL is OK.
|
| 832 |
|
|
// So, I modified as following statement for VCS.
|
| 833 |
|
|
#0.1;
|
| 834 |
|
|
if (READ_MODE == 1'b1)
|
| 835 |
|
|
data_read <= repeat(CL-1) @(posedge pclk) 1'b1;
|
| 836 |
|
|
else
|
| 837 |
|
|
data_read <= repeat(CL-1) @(posedge pclk) 1'b0;
|
| 838 |
|
|
end
|
| 839 |
|
|
|
| 840 |
|
|
always @(negedge tdata_read) begin
|
| 841 |
|
|
data_read = tdata_read;
|
| 842 |
|
|
tdata_read = `TRUE;
|
| 843 |
|
|
end
|
| 844 |
|
|
|
| 845 |
|
|
always @(dqo_event)
|
| 846 |
|
|
dqo <= repeat(CL-1) @(posedge pclk) t_dqo;
|
| 847 |
|
|
|
| 848 |
|
|
/*
|
| 849 |
|
|
*-----------------------------------------------------
|
| 850 |
|
|
* setup hold check
|
| 851 |
|
|
*-----------------------------------------------------
|
| 852 |
|
|
*/
|
| 853 |
|
|
|
| 854 |
|
|
initial #0.01 pcke = cke;
|
| 855 |
|
|
|
| 856 |
|
|
initial // time variables initialization
|
| 857 |
|
|
begin
|
| 858 |
|
|
$timeformat(-9, 1, " ns", 10);
|
| 859 |
|
|
TCKE = 0;
|
| 860 |
|
|
TADDR = 0;
|
| 861 |
|
|
TRASB = 0;
|
| 862 |
|
|
TCASB = 0;
|
| 863 |
|
|
TCSB = 0;
|
| 864 |
|
|
TWEB = 0;
|
| 865 |
|
|
TDQI = 0;
|
| 866 |
|
|
TCLK_H = -20;
|
| 867 |
|
|
TCLK_L = -20;
|
| 868 |
|
|
TRAS_P = -200;
|
| 869 |
|
|
TCAS_P = -200;
|
| 870 |
|
|
TSELF = -200;
|
| 871 |
|
|
pclk_high = -20;
|
| 872 |
|
|
last_read = -200;
|
| 873 |
|
|
last_rw = -20;
|
| 874 |
|
|
for (i = 0; i < `nDQM; i = i + 1)
|
| 875 |
|
|
TDQM[i] = 64'b0;
|
| 876 |
|
|
// 4bank
|
| 877 |
|
|
//TRAS_PP[0] = -200;
|
| 878 |
|
|
//TRAS_PP[1] = -200;
|
| 879 |
|
|
//TPRE_P[0] = -200;
|
| 880 |
|
|
//TPRE_P[1] = -200;
|
| 881 |
|
|
TRAS_PP0 = -200;
|
| 882 |
|
|
TRAS_PP1 = -200;
|
| 883 |
|
|
TPRE_P0 = -200;
|
| 884 |
|
|
TPRE_P1 = -200;
|
| 885 |
|
|
`ifdef NBANK4
|
| 886 |
|
|
//TRAS_PP[2] = -200;
|
| 887 |
|
|
//TRAS_PP[3] = -200;
|
| 888 |
|
|
//TPRE_P[2] = -200;
|
| 889 |
|
|
//TPRE_P[3] = -200;
|
| 890 |
|
|
TRAS_PP2 = -200;
|
| 891 |
|
|
TRAS_PP3 = -200;
|
| 892 |
|
|
TPRE_P2 = -200;
|
| 893 |
|
|
TPRE_P3 = -200;
|
| 894 |
|
|
`endif
|
| 895 |
|
|
|
| 896 |
|
|
end
|
| 897 |
|
|
|
| 898 |
|
|
initial // mode register variables initialization
|
| 899 |
|
|
begin
|
| 900 |
|
|
RASB_FLAG = `HIGH;
|
| 901 |
|
|
CASB_FLAG = `HIGH;
|
| 902 |
|
|
CSB_FLAG = `HIGH;
|
| 903 |
|
|
WEB_FLAG = `HIGH;
|
| 904 |
|
|
end
|
| 905 |
|
|
|
| 906 |
|
|
initial // mode register variables initialization
|
| 907 |
|
|
begin
|
| 908 |
|
|
INIT = `TRUE;
|
| 909 |
|
|
MRS_SET = `FALSE;
|
| 910 |
|
|
WRITE_MODE = `FALSE;
|
| 911 |
|
|
READ_MODE = `FALSE;
|
| 912 |
|
|
POWERDOWN_MODE = `FALSE;
|
| 913 |
|
|
POWERDOWN_MODE1 = `FALSE;//KyW ... 0928 for NOKIA claim
|
| 914 |
|
|
SUSPEND_MODE = `FALSE;
|
| 915 |
|
|
AUTOREF_MODE = `FALSE;
|
| 916 |
|
|
SELFREF_MODE = `FALSE;
|
| 917 |
|
|
`ifdef NOKIA
|
| 918 |
|
|
REF16M_MODE = `FALSE;
|
| 919 |
|
|
REF32M_MODE = `FALSE;
|
| 920 |
|
|
`endif
|
| 921 |
|
|
`ifdef MOBILE
|
| 922 |
|
|
REF4BANK = `TRUE;
|
| 923 |
|
|
REF2BANK = `FALSE;
|
| 924 |
|
|
REF1BANK = `FALSE;
|
| 925 |
|
|
`endif
|
| 926 |
|
|
`ifdef DPD
|
| 927 |
|
|
D_POWERDOWN = `FALSE;
|
| 928 |
|
|
D_PDOWN_EXIT = `FALSE;
|
| 929 |
|
|
PROC_DPDEXIT = 0;
|
| 930 |
|
|
`endif
|
| 931 |
|
|
write_event = `FALSE; //KyW ... 0408 for VCS
|
| 932 |
|
|
end
|
| 933 |
|
|
|
| 934 |
|
|
always @(POWERDOWN_MODE) POWERDOWN_MODE1 = #0.1 POWERDOWN_MODE;//KyW ... 0928 for NOKIA claim
|
| 935 |
|
|
|
| 936 |
|
|
always @( posedge clk )
|
| 937 |
|
|
if( PWR == `TRUE )
|
| 938 |
|
|
begin : main
|
| 939 |
|
|
CUR_TIME = $realtime;
|
| 940 |
|
|
|
| 941 |
|
|
if( POWERDOWN_MODE == `TRUE && CKE_FLAG == `TRUE )
|
| 942 |
|
|
begin
|
| 943 |
|
|
if( SELFREF_MODE == `TRUE )
|
| 944 |
|
|
begin
|
| 945 |
|
|
if( CUR_TIME - TSELF < `tRASmin-`MARGIN )
|
| 946 |
|
|
begin
|
| 947 |
|
|
$display("Warning: tRAS violation in self refresh at %t", CUR_TIME);
|
| 948 |
|
|
end
|
| 949 |
|
|
->selfexit;
|
| 950 |
|
|
`ifdef v $display(">> self refresh exit at %t", CUR_TIME);
|
| 951 |
|
|
`endif
|
| 952 |
|
|
`ifdef v // $display(">> power down exit at %t", CUR_TIME);
|
| 953 |
|
|
`endif
|
| 954 |
|
|
POWERDOWN_MODE = `FALSE;
|
| 955 |
|
|
CKE_FLAG = `FALSE;
|
| 956 |
|
|
`endprotect
|
| 957 |
|
|
`ifdef M16G2_M641G
|
| 958 |
|
|
pcke <= repeat (1) @(negedge pclk) cke;
|
| 959 |
|
|
`else
|
| 960 |
|
|
#0 pcke = cke;
|
| 961 |
|
|
`endif
|
| 962 |
|
|
|
| 963 |
|
|
end
|
| 964 |
|
|
`ifdef DPD
|
| 965 |
|
|
else if (D_POWERDOWN == `TRUE)
|
| 966 |
|
|
begin
|
| 967 |
|
|
->d_pdown_exit;
|
| 968 |
|
|
`ifdef v $display(">> deep power down exit at %t", CUR_TIME);
|
| 969 |
|
|
`endif
|
| 970 |
|
|
POWERDOWN_MODE = `FALSE;
|
| 971 |
|
|
CKE_FLAG = `FALSE;
|
| 972 |
|
|
end
|
| 973 |
|
|
`endif
|
| 974 |
|
|
else
|
| 975 |
|
|
begin
|
| 976 |
|
|
`ifdef M16G2_M641G
|
| 977 |
|
|
if (CUR_TIME - TCKE >= `tPDE-`MARGIN)
|
| 978 |
|
|
`else
|
| 979 |
|
|
if( CUR_TIME - TCKE >= `tSS-`MARGIN )
|
| 980 |
|
|
`endif
|
| 981 |
|
|
begin
|
| 982 |
|
|
`ifdef v $display(">> power down exit at %t", CUR_TIME);
|
| 983 |
|
|
`endif
|
| 984 |
|
|
POWERDOWN_MODE = `FALSE;
|
| 985 |
|
|
CKE_FLAG = `FALSE;
|
| 986 |
|
|
pcke <= repeat (1) @(negedge pclk) cke;
|
| 987 |
|
|
end
|
| 988 |
|
|
else
|
| 989 |
|
|
begin
|
| 990 |
|
|
`ifdef M16G2_M641G
|
| 991 |
|
|
$display("Warning: tPDE violation at %t", CUR_TIME);
|
| 992 |
|
|
`else
|
| 993 |
|
|
$display("Warning: tSS Precharge Power Down Exit Setup Violation at %t",CUR_TIME);
|
| 994 |
|
|
`endif
|
| 995 |
|
|
disable main;
|
| 996 |
|
|
end
|
| 997 |
|
|
end
|
| 998 |
|
|
end
|
| 999 |
|
|
|
| 1000 |
|
|
if( POWERDOWN_MODE == `FALSE)
|
| 1001 |
|
|
begin
|
| 1002 |
|
|
if( CUR_TIME - TCKE < `tSS-`MARGIN ) // check cke setup timing
|
| 1003 |
|
|
$display("Warning: CKE setup violation at %t", CUR_TIME);
|
| 1004 |
|
|
else if( cke && SUSPEND_MODE == `TRUE )
|
| 1005 |
|
|
begin
|
| 1006 |
|
|
`ifdef v $display(">> clock suspension exit at %t", CUR_TIME);
|
| 1007 |
|
|
`endif
|
| 1008 |
|
|
SUSPEND_MODE = `FALSE;
|
| 1009 |
|
|
pcke <= @(negedge clk) cke;
|
| 1010 |
|
|
end
|
| 1011 |
|
|
else
|
| 1012 |
|
|
pcke <= @(negedge clk) cke;
|
| 1013 |
|
|
end
|
| 1014 |
|
|
|
| 1015 |
|
|
// clock timing check
|
| 1016 |
|
|
|
| 1017 |
|
|
TCC_P = CUR_TIME - TCLK_H; // saving current clock period
|
| 1018 |
|
|
|
| 1019 |
|
|
if( CUR_TIME - TCLK_H < `tCCmin-`MARGIN && POWERDOWN_MODE1 == `FALSE)//KyW ... 0928 for NOKIA claim
|
| 1020 |
|
|
$display("Warning: tCCmin violation at %t", CUR_TIME);
|
| 1021 |
|
|
|
| 1022 |
|
|
if( CUR_TIME - TCLK_H > `tCCmax+`MARGIN && POWERDOWN_MODE1 == `FALSE)//KyW ... 0928 for NOKIA claim
|
| 1023 |
|
|
$display("Warning: tCCmax violation at %t", CUR_TIME);
|
| 1024 |
|
|
`protect
|
| 1025 |
|
|
if( CUR_TIME - TCLK_L < `tCL-`MARGIN )
|
| 1026 |
|
|
$display("Warning: tCL violation at %t", CUR_TIME);
|
| 1027 |
|
|
|
| 1028 |
|
|
// pcke is high
|
| 1029 |
|
|
if( pcke ) begin
|
| 1030 |
|
|
|
| 1031 |
|
|
// csb timing check
|
| 1032 |
|
|
if( CUR_TIME - TCSB < `tSS-`MARGIN )
|
| 1033 |
|
|
$display("Warning: CSB setup violation at %t", CUR_TIME);
|
| 1034 |
|
|
else // if( CUR_TIME - TCSB < `tCCmin + `tSS-`MARGIN )
|
| 1035 |
|
|
CSB_FLAG = csb;
|
| 1036 |
|
|
|
| 1037 |
|
|
// if chip selected
|
| 1038 |
|
|
if( CSB_FLAG == `LOW )
|
| 1039 |
|
|
begin
|
| 1040 |
|
|
if( CUR_TIME - TRASB < `tSS-`MARGIN )
|
| 1041 |
|
|
$display("Warning: RASB setup violation at %t", CUR_TIME);
|
| 1042 |
|
|
else
|
| 1043 |
|
|
RASB_FLAG = rasb;
|
| 1044 |
|
|
|
| 1045 |
|
|
if( CUR_TIME - TCASB < `tSS-`MARGIN )
|
| 1046 |
|
|
$display("Warning: CASB setup violation at %t", CUR_TIME);
|
| 1047 |
|
|
else
|
| 1048 |
|
|
CASB_FLAG = casb;
|
| 1049 |
|
|
|
| 1050 |
|
|
if( CUR_TIME - TWEB < `tSS-`MARGIN )
|
| 1051 |
|
|
$display("Warning: WEB setup violation at %t", CUR_TIME);
|
| 1052 |
|
|
else
|
| 1053 |
|
|
WEB_FLAG = web;
|
| 1054 |
|
|
|
| 1055 |
|
|
end
|
| 1056 |
|
|
for (i = 0; i < `nDQM; i = i + 1) begin
|
| 1057 |
|
|
if( CUR_TIME - $bitstoreal(TDQM[i]) < `tSS-`MARGIN )
|
| 1058 |
|
|
$display("Warning: DQM(%d) setup violation at %t", i, CUR_TIME);
|
| 1059 |
|
|
else begin
|
| 1060 |
|
|
// dqm_r[i] <= @(posedge pclk) dqm[i];
|
| 1061 |
|
|
// VCS does not support above statement. However Verilog-XL is OK.
|
| 1062 |
|
|
// So, I modified as following statement for VCS.
|
| 1063 |
|
|
dqm_r[i] <= dqm_ri[i];
|
| 1064 |
|
|
dqm_ri[i] <= dqm[i];
|
| 1065 |
|
|
end
|
| 1066 |
|
|
end
|
| 1067 |
|
|
end
|
| 1068 |
|
|
|
| 1069 |
|
|
TCLK_H = CUR_TIME; // the time clock is high
|
| 1070 |
|
|
|
| 1071 |
|
|
end
|
| 1072 |
|
|
|
| 1073 |
|
|
/*------------------------------------------
|
| 1074 |
|
|
* command recognition
|
| 1075 |
|
|
*------------------------------------------
|
| 1076 |
|
|
*/
|
| 1077 |
|
|
|
| 1078 |
|
|
always @( posedge pclk )
|
| 1079 |
|
|
if( PWR == `TRUE )
|
| 1080 |
|
|
begin : command
|
| 1081 |
|
|
integer bank_id;
|
| 1082 |
|
|
reg [8*8:1] str;
|
| 1083 |
|
|
|
| 1084 |
|
|
if( CSB_FLAG == `LOW )
|
| 1085 |
|
|
begin : command_sel
|
| 1086 |
|
|
if( auto_cnt == -1 )
|
| 1087 |
|
|
begin
|
| 1088 |
|
|
if( ~ `NOP ) // NOP1 -> NOP because of burst stop
|
| 1089 |
|
|
$display("Warning: NOP required during power-up pause time.");
|
| 1090 |
|
|
disable command_sel;
|
| 1091 |
|
|
end
|
| 1092 |
|
|
|
| 1093 |
|
|
if( CUR_TIME - TADDR < `tSS-`MARGIN )
|
| 1094 |
|
|
$display("Warning: Address setup violation at %t", CUR_TIME);
|
| 1095 |
|
|
|
| 1096 |
|
|
if( `NOP ) // deleted by burst stop -> NOP1 -> NOP
|
| 1097 |
|
|
disable command_sel;
|
| 1098 |
|
|
|
| 1099 |
|
|
if( AUTOREF_MODE == `TRUE || SELFREF_MODE == `TRUE )
|
| 1100 |
|
|
begin
|
| 1101 |
|
|
$display("Warning: Illegal command in refresh operation at %t", CUR_TIME);
|
| 1102 |
|
|
disable command_sel;
|
| 1103 |
|
|
end
|
| 1104 |
|
|
`ifdef DPD
|
| 1105 |
|
|
if (D_POWERDOWN == `TRUE) begin
|
| 1106 |
|
|
$display("Warning: Illegal command in deep power down exit at %t", CUR_TIME);
|
| 1107 |
|
|
disable command_sel;
|
| 1108 |
|
|
end
|
| 1109 |
|
|
if (D_PDOWN_EXIT) begin
|
| 1110 |
|
|
if (PROC_DPDEXIT == 0) begin
|
| 1111 |
|
|
if ({RASB_FLAG,CASB_FLAG,WEB_FLAG} == 3'b010) begin
|
| 1112 |
|
|
`ifdef M64_M128_M256
|
| 1113 |
|
|
`ifdef NBANK2
|
| 1114 |
|
|
prech_reg[1] = ba;
|
| 1115 |
|
|
prech_reg[0] = addr[`ADDR_AP];
|
| 1116 |
|
|
`endif
|
| 1117 |
|
|
`ifdef NBANK4
|
| 1118 |
|
|
prech_reg[2] = ba[1];
|
| 1119 |
|
|
prech_reg[1] = ba[0];
|
| 1120 |
|
|
prech_reg[0] = addr[`ADDR_AP];
|
| 1121 |
|
|
`endif
|
| 1122 |
|
|
`endif
|
| 1123 |
|
|
PROC_DPDEXIT = 1;
|
| 1124 |
|
|
->precharge;
|
| 1125 |
|
|
end
|
| 1126 |
|
|
else $display("Warning: all bank precharge required to complete deep power down mode exit.");
|
| 1127 |
|
|
end
|
| 1128 |
|
|
else if (PROC_DPDEXIT == 1 || PROC_DPDEXIT == 2) begin
|
| 1129 |
|
|
if ({cke,RASB_FLAG,CASB_FLAG,WEB_FLAG} == 4'b1001) begin
|
| 1130 |
|
|
PROC_DPDEXIT = PROC_DPDEXIT + 1;
|
| 1131 |
|
|
->autorefresh;
|
| 1132 |
|
|
end
|
| 1133 |
|
|
else $display("Warning: 2 or more auto refresh required to complete deep power down mode exit.");
|
| 1134 |
|
|
end
|
| 1135 |
|
|
else if (PROC_DPDEXIT == 3) begin
|
| 1136 |
|
|
if ({RASB_FLAG,CASB_FLAG,WEB_FLAG} == 3'b000) begin
|
| 1137 |
|
|
D_PDOWN_EXIT = `FALSE;
|
| 1138 |
|
|
PROC_DPDEXIT = 0;
|
| 1139 |
|
|
->modeset;
|
| 1140 |
|
|
end
|
| 1141 |
|
|
else if ({cke,RASB_FLAG,CASB_FLAG,WEB_FLAG} == 4'b1001) begin
|
| 1142 |
|
|
->autorefresh;
|
| 1143 |
|
|
end
|
| 1144 |
|
|
else $display("Warning: Mode register set required to complete deep power down mode exit.");
|
| 1145 |
|
|
end
|
| 1146 |
|
|
end
|
| 1147 |
|
|
|
| 1148 |
|
|
`endif
|
| 1149 |
|
|
if( ~pwrup_done )
|
| 1150 |
|
|
if( auto_cnt < 2 )
|
| 1151 |
|
|
begin
|
| 1152 |
|
|
case ( {RASB_FLAG,CASB_FLAG,WEB_FLAG} )
|
| 1153 |
|
|
'b010 :
|
| 1154 |
|
|
begin
|
| 1155 |
|
|
`ifdef M64_M128_M256
|
| 1156 |
|
|
`ifdef NBANK2
|
| 1157 |
|
|
prech_reg[1] = ba;
|
| 1158 |
|
|
prech_reg[0] = addr[`ADDR_AP];
|
| 1159 |
|
|
`endif
|
| 1160 |
|
|
`ifdef NBANK4
|
| 1161 |
|
|
prech_reg[2] = ba[1];
|
| 1162 |
|
|
prech_reg[1] = ba[0];
|
| 1163 |
|
|
prech_reg[0] = addr[`ADDR_AP];
|
| 1164 |
|
|
`endif
|
| 1165 |
|
|
`endif
|
| 1166 |
|
|
`ifdef M16
|
| 1167 |
|
|
prech_reg = addr[11:10];
|
| 1168 |
|
|
`endif
|
| 1169 |
|
|
->precharge;
|
| 1170 |
|
|
end
|
| 1171 |
|
|
'b001 :
|
| 1172 |
|
|
if( cke )
|
| 1173 |
|
|
begin
|
| 1174 |
|
|
auto_cnt = auto_cnt + 1;
|
| 1175 |
|
|
->autorefresh;
|
| 1176 |
|
|
end
|
| 1177 |
|
|
'b000 :
|
| 1178 |
|
|
begin
|
| 1179 |
|
|
if( MRS_SET == `TRUE )
|
| 1180 |
|
|
->modeset;
|
| 1181 |
|
|
else if( INIT == `TRUE )
|
| 1182 |
|
|
begin
|
| 1183 |
|
|
->modeset;
|
| 1184 |
|
|
INIT = `FALSE;
|
| 1185 |
|
|
end
|
| 1186 |
|
|
else
|
| 1187 |
|
|
$display("Warning: MODE register set need 2 clock cycles at %t", CUR_TIME);
|
| 1188 |
|
|
end
|
| 1189 |
|
|
|
| 1190 |
|
|
default: begin
|
| 1191 |
|
|
$display("Warning: 2 or more auto-refresh required during power up sequence.");
|
| 1192 |
|
|
end
|
| 1193 |
|
|
endcase
|
| 1194 |
|
|
disable command_sel;
|
| 1195 |
|
|
end
|
| 1196 |
|
|
else
|
| 1197 |
|
|
pwrup_done = `TRUE;
|
| 1198 |
|
|
|
| 1199 |
|
|
case( {RASB_FLAG,CASB_FLAG,WEB_FLAG} )
|
| 1200 |
|
|
'b000 :
|
| 1201 |
|
|
begin
|
| 1202 |
|
|
if( MRS_SET == `TRUE )
|
| 1203 |
|
|
->modeset;
|
| 1204 |
|
|
else if( INIT == `TRUE )
|
| 1205 |
|
|
begin
|
| 1206 |
|
|
->modeset;
|
| 1207 |
|
|
INIT = `FALSE;
|
| 1208 |
|
|
end
|
| 1209 |
|
|
else
|
| 1210 |
|
|
$display("Warning: MODE register set need 2 clock cycles at %t", CUR_TIME);
|
| 1211 |
|
|
end
|
| 1212 |
|
|
'b011 : // active
|
| 1213 |
|
|
begin
|
| 1214 |
|
|
if( MRS_SET == `TRUE )
|
| 1215 |
|
|
begin
|
| 1216 |
|
|
bank_id = BankSelect(ba);
|
| 1217 |
|
|
str = PrintBank(ba);
|
| 1218 |
|
|
if(Mode[bank_id] == `TRUE)
|
| 1219 |
|
|
$display("Warning: Illegal active (%0s is not precharged) at %t",str,CUR_TIME);
|
| 1220 |
|
|
|
| 1221 |
|
|
else
|
| 1222 |
|
|
->active;
|
| 1223 |
|
|
end
|
| 1224 |
|
|
|
| 1225 |
|
|
else if( INIT == `FALSE )
|
| 1226 |
|
|
$display("Warning: MODE register set need 2 clock cycles at %t",CUR_TIME);
|
| 1227 |
|
|
else if( INIT == `TRUE )
|
| 1228 |
|
|
$display("Warning: Initial MODE register set must be required before active at %t",CUR_TIME);
|
| 1229 |
|
|
end
|
| 1230 |
|
|
`endprotect
|
| 1231 |
|
|
'b101 :
|
| 1232 |
|
|
begin // read command
|
| 1233 |
|
|
bank_id = BankSelect(ba);
|
| 1234 |
|
|
str = PrintBank(ba);
|
| 1235 |
|
|
gapless = (pclk_high == last_rw && auto_flag[bank_id]) ?
|
| 1236 |
|
|
`TRUE : `FALSE;
|
| 1237 |
|
|
`ifdef M16G4_M64G3
|
| 1238 |
|
|
if (precharge_flag[bank_id])
|
| 1239 |
|
|
begin
|
| 1240 |
|
|
$display("Warning: Illegal command in precharge operation at %t",CUR_TIME);
|
| 1241 |
|
|
disable command_sel;
|
| 1242 |
|
|
end
|
| 1243 |
|
|
`else
|
| 1244 |
|
|
if( auto_flagx )
|
| 1245 |
|
|
begin
|
| 1246 |
|
|
$display("Warning: Illegal command in auto-precharge command at %t",CUR_TIME);
|
| 1247 |
|
|
disable command_sel;
|
| 1248 |
|
|
end
|
| 1249 |
|
|
`endif
|
| 1250 |
|
|
else if( Mode[bank_id] == `TRUE)
|
| 1251 |
|
|
begin
|
| 1252 |
|
|
if( READ_MODE == `TRUE)
|
| 1253 |
|
|
begin
|
| 1254 |
|
|
`ifdef M64G3_M128_M256
|
| 1255 |
|
|
if (auto_flag[prev_ba] == `TRUE && prev_ba != bank_id) begin
|
| 1256 |
|
|
rd_autoprech_reg = prev_ba;
|
| 1257 |
|
|
->rd_autoprecharge;
|
| 1258 |
|
|
end
|
| 1259 |
|
|
`endif
|
| 1260 |
|
|
READ_MODE = `FALSE;
|
| 1261 |
|
|
#0 disable read_block;
|
| 1262 |
|
|
end
|
| 1263 |
|
|
if( WRITE_MODE == `TRUE)
|
| 1264 |
|
|
begin
|
| 1265 |
|
|
`ifdef M64G3_M128_M256
|
| 1266 |
|
|
if (auto_flag[prev_ba] == `TRUE && prev_ba != bank_id) begin
|
| 1267 |
|
|
//`ifdef RDL2
|
| 1268 |
|
|
if (`tRDL == 2) begin
|
| 1269 |
|
|
wr_autoprech_reg2 = prev_ba;
|
| 1270 |
|
|
->wr_autoprecharge2;
|
| 1271 |
|
|
end
|
| 1272 |
|
|
//`else
|
| 1273 |
|
|
else begin
|
| 1274 |
|
|
wr_autoprech_reg = prev_ba;
|
| 1275 |
|
|
->wr_autoprecharge;
|
| 1276 |
|
|
end
|
| 1277 |
|
|
//`endif
|
| 1278 |
|
|
end
|
| 1279 |
|
|
`endif
|
| 1280 |
|
|
WRITE_MODE = `FALSE;
|
| 1281 |
|
|
disable write_block;
|
| 1282 |
|
|
end
|
| 1283 |
|
|
last_read = CUR_TIME;
|
| 1284 |
|
|
prev_com = {RASB_FLAG,CASB_FLAG,WEB_FLAG};
|
| 1285 |
|
|
prev_ba = ba;
|
| 1286 |
|
|
rw_dqm <= `FALSE;
|
| 1287 |
|
|
#0 ->read;
|
| 1288 |
|
|
end
|
| 1289 |
|
|
|
| 1290 |
|
|
else
|
| 1291 |
|
|
$display("Warning: Illegal read (%0s is not active) at %t",str,CUR_TIME);
|
| 1292 |
|
|
end
|
| 1293 |
|
|
'b100 :
|
| 1294 |
|
|
begin // write command
|
| 1295 |
|
|
bank_id = BankSelect(ba);
|
| 1296 |
|
|
str = PrintBank(ba);
|
| 1297 |
|
|
if (prev_com == 3'b101) begin
|
| 1298 |
|
|
if (clkh_dq !== `B'bz && data_read_delay == 1'b1) // 98.6.29 BYC
|
| 1299 |
|
|
$display("Warning: HIZ should be issued 1 cycle before write op at %t", CUR_TIME);
|
| 1300 |
|
|
end
|
| 1301 |
|
|
`ifdef M16G2_M641G
|
| 1302 |
|
|
`else
|
| 1303 |
|
|
gapless = (pclk_high == last_rw && auto_flag[bank_id])
|
| 1304 |
|
|
? `TRUE : `FALSE;
|
| 1305 |
|
|
`endif
|
| 1306 |
|
|
`ifdef M16G4_M64G3
|
| 1307 |
|
|
if (precharge_flag[bank_id])
|
| 1308 |
|
|
begin
|
| 1309 |
|
|
$display("Warning: Illegal command in precharge operation at %t",CUR_TIME);
|
| 1310 |
|
|
disable command_sel;
|
| 1311 |
|
|
end
|
| 1312 |
|
|
`else
|
| 1313 |
|
|
if( auto_flagx )
|
| 1314 |
|
|
begin
|
| 1315 |
|
|
$display("Warning: Illegal command in auto-precharge command at %t",CUR_TIME);
|
| 1316 |
|
|
disable command_sel;
|
| 1317 |
|
|
end
|
| 1318 |
|
|
`endif
|
| 1319 |
|
|
`protect
|
| 1320 |
|
|
else if( Mode[bank_id] == `TRUE)
|
| 1321 |
|
|
begin
|
| 1322 |
|
|
if( READ_MODE == `TRUE )
|
| 1323 |
|
|
begin
|
| 1324 |
|
|
`ifdef M64G3_M128_M256
|
| 1325 |
|
|
if (auto_flag[prev_ba] == `TRUE && prev_ba != bank_id) begin
|
| 1326 |
|
|
rd_autoprech_reg = prev_ba;
|
| 1327 |
|
|
->rd_autoprecharge;
|
| 1328 |
|
|
end
|
| 1329 |
|
|
`endif
|
| 1330 |
|
|
READ_MODE = `FALSE;
|
| 1331 |
|
|
tdata_read <= @(posedge pclk) READ_MODE; // 3.2
|
| 1332 |
|
|
#0 disable read_block;
|
| 1333 |
|
|
end
|
| 1334 |
|
|
if( WRITE_MODE == `TRUE )
|
| 1335 |
|
|
begin
|
| 1336 |
|
|
`ifdef M64G3_M128_M256
|
| 1337 |
|
|
if (auto_flag[prev_ba] == `TRUE && prev_ba != bank_id) begin
|
| 1338 |
|
|
//`ifdef RDL2
|
| 1339 |
|
|
if (`tRDL == 2) begin
|
| 1340 |
|
|
wr_autoprech_reg2 = prev_ba;
|
| 1341 |
|
|
->wr_autoprecharge2;
|
| 1342 |
|
|
end
|
| 1343 |
|
|
//`else
|
| 1344 |
|
|
else begin
|
| 1345 |
|
|
wr_autoprech_reg = prev_ba;
|
| 1346 |
|
|
->wr_autoprecharge;
|
| 1347 |
|
|
end
|
| 1348 |
|
|
//`endif
|
| 1349 |
|
|
end
|
| 1350 |
|
|
`endif
|
| 1351 |
|
|
WRITE_MODE = `FALSE;
|
| 1352 |
|
|
disable write_block;
|
| 1353 |
|
|
end
|
| 1354 |
|
|
if( |dqm === 1'b0 ) begin // 98.6.26 BYC
|
| 1355 |
|
|
if( CUR_TIME - TDQI < `tSS-`MARGIN )
|
| 1356 |
|
|
$display("Warning: DQi setup violation at %t", CUR_TIME);
|
| 1357 |
|
|
end
|
| 1358 |
|
|
prev_com = {RASB_FLAG,CASB_FLAG,WEB_FLAG};
|
| 1359 |
|
|
prev_ba = ba;
|
| 1360 |
|
|
if (pclk_high == last_read)
|
| 1361 |
|
|
rw_dqm <= @(negedge pclk) `TRUE;
|
| 1362 |
|
|
//#0 ->write;
|
| 1363 |
|
|
write_event <= `TRUE; //KyW ... 0408 for VCS
|
| 1364 |
|
|
write_event <= #0.1 `FALSE; //KyW ... 0408 for VCS
|
| 1365 |
|
|
end
|
| 1366 |
|
|
else
|
| 1367 |
|
|
$display("Warning: Illegal write ( %0s is not active) at %t",str,CUR_TIME);
|
| 1368 |
|
|
|
| 1369 |
|
|
end
|
| 1370 |
|
|
'b110 : // burst stop
|
| 1371 |
|
|
`ifdef DPD
|
| 1372 |
|
|
if( cke === 1'b0 )
|
| 1373 |
|
|
->deeppowerdown;
|
| 1374 |
|
|
else if (cke === 1'b1)
|
| 1375 |
|
|
`endif
|
| 1376 |
|
|
begin
|
| 1377 |
|
|
`ifdef v $display ("Burst stop");
|
| 1378 |
|
|
`endif
|
| 1379 |
|
|
|
| 1380 |
|
|
|
| 1381 |
|
|
if( READ_MODE == `TRUE )
|
| 1382 |
|
|
begin
|
| 1383 |
|
|
READ_MODE = `FALSE;
|
| 1384 |
|
|
`ifdef v $display("-- reading burst stop at %t", CUR_TIME);
|
| 1385 |
|
|
`endif
|
| 1386 |
|
|
disable read_block;
|
| 1387 |
|
|
end
|
| 1388 |
|
|
else if( WRITE_MODE == `TRUE)
|
| 1389 |
|
|
begin
|
| 1390 |
|
|
// at this clock, writing done
|
| 1391 |
|
|
`ifdef v $display("-- writing burst stop at %t", CUR_TIME);
|
| 1392 |
|
|
`endif
|
| 1393 |
|
|
`ifdef M16G2_M641G
|
| 1394 |
|
|
WRITE_MODE = @(negedge pclk) `FALSE;
|
| 1395 |
|
|
`else
|
| 1396 |
|
|
WRITE_MODE = `FALSE;
|
| 1397 |
|
|
`endif
|
| 1398 |
|
|
disable write_block;
|
| 1399 |
|
|
end
|
| 1400 |
|
|
prev_com = {RASB_FLAG,CASB_FLAG,WEB_FLAG};
|
| 1401 |
|
|
end
|
| 1402 |
|
|
'b010 :
|
| 1403 |
|
|
begin
|
| 1404 |
|
|
`endprotect
|
| 1405 |
|
|
`ifdef M16G4_M64G3 //KyW ... 0624 : rev 3.3
|
| 1406 |
|
|
`else
|
| 1407 |
|
|
if(auto_flagx == `TRUE && (addr[`ADDR_AP] || ba == c_bank_addr))
|
| 1408 |
|
|
begin
|
| 1409 |
|
|
$display("Warning: Illegal command in auto-precharge command at %t",CUR_TIME);
|
| 1410 |
|
|
disable command_sel;
|
| 1411 |
|
|
end
|
| 1412 |
|
|
`endif
|
| 1413 |
|
|
`ifdef M64_M128_M256
|
| 1414 |
|
|
`ifdef NBANK2
|
| 1415 |
|
|
prech_reg[1] = ba;
|
| 1416 |
|
|
prech_reg[0] = addr[`ADDR_AP];
|
| 1417 |
|
|
`endif
|
| 1418 |
|
|
`ifdef NBANK4
|
| 1419 |
|
|
prech_reg[2] = ba[1];
|
| 1420 |
|
|
prech_reg[1] = ba[0];
|
| 1421 |
|
|
prech_reg[0] = addr[`ADDR_AP];
|
| 1422 |
|
|
`endif
|
| 1423 |
|
|
`endif
|
| 1424 |
|
|
`ifdef M16
|
| 1425 |
|
|
prech_reg = addr[11:10];
|
| 1426 |
|
|
`endif
|
| 1427 |
|
|
->precharge;
|
| 1428 |
|
|
end
|
| 1429 |
|
|
`protect
|
| 1430 |
|
|
'b001 : begin
|
| 1431 |
|
|
if( cke )
|
| 1432 |
|
|
->autorefresh;
|
| 1433 |
|
|
else if( ~cke )
|
| 1434 |
|
|
->selfrefresh;
|
| 1435 |
|
|
end
|
| 1436 |
|
|
// default :
|
| 1437 |
|
|
`ifdef v // $display("- NOP");
|
| 1438 |
|
|
`endif
|
| 1439 |
|
|
endcase
|
| 1440 |
|
|
end // command_sel
|
| 1441 |
|
|
|
| 1442 |
|
|
// TCLK_H = CUR_TIME; // the time clock is high
|
| 1443 |
|
|
end
|
| 1444 |
|
|
|
| 1445 |
|
|
`ifdef DPD_PIN
|
| 1446 |
|
|
always @(negedge dpdb)
|
| 1447 |
|
|
if (dpdb === 1'b0) ->deeppowerdown;
|
| 1448 |
|
|
else begin
|
| 1449 |
|
|
`ifdef v $display("Warning: Invalid dpdb pin state at %t", CUR_TIME);
|
| 1450 |
|
|
`endif
|
| 1451 |
|
|
end
|
| 1452 |
|
|
always @(posedge dpdb)
|
| 1453 |
|
|
if (dpdb === 1'b1) begin
|
| 1454 |
|
|
if (D_POWERDOWN == `TRUE)
|
| 1455 |
|
|
begin
|
| 1456 |
|
|
->d_pdown_exit;
|
| 1457 |
|
|
`ifdef v $display(">> deep power down exit at %t", CUR_TIME);
|
| 1458 |
|
|
`endif
|
| 1459 |
|
|
POWERDOWN_MODE = `FALSE;
|
| 1460 |
|
|
CKE_FLAG = `FALSE;
|
| 1461 |
|
|
end
|
| 1462 |
|
|
end
|
| 1463 |
|
|
else begin
|
| 1464 |
|
|
`ifdef v $display("Warning: Invalid dpdb pin state at %t", CUR_TIME);
|
| 1465 |
|
|
`endif
|
| 1466 |
|
|
end
|
| 1467 |
|
|
`endif
|
| 1468 |
|
|
|
| 1469 |
|
|
// power down or supend enter mode
|
| 1470 |
|
|
always @( posedge pclk )
|
| 1471 |
|
|
if( POWERDOWN_MODE == `FALSE && cke == `LOW && CUR_TIME - TCKE >= `tSS-`MARGIN )
|
| 1472 |
|
|
begin
|
| 1473 |
|
|
if( |Mode == 1'b0 ) //BYC
|
| 1474 |
|
|
begin
|
| 1475 |
|
|
`ifdef v $display(">> power down enter at %t",CUR_TIME);
|
| 1476 |
|
|
`endif
|
| 1477 |
|
|
POWERDOWN_MODE = `TRUE;
|
| 1478 |
|
|
end
|
| 1479 |
|
|
else
|
| 1480 |
|
|
begin
|
| 1481 |
|
|
`ifdef v $display(">> clock suspension enter at %t",CUR_TIME);
|
| 1482 |
|
|
`endif
|
| 1483 |
|
|
SUSPEND_MODE = `TRUE;
|
| 1484 |
|
|
end
|
| 1485 |
|
|
end
|
| 1486 |
|
|
|
| 1487 |
|
|
// clock width check
|
| 1488 |
|
|
always @( negedge clk )
|
| 1489 |
|
|
if( PWR == `TRUE )
|
| 1490 |
|
|
begin
|
| 1491 |
|
|
CUR_TIME = $realtime;
|
| 1492 |
|
|
if( CUR_TIME - TCLK_H < `tCH-`MARGIN )
|
| 1493 |
|
|
$display("Warning: tCH violation at %t", CUR_TIME);
|
| 1494 |
|
|
TCLK_L = CUR_TIME;
|
| 1495 |
|
|
end
|
| 1496 |
|
|
|
| 1497 |
|
|
// hold time check
|
| 1498 |
|
|
always @(cke)
|
| 1499 |
|
|
begin
|
| 1500 |
|
|
CUR_TIME = $realtime;
|
| 1501 |
|
|
if( PWR == `TRUE )
|
| 1502 |
|
|
if( POWERDOWN_MODE == `FALSE && CUR_TIME - TCLK_H < `tSH-`MARGIN )
|
| 1503 |
|
|
$display("Warning: CKE hold violation at %t", CUR_TIME);
|
| 1504 |
|
|
else if( POWERDOWN_MODE == `TRUE && cke == `HIGH )
|
| 1505 |
|
|
CKE_FLAG = `TRUE;
|
| 1506 |
|
|
|
| 1507 |
|
|
TCKE = CUR_TIME;
|
| 1508 |
|
|
end
|
| 1509 |
|
|
|
| 1510 |
|
|
|
| 1511 |
|
|
always @(addr) //posedge addr or negedge addr )
|
| 1512 |
|
|
begin
|
| 1513 |
|
|
CUR_TIME = $realtime;
|
| 1514 |
|
|
if( PWR == `TRUE && CSB_FLAG == `LOW && pcke == `HIGH )
|
| 1515 |
|
|
if( CUR_TIME - TCLK_H < `tSH-`MARGIN )
|
| 1516 |
|
|
$display("Warning: Address hold violation at %t", CUR_TIME);
|
| 1517 |
|
|
TADDR = CUR_TIME;
|
| 1518 |
|
|
end
|
| 1519 |
|
|
|
| 1520 |
|
|
always @( negedge rasb or posedge rasb)
|
| 1521 |
|
|
begin
|
| 1522 |
|
|
CUR_TIME = $realtime;
|
| 1523 |
|
|
if( PWR == `TRUE && CSB_FLAG == `LOW )
|
| 1524 |
|
|
if( pcke == `HIGH && CUR_TIME - TCLK_H < `tSH-`MARGIN )
|
| 1525 |
|
|
$display("Warning: RASB hold violation at %t", CUR_TIME);
|
| 1526 |
|
|
if(rasb)
|
| 1527 |
|
|
RASB_FLAG = `HIGH;
|
| 1528 |
|
|
TRASB = CUR_TIME;
|
| 1529 |
|
|
end
|
| 1530 |
|
|
|
| 1531 |
|
|
always @( negedge casb or posedge casb)
|
| 1532 |
|
|
begin
|
| 1533 |
|
|
CUR_TIME = $realtime;
|
| 1534 |
|
|
if( PWR == `TRUE && CSB_FLAG == `LOW )
|
| 1535 |
|
|
if( pcke == `HIGH && CUR_TIME - TCLK_H < `tSH-`MARGIN )
|
| 1536 |
|
|
$display("Warning: CASB hold violation at %t", CUR_TIME);
|
| 1537 |
|
|
if(casb)
|
| 1538 |
|
|
CASB_FLAG = `HIGH;
|
| 1539 |
|
|
TCASB = CUR_TIME;
|
| 1540 |
|
|
end
|
| 1541 |
|
|
|
| 1542 |
|
|
always @( negedge csb or posedge csb)
|
| 1543 |
|
|
begin
|
| 1544 |
|
|
CUR_TIME = $realtime;
|
| 1545 |
|
|
if( csb )
|
| 1546 |
|
|
CSB_FLAG <= #(CUR_TIME - TCLK_H + `tSH) csb;
|
| 1547 |
|
|
if( PWR == `TRUE && pcke == `HIGH && CUR_TIME - TCLK_H < `tSH-`MARGIN )
|
| 1548 |
|
|
$display("Warning: CSB hold violation at %t", CUR_TIME);
|
| 1549 |
|
|
TCSB = CUR_TIME;
|
| 1550 |
|
|
end
|
| 1551 |
|
|
|
| 1552 |
|
|
always @( negedge web or posedge web)
|
| 1553 |
|
|
begin
|
| 1554 |
|
|
CUR_TIME = $realtime;
|
| 1555 |
|
|
if( PWR == `TRUE && CSB_FLAG == `LOW )
|
| 1556 |
|
|
if( pcke == `HIGH && CUR_TIME - TCLK_H < `tSH-`MARGIN )
|
| 1557 |
|
|
$display("Warning: WEB hold violation at %t", CUR_TIME);
|
| 1558 |
|
|
if(web)
|
| 1559 |
|
|
WEB_FLAG = `HIGH;
|
| 1560 |
|
|
else
|
| 1561 |
|
|
WEB_FLAG = `LOW;
|
| 1562 |
|
|
TWEB = CUR_TIME;
|
| 1563 |
|
|
end
|
| 1564 |
|
|
|
| 1565 |
|
|
always @(dqi)
|
| 1566 |
|
|
begin
|
| 1567 |
|
|
if( WRITE_MODE )
|
| 1568 |
|
|
begin
|
| 1569 |
|
|
CUR_TIME = $realtime;
|
| 1570 |
|
|
if( CUR_TIME - TCLK_H < `tSH-`MARGIN )
|
| 1571 |
|
|
$display("Warning: DQi hold violation at %t", CUR_TIME);
|
| 1572 |
|
|
end
|
| 1573 |
|
|
TDQI = $realtime;
|
| 1574 |
|
|
end
|
| 1575 |
|
|
|
| 1576 |
|
|
always @(dqm) begin
|
| 1577 |
|
|
CUR_TIME = $realtime;
|
| 1578 |
|
|
if (PWR == `TRUE)
|
| 1579 |
|
|
for (i = 0; i < `nDQM; i = i + 1) begin
|
| 1580 |
|
|
if (CUR_TIME - TCLK_H < `tSH-`MARGIN && pcke == `HIGH)
|
| 1581 |
|
|
$display("Warning: DQM(%d) hold violation at %t", i, CUR_TIME);
|
| 1582 |
|
|
TDQM[i] = $realtobits(CUR_TIME);
|
| 1583 |
|
|
end
|
| 1584 |
|
|
end
|
| 1585 |
|
|
|
| 1586 |
|
|
|
| 1587 |
|
|
/*
|
| 1588 |
|
|
*-----------------------------------------------------
|
| 1589 |
|
|
* power up check routine
|
| 1590 |
|
|
*-----------------------------------------------------
|
| 1591 |
|
|
*/
|
| 1592 |
|
|
|
| 1593 |
|
|
initial
|
| 1594 |
|
|
begin
|
| 1595 |
|
|
auto_cnt = -1;
|
| 1596 |
|
|
PWR = `FALSE;
|
| 1597 |
|
|
if(pwrup_check)
|
| 1598 |
|
|
fork
|
| 1599 |
|
|
@(posedge clk or negedge clk) PWR <= #0 `TRUE;
|
| 1600 |
|
|
begin
|
| 1601 |
|
|
#pwrup_time auto_cnt = 0;
|
| 1602 |
|
|
Mode = `INITIAL;
|
| 1603 |
|
|
end
|
| 1604 |
|
|
join
|
| 1605 |
|
|
else
|
| 1606 |
|
|
begin
|
| 1607 |
|
|
@(posedge clk or negedge clk);
|
| 1608 |
|
|
auto_cnt = 2;
|
| 1609 |
|
|
pwrup_done = `TRUE;
|
| 1610 |
|
|
PWR <= #0 `TRUE;
|
| 1611 |
|
|
`ifdef v $display("-- power up check routine skipped");
|
| 1612 |
|
|
`endif
|
| 1613 |
|
|
end
|
| 1614 |
|
|
end
|
| 1615 |
|
|
|
| 1616 |
|
|
/*
|
| 1617 |
|
|
*-----------------------------------------------------
|
| 1618 |
|
|
* MRS(mode register set)
|
| 1619 |
|
|
*-----------------------------------------------------
|
| 1620 |
|
|
*/
|
| 1621 |
|
|
|
| 1622 |
|
|
always @(modeset)
|
| 1623 |
|
|
begin : mrs_op
|
| 1624 |
|
|
if( &precharge_flag == 1'b1)
|
| 1625 |
|
|
begin
|
| 1626 |
|
|
$display("Warning: Illegal command in precharge operation at %t", CUR_TIME);
|
| 1627 |
|
|
disable mrs_op;
|
| 1628 |
|
|
end
|
| 1629 |
|
|
|
| 1630 |
|
|
if (|Mode == 1'b0)
|
| 1631 |
|
|
$display(">> MODE register set at %t", CUR_TIME);
|
| 1632 |
|
|
else
|
| 1633 |
|
|
begin
|
| 1634 |
|
|
$display("Warning: Illegal MRS command at %t",CUR_TIME);
|
| 1635 |
|
|
disable mrs_op;
|
| 1636 |
|
|
end
|
| 1637 |
|
|
|
| 1638 |
|
|
// mode initialization
|
| 1639 |
|
|
MRS_SET = `FALSE;
|
| 1640 |
|
|
|
| 1641 |
|
|
begin
|
| 1642 |
|
|
if(~|RFU)
|
| 1643 |
|
|
begin // {
|
| 1644 |
|
|
case(addr[2:0]) // burst length programming
|
| 1645 |
|
|
3'b000:begin
|
| 1646 |
|
|
BL = 1;
|
| 1647 |
|
|
WBL = 1;
|
| 1648 |
|
|
$display("-- burst length = 1");
|
| 1649 |
|
|
end
|
| 1650 |
|
|
3'b001:begin
|
| 1651 |
|
|
BL = 2;
|
| 1652 |
|
|
WBL = 2;
|
| 1653 |
|
|
$display("-- burst length = 2");
|
| 1654 |
|
|
end
|
| 1655 |
|
|
3'b010:begin
|
| 1656 |
|
|
BL = 4;
|
| 1657 |
|
|
WBL = 4;
|
| 1658 |
|
|
$display("-- burst length = 4");
|
| 1659 |
|
|
end
|
| 1660 |
|
|
3'b011:begin
|
| 1661 |
|
|
BL = 8;
|
| 1662 |
|
|
WBL = 8;
|
| 1663 |
|
|
$display("-- burst length = 8");
|
| 1664 |
|
|
end
|
| 1665 |
|
|
3'b111:begin // added
|
| 1666 |
|
|
BL = `PAGEDEPTH;
|
| 1667 |
|
|
WBL = `PAGEDEPTH;
|
| 1668 |
|
|
$display("-- burst length = %d", `PAGEDEPTH);
|
| 1669 |
|
|
end
|
| 1670 |
|
|
default $display("Warning: Invalid Burst length!");
|
| 1671 |
|
|
endcase
|
| 1672 |
|
|
`endprotect
|
| 1673 |
|
|
|
| 1674 |
|
|
if(addr[3] && BL != `PAGEDEPTH) // burst type programming
|
| 1675 |
|
|
begin
|
| 1676 |
|
|
burst_type = 1'b1;
|
| 1677 |
|
|
$display("-- burst type = interleave.");
|
| 1678 |
|
|
end
|
| 1679 |
|
|
else
|
| 1680 |
|
|
begin
|
| 1681 |
|
|
`ifdef M16G4_M64G3 // jhkim(8.14)
|
| 1682 |
|
|
if (addr[3] && BL == `PAGEDEPTH) begin
|
| 1683 |
|
|
$display("Warning: interleave mode does not support Full page Mode");
|
| 1684 |
|
|
$display(" interleave mode will be changed to sequential mode");
|
| 1685 |
|
|
end
|
| 1686 |
|
|
`endif
|
| 1687 |
|
|
burst_type = 1'b0;
|
| 1688 |
|
|
$display("-- burst type = sequential.");
|
| 1689 |
|
|
end
|
| 1690 |
|
|
|
| 1691 |
|
|
case(addr[6:4]) // CAS latency programming
|
| 1692 |
|
|
3'b001:begin
|
| 1693 |
|
|
`ifdef NO_CL1
|
| 1694 |
|
|
$display("Warning: cas latency 1 is not supported in 16M 4Gen. & 64M 3 Gen.");
|
| 1695 |
|
|
`else
|
| 1696 |
|
|
tSAC = `tSAC1; CL=1; tSHZ = `tSHZ1;
|
| 1697 |
|
|
if( TCC_P < `tCC1-`MARGIN )
|
| 1698 |
|
|
$display("Warning: clock minimun cycle violation at cas latency=1");
|
| 1699 |
|
|
$display("-- cas latency = 1");
|
| 1700 |
|
|
`endif
|
| 1701 |
|
|
end
|
| 1702 |
|
|
3'b010:begin
|
| 1703 |
|
|
`ifdef NO_CL2 //KyW
|
| 1704 |
|
|
$display("Warning: cas latency 2 is not supported in this device.");
|
| 1705 |
|
|
`else
|
| 1706 |
|
|
tSAC = `tSAC2; CL=2; tSHZ = `tSHZ2;
|
| 1707 |
|
|
if( TCC_P < `tCC2-`MARGIN )
|
| 1708 |
|
|
$display("Warning: clock minimun cycle violation at cas latency=2");
|
| 1709 |
|
|
$display("-- cas latency = 2");
|
| 1710 |
|
|
`endif
|
| 1711 |
|
|
end
|
| 1712 |
|
|
3'b011:begin
|
| 1713 |
|
|
`ifdef NO_CL3 //KyW
|
| 1714 |
|
|
$display("Warning: cas latency 3 is not supported in this device.");
|
| 1715 |
|
|
`else
|
| 1716 |
|
|
tSAC = `tSAC3; CL=3; tSHZ = `tSHZ3;
|
| 1717 |
|
|
if( TCC_P < `tCC3-`MARGIN )
|
| 1718 |
|
|
$display("Warning: clock minimun cycle violation at cas latency=3");
|
| 1719 |
|
|
$display("-- cas latency = 3");
|
| 1720 |
|
|
`endif
|
| 1721 |
|
|
end
|
| 1722 |
|
|
default $display("Warning: Invalid CAS latency!");
|
| 1723 |
|
|
endcase
|
| 1724 |
|
|
|
| 1725 |
|
|
if(addr[9])
|
| 1726 |
|
|
begin
|
| 1727 |
|
|
$display("-- Burst read single bit write mode");
|
| 1728 |
|
|
WBL = 1;
|
| 1729 |
|
|
end
|
| 1730 |
|
|
`ifdef NOKIA
|
| 1731 |
|
|
REF16M_MODE = `FALSE;
|
| 1732 |
|
|
REF32M_MODE = `FALSE;
|
| 1733 |
|
|
`endif
|
| 1734 |
|
|
`ifdef MOBILE
|
| 1735 |
|
|
REF4BANK = `TRUE;
|
| 1736 |
|
|
REF2BANK = `FALSE;
|
| 1737 |
|
|
REF1BANK = `FALSE;
|
| 1738 |
|
|
`endif
|
| 1739 |
|
|
end
|
| 1740 |
|
|
`ifdef NOKIA
|
| 1741 |
|
|
else if (addr[8:7] === 2'b01) begin
|
| 1742 |
|
|
if (addr[6:4] === 3'b000) begin
|
| 1743 |
|
|
if (addr[3] === 1'b0) begin
|
| 1744 |
|
|
$display("-- Partial Refresh mode (16M)");
|
| 1745 |
|
|
REF16M_MODE = `TRUE;
|
| 1746 |
|
|
REF32M_MODE = `FALSE;
|
| 1747 |
|
|
end
|
| 1748 |
|
|
else if (addr[3] === 1'b1) begin
|
| 1749 |
|
|
$display("-- Partial Refresh mode (32M)");
|
| 1750 |
|
|
REF32M_MODE = `TRUE;
|
| 1751 |
|
|
REF16M_MODE = `FALSE;
|
| 1752 |
|
|
end
|
| 1753 |
|
|
end
|
| 1754 |
|
|
else if (addr[4] === 1'b1) begin
|
| 1755 |
|
|
if (addr[2] === 1'b0) $display("-- VREFi is set to 1.4V");
|
| 1756 |
|
|
if (addr[2] === 1'b1) $display("-- VREFi is set to 0.9V");
|
| 1757 |
|
|
end
|
| 1758 |
|
|
end
|
| 1759 |
|
|
`endif
|
| 1760 |
|
|
`ifdef MOBILE
|
| 1761 |
|
|
else if (ba[1] === 1'b1 && ba[0] === 1'b0) begin //Extended MRS for Mobile DRAM
|
| 1762 |
|
|
case(addr[6:5]) // Drive Strength
|
| 1763 |
|
|
2'b00:
|
| 1764 |
|
|
$display("-- Full drive strength");
|
| 1765 |
|
|
2'b01:
|
| 1766 |
|
|
$display("-- Half drive strength");
|
| 1767 |
|
|
default $display("Warning: Invalid drive strength address!");
|
| 1768 |
|
|
endcase
|
| 1769 |
|
|
case(addr[4:3]) // TCSR
|
| 1770 |
|
|
2'b00:
|
| 1771 |
|
|
$display("-- TCSR (46'C~70'C) mode");
|
| 1772 |
|
|
2'b01:
|
| 1773 |
|
|
$display("-- TCSR (16'C~45'C) mode");
|
| 1774 |
|
|
2'b10:
|
| 1775 |
|
|
$display("-- TCSR (-25'C~15'C) mode");
|
| 1776 |
|
|
2'b11:
|
| 1777 |
|
|
$display("-- TCSR (71'C~85'C) mode");
|
| 1778 |
|
|
default $display("Warning: Invalid TCSR address!");
|
| 1779 |
|
|
endcase
|
| 1780 |
|
|
case(addr[2:0]) // PASR
|
| 1781 |
|
|
3'b000: begin
|
| 1782 |
|
|
$display("-- PASR (4 banks) mode");
|
| 1783 |
|
|
REF4BANK = `TRUE;
|
| 1784 |
|
|
REF2BANK = `FALSE;
|
| 1785 |
|
|
REF1BANK = `FALSE;
|
| 1786 |
|
|
end
|
| 1787 |
|
|
3'b001: begin
|
| 1788 |
|
|
$display("-- PASR (2 banks) mode");
|
| 1789 |
|
|
REF4BANK = `FALSE;
|
| 1790 |
|
|
REF2BANK = `TRUE;
|
| 1791 |
|
|
REF1BANK = `FALSE;
|
| 1792 |
|
|
end
|
| 1793 |
|
|
3'b010: begin
|
| 1794 |
|
|
$display("-- PASR (1 banks) mode");
|
| 1795 |
|
|
REF4BANK = `FALSE;
|
| 1796 |
|
|
REF2BANK = `FALSE;
|
| 1797 |
|
|
REF1BANK = `TRUE;
|
| 1798 |
|
|
end
|
| 1799 |
|
|
default $display("Warning: Invalid PASR address!");
|
| 1800 |
|
|
endcase
|
| 1801 |
|
|
end
|
| 1802 |
|
|
`endif
|
| 1803 |
|
|
else
|
| 1804 |
|
|
begin
|
| 1805 |
|
|
$display("-- reserved for future use !!");
|
| 1806 |
|
|
$display("-- check address: [11,10,8,7] = %b",RFU);
|
| 1807 |
|
|
end
|
| 1808 |
|
|
|
| 1809 |
|
|
`ifdef M16G4_M64G3
|
| 1810 |
|
|
MRS_SET <= repeat (2) @(negedge pclk) `TRUE; // From 3 -> 2
|
| 1811 |
|
|
`else
|
| 1812 |
|
|
MRS_SET <= repeat (2) @(negedge pclk) `TRUE; // From 3 -> 2
|
| 1813 |
|
|
`endif
|
| 1814 |
|
|
end
|
| 1815 |
|
|
end
|
| 1816 |
|
|
|
| 1817 |
|
|
`protect
|
| 1818 |
|
|
/*
|
| 1819 |
|
|
*-----------------------------------------------------
|
| 1820 |
|
|
* ACTIVE command
|
| 1821 |
|
|
*-----------------------------------------------------
|
| 1822 |
|
|
*/
|
| 1823 |
|
|
|
| 1824 |
|
|
// In active command, bank is selected in accordance with A11 address.
|
| 1825 |
|
|
|
| 1826 |
|
|
always @(active)
|
| 1827 |
|
|
begin : active_op
|
| 1828 |
|
|
integer bank_id;
|
| 1829 |
|
|
reg [8*8:1] str;
|
| 1830 |
|
|
|
| 1831 |
|
|
if(CUR_TIME - TRAS_P < `tRRD-`MARGIN)
|
| 1832 |
|
|
begin
|
| 1833 |
|
|
$display("Warning: tRRD violation at %t", CUR_TIME);
|
| 1834 |
|
|
disable active_op;
|
| 1835 |
|
|
end
|
| 1836 |
|
|
|
| 1837 |
|
|
r_bank_addr = ba;
|
| 1838 |
|
|
|
| 1839 |
|
|
bank_id = BankSelect(ba);
|
| 1840 |
|
|
str = PrintBank(ba);
|
| 1841 |
|
|
|
| 1842 |
|
|
//if(CUR_TIME - $bitstoreal(TPRE_P[bank_id]) < `tRP-`MARGIN)
|
| 1843 |
|
|
if ((bank_id == 0) && (CUR_TIME - TPRE_P0 < `tRP-`MARGIN) ||
|
| 1844 |
|
|
(bank_id == 1) && (CUR_TIME - TPRE_P1 < `tRP-`MARGIN) ||
|
| 1845 |
|
|
(bank_id == 2) && (CUR_TIME - TPRE_P2 < `tRP-`MARGIN) ||
|
| 1846 |
|
|
(bank_id == 3) && (CUR_TIME - TPRE_P3 < `tRP-`MARGIN))
|
| 1847 |
|
|
begin
|
| 1848 |
|
|
$display("Warning: tRP violation at %t", CUR_TIME);
|
| 1849 |
|
|
disable active_op;
|
| 1850 |
|
|
end
|
| 1851 |
|
|
//if(CUR_TIME - $bitstoreal(TRAS_PP[bank_id]) < `tRC-`MARGIN) // 2.27
|
| 1852 |
|
|
if ((bank_id == 0) && (CUR_TIME - TRAS_PP0 < `tRC-`MARGIN) ||
|
| 1853 |
|
|
(bank_id == 1) && (CUR_TIME - TRAS_PP1 < `tRC-`MARGIN) ||
|
| 1854 |
|
|
(bank_id == 2) && (CUR_TIME - TRAS_PP2 < `tRC-`MARGIN) ||
|
| 1855 |
|
|
(bank_id == 3) && (CUR_TIME - TRAS_PP3 < `tRC-`MARGIN))
|
| 1856 |
|
|
begin
|
| 1857 |
|
|
$display("Warning: tRC violation at %t", CUR_TIME);
|
| 1858 |
|
|
disable active_op;
|
| 1859 |
|
|
end
|
| 1860 |
|
|
|
| 1861 |
|
|
if(Mode[bank_id] == `TRUE)
|
| 1862 |
|
|
begin
|
| 1863 |
|
|
$display("Warning: Illegal active (%0s is not precharged) at %t",str,CUR_TIME);
|
| 1864 |
|
|
end
|
| 1865 |
|
|
else
|
| 1866 |
|
|
begin
|
| 1867 |
|
|
/*
|
| 1868 |
|
|
md = Mode;
|
| 1869 |
|
|
md[bank_id] = 1;
|
| 1870 |
|
|
Mode = md;
|
| 1871 |
|
|
*/
|
| 1872 |
|
|
Mode[bank_id] = 1'b1;
|
| 1873 |
|
|
`ifdef v $display(">> active (%0s) at %t", str, CUR_TIME);
|
| 1874 |
|
|
`endif
|
| 1875 |
|
|
//TRAS_PP[bank_id] = $realtobits(CUR_TIME); // save current time for tRCD,tRC check.
|
| 1876 |
|
|
case(bank_id)//TRAS_PP
|
| 1877 |
|
|
'd0: TRAS_PP0 = CUR_TIME;
|
| 1878 |
|
|
'd1: TRAS_PP1 = CUR_TIME;
|
| 1879 |
|
|
'd2: TRAS_PP2 = CUR_TIME;
|
| 1880 |
|
|
'd3: TRAS_PP3 = CUR_TIME;
|
| 1881 |
|
|
endcase//TRAS_PP
|
| 1882 |
|
|
|
| 1883 |
|
|
r_addr_[bank_id] = addr[`ADDRTOP:0]; // check in 64M 2bank
|
| 1884 |
|
|
end
|
| 1885 |
|
|
//TRAS_PP[bank_id] = $realtobits(CUR_TIME); // save current time for tRCD,tRC check.
|
| 1886 |
|
|
case(bank_id)//TRAS_PP
|
| 1887 |
|
|
'd0: TRAS_PP0 = CUR_TIME;
|
| 1888 |
|
|
'd1: TRAS_PP1 = CUR_TIME;
|
| 1889 |
|
|
'd2: TRAS_PP2 = CUR_TIME;
|
| 1890 |
|
|
'd3: TRAS_PP3 = CUR_TIME;
|
| 1891 |
|
|
endcase//TRAS_PP
|
| 1892 |
|
|
TRAS_P = CUR_TIME;
|
| 1893 |
|
|
|
| 1894 |
|
|
end // active operation
|
| 1895 |
|
|
|
| 1896 |
|
|
/*
|
| 1897 |
|
|
*-----------------------------------------------------
|
| 1898 |
|
|
* READ command
|
| 1899 |
|
|
*-----------------------------------------------------
|
| 1900 |
|
|
*/
|
| 1901 |
|
|
|
| 1902 |
|
|
always @(read)
|
| 1903 |
|
|
begin :read_block
|
| 1904 |
|
|
integer bank_id;
|
| 1905 |
|
|
reg [8*8:1] str;
|
| 1906 |
|
|
|
| 1907 |
|
|
if(CUR_TIME - TCAS_P < `tCCD-`MARGIN)
|
| 1908 |
|
|
begin
|
| 1909 |
|
|
$display("Warning: tCCD violation at %t", CUR_TIME);
|
| 1910 |
|
|
disable read_block;
|
| 1911 |
|
|
end
|
| 1912 |
|
|
|
| 1913 |
|
|
`ifdef M512_M1024_X4
|
| 1914 |
|
|
c_addr = {addr[12:11],addr[`nCOL-3:0]};
|
| 1915 |
|
|
`else
|
| 1916 |
|
|
`ifdef M512_M1024_X8
|
| 1917 |
|
|
c_addr = {addr[11],addr[`nCOL-2:0]};
|
| 1918 |
|
|
`else
|
| 1919 |
|
|
`ifdef M128_M256_X4 // 98.6.30 BYC
|
| 1920 |
|
|
c_addr = {addr[11],addr[`nCOL-2:0]};
|
| 1921 |
|
|
`else
|
| 1922 |
|
|
c_addr = addr[`BIT_C];
|
| 1923 |
|
|
`endif
|
| 1924 |
|
|
`endif
|
| 1925 |
|
|
`endif
|
| 1926 |
|
|
c_bank_addr = ba;
|
| 1927 |
|
|
|
| 1928 |
|
|
bank_id = BankSelect(ba);
|
| 1929 |
|
|
str = PrintBank(ba);
|
| 1930 |
|
|
//if(CUR_TIME - $bitstoreal(TRAS_PP[bank_id]) < `tRCD-`MARGIN)
|
| 1931 |
|
|
if ((bank_id == 0) && (CUR_TIME - TRAS_PP0 < `tRCD-`MARGIN) ||
|
| 1932 |
|
|
(bank_id == 1) && (CUR_TIME - TRAS_PP1 < `tRCD-`MARGIN) ||
|
| 1933 |
|
|
(bank_id == 2) && (CUR_TIME - TRAS_PP2 < `tRCD-`MARGIN) ||
|
| 1934 |
|
|
(bank_id == 3) && (CUR_TIME - TRAS_PP3 < `tRCD-`MARGIN))
|
| 1935 |
|
|
begin
|
| 1936 |
|
|
$display("Warning: tRCD violation at %t", CUR_TIME);
|
| 1937 |
|
|
disable read_block;
|
| 1938 |
|
|
end
|
| 1939 |
|
|
r_addr = r_addr_[bank_id];
|
| 1940 |
|
|
`endprotect
|
| 1941 |
|
|
|
| 1942 |
|
|
if(Mode[bank_id] == `TRUE)
|
| 1943 |
|
|
begin
|
| 1944 |
|
|
if( addr[`ADDR_AP] == `TRUE)
|
| 1945 |
|
|
begin
|
| 1946 |
|
|
`ifdef v $display(">> read with auto precharge(%0s) at %t",str,CUR_TIME);
|
| 1947 |
|
|
`endif
|
| 1948 |
|
|
auto_flag[bank_id] <= @(negedge pclk) `TRUE;
|
| 1949 |
|
|
rd_autoprech_reg <= @(negedge pclk) ba;
|
| 1950 |
|
|
end
|
| 1951 |
|
|
else begin
|
| 1952 |
|
|
`ifdef v $display(">> read (%0s) at %t ",str,CUR_TIME);
|
| 1953 |
|
|
`endif
|
| 1954 |
|
|
auto_flag[bank_id] <= @(negedge pclk) `FALSE;
|
| 1955 |
|
|
end
|
| 1956 |
|
|
end
|
| 1957 |
|
|
|
| 1958 |
|
|
else begin
|
| 1959 |
|
|
`ifdef v $display("Illegal Read %0s is not activated",str);
|
| 1960 |
|
|
`endif
|
| 1961 |
|
|
disable read_block;
|
| 1962 |
|
|
end
|
| 1963 |
|
|
|
| 1964 |
|
|
READ_MODE = `TRUE; // read operation start
|
| 1965 |
|
|
TCAS_P = CUR_TIME;
|
| 1966 |
|
|
|
| 1967 |
|
|
m_addr = {r_addr, c_addr};
|
| 1968 |
|
|
|
| 1969 |
|
|
if(~burst_type)
|
| 1970 |
|
|
increment_read;
|
| 1971 |
|
|
else
|
| 1972 |
|
|
interleave_read;
|
| 1973 |
|
|
|
| 1974 |
|
|
`ifdef M16G4_M64G3
|
| 1975 |
|
|
`else
|
| 1976 |
|
|
if( auto_flag[bank_id] )
|
| 1977 |
|
|
begin
|
| 1978 |
|
|
if( BL != 1)
|
| 1979 |
|
|
auto_flagx <= @(negedge pclk) `TRUE;
|
| 1980 |
|
|
->autostart;
|
| 1981 |
|
|
end
|
| 1982 |
|
|
`endif
|
| 1983 |
|
|
|
| 1984 |
|
|
read_task; // task call
|
| 1985 |
|
|
|
| 1986 |
|
|
READ_MODE = `FALSE; // read operation end.
|
| 1987 |
|
|
// last_rw = CUR_TIME;
|
| 1988 |
|
|
last_rw = TCLK_H;
|
| 1989 |
|
|
|
| 1990 |
|
|
if( auto_flag[bank_id] )
|
| 1991 |
|
|
begin
|
| 1992 |
|
|
// rd_autoprech_reg = c_bank_addr;
|
| 1993 |
|
|
if ({CSB_FLAG,RASB_FLAG,CASB_FLAG} == 3'b010 && bank_id === ba)
|
| 1994 |
|
|
$display($time, " Warning: For actual device, this gapless command would be illegal");
|
| 1995 |
|
|
else
|
| 1996 |
|
|
->rd_autoprecharge;
|
| 1997 |
|
|
end
|
| 1998 |
|
|
end
|
| 1999 |
|
|
|
| 2000 |
|
|
/*
|
| 2001 |
|
|
*-----------------------------------------------------
|
| 2002 |
|
|
* WRITE command
|
| 2003 |
|
|
*-----------------------------------------------------
|
| 2004 |
|
|
*/
|
| 2005 |
|
|
|
| 2006 |
|
|
//always @(write)
|
| 2007 |
|
|
always @(posedge write_event)//KyW ... 0408 for VCS
|
| 2008 |
|
|
begin:write_block
|
| 2009 |
|
|
integer bank_id;
|
| 2010 |
|
|
reg [8*8:1] str;
|
| 2011 |
|
|
|
| 2012 |
|
|
if(CUR_TIME - TCAS_P < `tCCD-`MARGIN)
|
| 2013 |
|
|
begin
|
| 2014 |
|
|
$display("Warning: tCCD violation at %t", CUR_TIME);
|
| 2015 |
|
|
disable write_block;
|
| 2016 |
|
|
end
|
| 2017 |
|
|
|
| 2018 |
|
|
`ifdef M512_X4
|
| 2019 |
|
|
c_addr = {addr[12:11],addr[`nCOL-3:0]};
|
| 2020 |
|
|
`else
|
| 2021 |
|
|
`ifdef M512_X8
|
| 2022 |
|
|
c_addr = {addr[11],addr[`nCOL-2:0]};
|
| 2023 |
|
|
`else
|
| 2024 |
|
|
`ifdef M128_M256_X4 // 98.6.30 BYC
|
| 2025 |
|
|
c_addr = {addr[11],addr[`nCOL-2:0]};
|
| 2026 |
|
|
`else
|
| 2027 |
|
|
c_addr = addr[`BIT_C];
|
| 2028 |
|
|
`endif
|
| 2029 |
|
|
`endif
|
| 2030 |
|
|
`endif
|
| 2031 |
|
|
c_bank_addr = ba;
|
| 2032 |
|
|
|
| 2033 |
|
|
bank_id = BankSelect(ba);
|
| 2034 |
|
|
str = PrintBank(ba);
|
| 2035 |
|
|
r_addr = r_addr_[bank_id];
|
| 2036 |
|
|
|
| 2037 |
|
|
//if(CUR_TIME - $bitstoreal(TRAS_PP[bank_id]) < `tRCD-`MARGIN)
|
| 2038 |
|
|
if ((bank_id == 0) && (CUR_TIME - TRAS_PP0 < `tRCD-`MARGIN) ||
|
| 2039 |
|
|
(bank_id == 1) && (CUR_TIME - TRAS_PP1 < `tRCD-`MARGIN) ||
|
| 2040 |
|
|
(bank_id == 2) && (CUR_TIME - TRAS_PP2 < `tRCD-`MARGIN) ||
|
| 2041 |
|
|
(bank_id == 3) && (CUR_TIME - TRAS_PP3 < `tRCD-`MARGIN))
|
| 2042 |
|
|
begin
|
| 2043 |
|
|
$display("Warning: tRCD violation at %t", CUR_TIME);
|
| 2044 |
|
|
disable write_block;
|
| 2045 |
|
|
end
|
| 2046 |
|
|
|
| 2047 |
|
|
if(Mode[bank_id] == `TRUE)
|
| 2048 |
|
|
begin
|
| 2049 |
|
|
if(addr[`ADDR_AP])
|
| 2050 |
|
|
begin
|
| 2051 |
|
|
`ifdef v $display(">> write with auto precharge( %0s ) at %t",str,CUR_TIME);
|
| 2052 |
|
|
`endif
|
| 2053 |
|
|
auto_flag[bank_id] <= @(negedge pclk) `TRUE;
|
| 2054 |
|
|
//`ifdef RDL2
|
| 2055 |
|
|
if (`tRDL == 2)
|
| 2056 |
|
|
wr_autoprech_reg2 <= @(negedge pclk) ba;
|
| 2057 |
|
|
//`else
|
| 2058 |
|
|
else
|
| 2059 |
|
|
wr_autoprech_reg <= @(negedge pclk) ba;
|
| 2060 |
|
|
//`endif
|
| 2061 |
|
|
end
|
| 2062 |
|
|
else begin
|
| 2063 |
|
|
`ifdef v $display(">> write ( %0s ) at %t",str,CUR_TIME);
|
| 2064 |
|
|
`endif
|
| 2065 |
|
|
auto_flag[bank_id] <= @(negedge pclk) `FALSE;
|
| 2066 |
|
|
/*
|
| 2067 |
|
|
if (auto_flag == `TRUE && autoprech_reg == ba)
|
| 2068 |
|
|
auto_flag = `FALSE;
|
| 2069 |
|
|
*/
|
| 2070 |
|
|
end
|
| 2071 |
|
|
end
|
| 2072 |
|
|
else
|
| 2073 |
|
|
begin
|
| 2074 |
|
|
$display("Warning: Illegal write command at %t",CUR_TIME);
|
| 2075 |
|
|
disable write_block;
|
| 2076 |
|
|
end
|
| 2077 |
|
|
|
| 2078 |
|
|
WRITE_MODE = `TRUE;
|
| 2079 |
|
|
TCAS_P = CUR_TIME;
|
| 2080 |
|
|
|
| 2081 |
|
|
m_addr = {r_addr, c_addr};
|
| 2082 |
|
|
|
| 2083 |
|
|
`ifdef M16G4_M64G3
|
| 2084 |
|
|
`else
|
| 2085 |
|
|
if( auto_flag[bank_id] )
|
| 2086 |
|
|
begin
|
| 2087 |
|
|
if( WBL != 1)
|
| 2088 |
|
|
auto_flagx <= @(negedge pclk) `TRUE;
|
| 2089 |
|
|
->autostart;
|
| 2090 |
|
|
end
|
| 2091 |
|
|
`endif
|
| 2092 |
|
|
|
| 2093 |
|
|
write_task;
|
| 2094 |
|
|
|
| 2095 |
|
|
WRITE_MODE <= #(`tSH) `FALSE;
|
| 2096 |
|
|
last_rw = CUR_TIME;
|
| 2097 |
|
|
|
| 2098 |
|
|
@(posedge pclk);
|
| 2099 |
|
|
if(auto_flag[bank_id]) begin
|
| 2100 |
|
|
if ({CSB_FLAG,RASB_FLAG,CASB_FLAG} == 3'b010 && bank_id === ba)
|
| 2101 |
|
|
$display($time, " Warning: For actual device, this gapless command would be illegal");
|
| 2102 |
|
|
else begin
|
| 2103 |
|
|
//`ifdef RDL2
|
| 2104 |
|
|
if (`tRDL == 2)
|
| 2105 |
|
|
#0 ->wr_autoprecharge2;
|
| 2106 |
|
|
//`else
|
| 2107 |
|
|
else
|
| 2108 |
|
|
->wr_autoprecharge;
|
| 2109 |
|
|
//`endif
|
| 2110 |
|
|
end
|
| 2111 |
|
|
end
|
| 2112 |
|
|
end
|
| 2113 |
|
|
|
| 2114 |
|
|
`protect
|
| 2115 |
|
|
// In bank interleave write mode, din data should be stored
|
| 2116 |
|
|
// in din register as the other bank selection occurred.
|
| 2117 |
|
|
|
| 2118 |
|
|
always @(flush_write)
|
| 2119 |
|
|
begin
|
| 2120 |
|
|
if(~burst_type)
|
| 2121 |
|
|
increment_write;
|
| 2122 |
|
|
else
|
| 2123 |
|
|
interleave_write;
|
| 2124 |
|
|
end
|
| 2125 |
|
|
|
| 2126 |
|
|
/*
|
| 2127 |
|
|
*-----------------------------------------------------
|
| 2128 |
|
|
* REFRESH command
|
| 2129 |
|
|
*-----------------------------------------------------
|
| 2130 |
|
|
*/
|
| 2131 |
|
|
|
| 2132 |
|
|
always @(autorefresh)
|
| 2133 |
|
|
begin : auto_op
|
| 2134 |
|
|
if (INIT == `FALSE && MRS_SET == `FALSE) // for refersh protection during MRS_ING
|
| 2135 |
|
|
begin
|
| 2136 |
|
|
$display("Warning: Illegal refresh command at %t",CUR_TIME);
|
| 2137 |
|
|
disable auto_op;
|
| 2138 |
|
|
end
|
| 2139 |
|
|
|
| 2140 |
|
|
if (|Mode !== 1'b0) begin
|
| 2141 |
|
|
$display("Warning: Illegal refresh command at %t",CUR_TIME);
|
| 2142 |
|
|
disable auto_op;
|
| 2143 |
|
|
end
|
| 2144 |
|
|
|
| 2145 |
|
|
/* -- jhkim-TEST
|
| 2146 |
|
|
`ifdef M16G4_M64G3
|
| 2147 |
|
|
`else
|
| 2148 |
|
|
for(i=0; i < `nBank; i=i+1)
|
| 2149 |
|
|
begin
|
| 2150 |
|
|
//if( CUR_TIME - $bitstoreal(TRAS_PP[i]) < `tRFC-`MARGIN )
|
| 2151 |
|
|
if ((i == 0) && (CUR_TIME - TRAS_PP0 < `tRFC-`MARGIN) ||
|
| 2152 |
|
|
(i == 1) && (CUR_TIME - TRAS_PP1 < `tRFC-`MARGIN) ||
|
| 2153 |
|
|
(i == 2) && (CUR_TIME - TRAS_PP2 < `tRFC-`MARGIN) ||
|
| 2154 |
|
|
(i == 3) && (CUR_TIME - TRAS_PP3 < `tRFC-`MARGIN))
|
| 2155 |
|
|
$display("Warning: tRFC violation at %t",CUR_TIME);
|
| 2156 |
|
|
end
|
| 2157 |
|
|
`endif
|
| 2158 |
|
|
*/
|
| 2159 |
|
|
|
| 2160 |
|
|
AUTOREF_MODE = `TRUE;
|
| 2161 |
|
|
`ifdef v
|
| 2162 |
|
|
//`ifdef NOKIA
|
| 2163 |
|
|
// if (REF16M_MODE == `TRUE)
|
| 2164 |
|
|
// $display(">> partial auto refresh (16M) at %t",CUR_TIME);
|
| 2165 |
|
|
// else if (REF32M_MODE == `TRUE)
|
| 2166 |
|
|
// $display(">> partial auto refresh (32M) at %t",CUR_TIME);
|
| 2167 |
|
|
// else
|
| 2168 |
|
|
//`endif
|
| 2169 |
|
|
$display(">> auto refresh at %t",CUR_TIME);
|
| 2170 |
|
|
`endif
|
| 2171 |
|
|
/* -- jhkim-TEST
|
| 2172 |
|
|
`ifdef M16G4_M64G3
|
| 2173 |
|
|
AUTOREF_MODE = #(`tRC) `FALSE;
|
| 2174 |
|
|
`else
|
| 2175 |
|
|
AUTOREF_MODE = #(`tRFC) `FALSE;
|
| 2176 |
|
|
`endif
|
| 2177 |
|
|
*/
|
| 2178 |
|
|
`ifdef tARFC
|
| 2179 |
|
|
AUTOREF_MODE = #(`tARFC) `FALSE;
|
| 2180 |
|
|
`else
|
| 2181 |
|
|
AUTOREF_MODE = #(`tRC) `FALSE;
|
| 2182 |
|
|
`endif
|
| 2183 |
|
|
|
| 2184 |
|
|
end
|
| 2185 |
|
|
|
| 2186 |
|
|
/*
|
| 2187 |
|
|
*-----------------------------------------------------
|
| 2188 |
|
|
* SELF REFRESH command
|
| 2189 |
|
|
*-----------------------------------------------------
|
| 2190 |
|
|
*/
|
| 2191 |
|
|
|
| 2192 |
|
|
always @(selfrefresh)
|
| 2193 |
|
|
begin : self_op
|
| 2194 |
|
|
if (|Mode == 1'b0) begin
|
| 2195 |
|
|
SELFREF_MODE = `TRUE;
|
| 2196 |
|
|
`ifdef v
|
| 2197 |
|
|
`ifdef NOKIA
|
| 2198 |
|
|
if (REF16M_MODE == `TRUE)
|
| 2199 |
|
|
$display(">> partial self refresh (16M) enter at %t",CUR_TIME);
|
| 2200 |
|
|
else if (REF32M_MODE == `TRUE)
|
| 2201 |
|
|
$display(">> partial self refresh (32M) enter at %t",CUR_TIME);
|
| 2202 |
|
|
else
|
| 2203 |
|
|
`endif
|
| 2204 |
|
|
`ifdef MOBILE
|
| 2205 |
|
|
if (REF4BANK == `TRUE)
|
| 2206 |
|
|
$display(">> Partial Array Self Refresh (4banks) enter at %t",CUR_TIME);
|
| 2207 |
|
|
else if (REF2BANK == `TRUE)
|
| 2208 |
|
|
$display(">> Partial Array Self Refresh (2banks) enter at %t",CUR_TIME);
|
| 2209 |
|
|
else if (REF1BANK == `TRUE)
|
| 2210 |
|
|
$display(">> Partial Array Self Refresh (1banks) enter at %t",CUR_TIME);
|
| 2211 |
|
|
else
|
| 2212 |
|
|
`endif
|
| 2213 |
|
|
$display(">> self refresh enter at %t",CUR_TIME);
|
| 2214 |
|
|
`endif
|
| 2215 |
|
|
TSELF = CUR_TIME;
|
| 2216 |
|
|
end
|
| 2217 |
|
|
else begin
|
| 2218 |
|
|
$display("Warning: Illegal self refresh command at %t",CUR_TIME);
|
| 2219 |
|
|
disable self_op;
|
| 2220 |
|
|
end
|
| 2221 |
|
|
|
| 2222 |
|
|
for(i =0; i < `nBank; i = i+1)
|
| 2223 |
|
|
begin
|
| 2224 |
|
|
/* -- jhkim-TEST
|
| 2225 |
|
|
`ifdef M16G4_M64G3
|
| 2226 |
|
|
//if( CUR_TIME - $bitstoreal(TRAS_PP[i]) < `tRC-`MARGIN )
|
| 2227 |
|
|
if ((i == 0) && (CUR_TIME - TRAS_PP0 < `tRC-`MARGIN) ||
|
| 2228 |
|
|
(i == 1) && (CUR_TIME - TRAS_PP1 < `tRC-`MARGIN) ||
|
| 2229 |
|
|
(i == 2) && (CUR_TIME - TRAS_PP2 < `tRC-`MARGIN) ||
|
| 2230 |
|
|
(i == 3) && (CUR_TIME - TRAS_PP3 < `tRC-`MARGIN))
|
| 2231 |
|
|
$display("Warning: tRC violation at %t",CUR_TIME);
|
| 2232 |
|
|
`else
|
| 2233 |
|
|
//if( CUR_TIME - $bitstoreal(TRAS_PP[i]) < `tRFC-`MARGIN )
|
| 2234 |
|
|
if ((i == 0) && (CUR_TIME - TRAS_PP0 < `tRFC-`MARGIN) ||
|
| 2235 |
|
|
(i == 1) && (CUR_TIME - TRAS_PP1 < `tRFC-`MARGIN) ||
|
| 2236 |
|
|
(i == 2) && (CUR_TIME - TRAS_PP2 < `tRFC-`MARGIN) ||
|
| 2237 |
|
|
(i == 3) && (CUR_TIME - TRAS_PP3 < `tRFC-`MARGIN))
|
| 2238 |
|
|
$display("Warning: tRFC violation at %t",CUR_TIME);
|
| 2239 |
|
|
`endif
|
| 2240 |
|
|
*/
|
| 2241 |
|
|
//if( CUR_TIME - $bitstoreal(TRAS_PP[i]) < `tRC-`MARGIN )
|
| 2242 |
|
|
if ((i == 0) && (CUR_TIME - TRAS_PP0 < `tRC-`MARGIN) ||
|
| 2243 |
|
|
(i == 1) && (CUR_TIME - TRAS_PP1 < `tRC-`MARGIN) ||
|
| 2244 |
|
|
(i == 2) && (CUR_TIME - TRAS_PP2 < `tRC-`MARGIN) ||
|
| 2245 |
|
|
(i == 3) && (CUR_TIME - TRAS_PP3 < `tRC-`MARGIN))
|
| 2246 |
|
|
$display("Warning: tRC violation at %t",CUR_TIME);
|
| 2247 |
|
|
end
|
| 2248 |
|
|
end
|
| 2249 |
|
|
|
| 2250 |
|
|
always @(selfexit) begin
|
| 2251 |
|
|
TSEXIT = CUR_TIME;
|
| 2252 |
|
|
/* -- jhkim-TEST
|
| 2253 |
|
|
`ifdef M16G4_M64G3
|
| 2254 |
|
|
SELFREF_MODE = #(`tRC) `FALSE;
|
| 2255 |
|
|
`else
|
| 2256 |
|
|
SELFREF_MODE = #(`tRFC) `FALSE;
|
| 2257 |
|
|
`endif
|
| 2258 |
|
|
*/
|
| 2259 |
|
|
`ifdef tSRFX
|
| 2260 |
|
|
SELFREF_MODE = #(`tSRFX) `FALSE;
|
| 2261 |
|
|
`else
|
| 2262 |
|
|
SELFREF_MODE = #(`tRC) `FALSE;
|
| 2263 |
|
|
`endif
|
| 2264 |
|
|
end
|
| 2265 |
|
|
|
| 2266 |
|
|
/*
|
| 2267 |
|
|
always @(negedge cke) begin
|
| 2268 |
|
|
if (SELFREF_MODE == `TRUE && POWERDOWN_MODE == `FALSE) begin
|
| 2269 |
|
|
if (CUR_TIME - TSEXIT < `tSRX-`MARGIN)
|
| 2270 |
|
|
$display("Warning: tSRX violation at %t", CUR_TIME);
|
| 2271 |
|
|
end
|
| 2272 |
|
|
end
|
| 2273 |
|
|
*/
|
| 2274 |
|
|
`endprotect
|
| 2275 |
|
|
|
| 2276 |
|
|
/*
|
| 2277 |
|
|
*-----------------------------------------------------
|
| 2278 |
|
|
* PRECHARGE command
|
| 2279 |
|
|
*-----------------------------------------------------
|
| 2280 |
|
|
*/
|
| 2281 |
|
|
|
| 2282 |
|
|
// precharge command performs to disable active operation.
|
| 2283 |
|
|
|
| 2284 |
|
|
always @(precharge)
|
| 2285 |
|
|
begin : prech_op
|
| 2286 |
|
|
integer bank_id;
|
| 2287 |
|
|
integer i;
|
| 2288 |
|
|
reg [8*8:1] str;
|
| 2289 |
|
|
reg [8*8:1] str1;
|
| 2290 |
|
|
|
| 2291 |
|
|
`ifdef NBANK4
|
| 2292 |
|
|
bank_id = BankSelect(prech_reg[2:1]);
|
| 2293 |
|
|
str = PrintBank(prech_reg[2:1]);
|
| 2294 |
|
|
`endif
|
| 2295 |
|
|
`ifdef NBANK2
|
| 2296 |
|
|
bank_id = BankSelect(prech_reg[1]);
|
| 2297 |
|
|
str = PrintBank(prech_reg[1]);
|
| 2298 |
|
|
`endif
|
| 2299 |
|
|
`protect
|
| 2300 |
|
|
|
| 2301 |
|
|
if(prech_reg[0] == `FALSE)
|
| 2302 |
|
|
begin
|
| 2303 |
|
|
|
| 2304 |
|
|
if(Mode[bank_id] !== 1'b0)
|
| 2305 |
|
|
begin
|
| 2306 |
|
|
|
| 2307 |
|
|
//if(CUR_TIME - $bitstoreal(TRAS_PP[bank_id]) < `tRASmin-`MARGIN)
|
| 2308 |
|
|
if ((bank_id == 0) && (CUR_TIME - TRAS_PP0 < `tRASmin-`MARGIN) ||
|
| 2309 |
|
|
(bank_id == 1) && (CUR_TIME - TRAS_PP1 < `tRASmin-`MARGIN) ||
|
| 2310 |
|
|
(bank_id == 2) && (CUR_TIME - TRAS_PP2 < `tRASmin-`MARGIN) ||
|
| 2311 |
|
|
(bank_id == 3) && (CUR_TIME - TRAS_PP3 < `tRASmin-`MARGIN))
|
| 2312 |
|
|
begin
|
| 2313 |
|
|
$display("Warning: tRASmin violation( %0s ) at %t", str, CUR_TIME);
|
| 2314 |
|
|
disable prech_op;
|
| 2315 |
|
|
end
|
| 2316 |
|
|
|
| 2317 |
|
|
//if(first_pre[bank_id]==`FALSE && CUR_TIME - $bitstoreal(TRAS_PP[bank_id]) > `tRASmax+`MARGIN)
|
| 2318 |
|
|
if (first_pre[bank_id]==`FALSE && ((bank_id == 0) && (CUR_TIME - TRAS_PP0 > `tRASmax-`MARGIN) ||
|
| 2319 |
|
|
(bank_id == 1) && (CUR_TIME - TRAS_PP1 > `tRASmax-`MARGIN) ||
|
| 2320 |
|
|
(bank_id == 2) && (CUR_TIME - TRAS_PP2 > `tRASmax-`MARGIN) ||
|
| 2321 |
|
|
(bank_id == 3) && (CUR_TIME - TRAS_PP3 > `tRASmax-`MARGIN)))
|
| 2322 |
|
|
$display("Warning: tRASmax violation( %0s ) at %t", str, CUR_TIME);
|
| 2323 |
|
|
|
| 2324 |
|
|
first_pre[bank_id] = `FALSE;
|
| 2325 |
|
|
|
| 2326 |
|
|
md = Mode;
|
| 2327 |
|
|
md[bank_id] = 0;
|
| 2328 |
|
|
Mode = md;
|
| 2329 |
|
|
`ifdef v $display(">> precharge ( %0s ) at %t", str, CUR_TIME);
|
| 2330 |
|
|
`endif
|
| 2331 |
|
|
end
|
| 2332 |
|
|
|
| 2333 |
|
|
else
|
| 2334 |
|
|
begin
|
| 2335 |
|
|
`ifdef v $display("-- current precharge command is NOP at %t",CUR_TIME);
|
| 2336 |
|
|
`endif
|
| 2337 |
|
|
disable prech_op;
|
| 2338 |
|
|
end
|
| 2339 |
|
|
|
| 2340 |
|
|
precharge_flag[bank_id] = `TRUE;
|
| 2341 |
|
|
kill_bank = bank_id;
|
| 2342 |
|
|
->precharge_flag_kill;
|
| 2343 |
|
|
//TPRE_P[bank_id] = $realtobits(CUR_TIME);
|
| 2344 |
|
|
case(bank_id)//TPRE_P
|
| 2345 |
|
|
'd0: TPRE_P0 = CUR_TIME;
|
| 2346 |
|
|
'd1: TPRE_P1 = CUR_TIME;
|
| 2347 |
|
|
'd2: TPRE_P2 = CUR_TIME;
|
| 2348 |
|
|
'd3: TPRE_P3 = CUR_TIME;
|
| 2349 |
|
|
endcase//TPRE_P
|
| 2350 |
|
|
end
|
| 2351 |
|
|
|
| 2352 |
|
|
else
|
| 2353 |
|
|
begin
|
| 2354 |
|
|
if(|Mode[`nBank-1:0] !== 1'b0) // BYC
|
| 2355 |
|
|
begin
|
| 2356 |
|
|
|
| 2357 |
|
|
for(i = 0; i < `nBank; i = i+1)
|
| 2358 |
|
|
begin
|
| 2359 |
|
|
case(i)
|
| 2360 |
|
|
'd0 :
|
| 2361 |
|
|
str1 = " A Bank";
|
| 2362 |
|
|
'd2 :
|
| 2363 |
|
|
str1 = " B Bank";
|
| 2364 |
|
|
'd1 :
|
| 2365 |
|
|
str1 = " C Bank";
|
| 2366 |
|
|
'd3 :
|
| 2367 |
|
|
str1 = " D Bank";
|
| 2368 |
|
|
default :
|
| 2369 |
|
|
str1 = "Bad Bank";
|
| 2370 |
|
|
endcase
|
| 2371 |
|
|
|
| 2372 |
|
|
//if(Mode[i] !== 1'b0 && CUR_TIME - $bitstoreal(TRAS_PP[i]) < `tRASmin-`MARGIN)
|
| 2373 |
|
|
if (Mode[i] !== 1'b0 && ((i == 0) && (CUR_TIME - TRAS_PP0 < `tRASmin-`MARGIN) ||
|
| 2374 |
|
|
(i == 1) && (CUR_TIME - TRAS_PP1 < `tRASmin-`MARGIN) ||
|
| 2375 |
|
|
(i == 2) && (CUR_TIME - TRAS_PP2 < `tRASmin-`MARGIN) ||
|
| 2376 |
|
|
(i == 3) && (CUR_TIME - TRAS_PP3 < `tRASmin-`MARGIN)))
|
| 2377 |
|
|
begin
|
| 2378 |
|
|
$display("Warning: tRASmin violation ( %0s ) at %t", str1, CUR_TIME);
|
| 2379 |
|
|
disable prech_op;
|
| 2380 |
|
|
end
|
| 2381 |
|
|
|
| 2382 |
|
|
//if(Mode[i] !== 1'b0 && first_pre[i]==`FALSE && CUR_TIME - $bitstoreal(TRAS_PP[i]) > `tRASmax+`MARGIN)
|
| 2383 |
|
|
if (Mode[i] !== 1'b0 && first_pre[i]==`FALSE && ((i == 0) && (CUR_TIME - TRAS_PP0 > `tRASmax-`MARGIN) ||
|
| 2384 |
|
|
(i == 1) && (CUR_TIME - TRAS_PP1 > `tRASmax-`MARGIN) ||
|
| 2385 |
|
|
(i == 2) && (CUR_TIME - TRAS_PP2 > `tRASmax-`MARGIN) ||
|
| 2386 |
|
|
(i == 3) && (CUR_TIME - TRAS_PP3 > `tRASmax-`MARGIN)))
|
| 2387 |
|
|
$display("Warning: tRASmax violation ( %0s ) at %t", str1, CUR_TIME);
|
| 2388 |
|
|
|
| 2389 |
|
|
first_pre[i] = `FALSE;
|
| 2390 |
|
|
|
| 2391 |
|
|
Mode[i] = 1'b0;
|
| 2392 |
|
|
precharge_flag[i] = `TRUE;
|
| 2393 |
|
|
//TPRE_P[i] = $realtobits(CUR_TIME);
|
| 2394 |
|
|
case(i)//TPRE_P
|
| 2395 |
|
|
'd0: TPRE_P0 = CUR_TIME;
|
| 2396 |
|
|
'd1: TPRE_P1 = CUR_TIME;
|
| 2397 |
|
|
'd2: TPRE_P2 = CUR_TIME;
|
| 2398 |
|
|
'd3: TPRE_P3 = CUR_TIME;
|
| 2399 |
|
|
endcase//TPRE_P
|
| 2400 |
|
|
first_pre[i] = `FALSE;
|
| 2401 |
|
|
end
|
| 2402 |
|
|
|
| 2403 |
|
|
`ifdef NBANK2
|
| 2404 |
|
|
`ifdef v $display(">> precharge ( A and B bank ) at %t",CUR_TIME);
|
| 2405 |
|
|
`endif
|
| 2406 |
|
|
`endif
|
| 2407 |
|
|
`ifdef NBANK4
|
| 2408 |
|
|
`ifdef v $display(">> precharge ( A,B,C, and D bank ) at %t",CUR_TIME);
|
| 2409 |
|
|
`endif
|
| 2410 |
|
|
`endif
|
| 2411 |
|
|
end
|
| 2412 |
|
|
|
| 2413 |
|
|
else
|
| 2414 |
|
|
begin
|
| 2415 |
|
|
`ifdef v $display("-- current precharge command is NOP at %t",CUR_TIME);
|
| 2416 |
|
|
`endif
|
| 2417 |
|
|
disable prech_op;
|
| 2418 |
|
|
end
|
| 2419 |
|
|
|
| 2420 |
|
|
kill_bank = bank_id;
|
| 2421 |
|
|
->precharge_flag_kill;
|
| 2422 |
|
|
|
| 2423 |
|
|
end
|
| 2424 |
|
|
->precharge_start;
|
| 2425 |
|
|
end
|
| 2426 |
|
|
`endprotect
|
| 2427 |
|
|
|
| 2428 |
|
|
/*
|
| 2429 |
|
|
*-----------------------------------------------------
|
| 2430 |
|
|
* tRDL=2 AUTO PRECHARGE command
|
| 2431 |
|
|
*-----------------------------------------------------
|
| 2432 |
|
|
*/
|
| 2433 |
|
|
|
| 2434 |
|
|
always @(wr_autoprecharge2) begin
|
| 2435 |
|
|
wr_autoprech_reg = wr_autoprech_reg2;
|
| 2436 |
|
|
@(posedge pclk);
|
| 2437 |
|
|
if ({CSB_FLAG,RASB_FLAG,CASB_FLAG} == 3'b010 && wr_autoprech_reg === ba)
|
| 2438 |
|
|
$display($time, " Warning: For actual device, this 1-clk-gap command would be illegal");
|
| 2439 |
|
|
else
|
| 2440 |
|
|
->wr_autoprecharge;
|
| 2441 |
|
|
end
|
| 2442 |
|
|
|
| 2443 |
|
|
/*
|
| 2444 |
|
|
*-----------------------------------------------------
|
| 2445 |
|
|
* READ AUTO PRECHARGE command
|
| 2446 |
|
|
*-----------------------------------------------------
|
| 2447 |
|
|
*/
|
| 2448 |
|
|
|
| 2449 |
|
|
always @(rd_autoprecharge or posedge rd_reautoprecharge)
|
| 2450 |
|
|
begin : rd_autoprech_op
|
| 2451 |
|
|
real difftime;
|
| 2452 |
|
|
integer bank_id;
|
| 2453 |
|
|
reg [8*8:1] str;
|
| 2454 |
|
|
reg tmp_reauto;
|
| 2455 |
|
|
integer prev_bank;
|
| 2456 |
|
|
integer tmp_bank;
|
| 2457 |
|
|
|
| 2458 |
|
|
tmp_reauto = `FALSE;
|
| 2459 |
|
|
bank_id = BankSelect(rd_autoprech_reg);
|
| 2460 |
|
|
if (rd_reautoprecharge == `TRUE) begin
|
| 2461 |
|
|
rd_reautoprecharge = `FALSE;
|
| 2462 |
|
|
tmp_bank = prev_bank;
|
| 2463 |
|
|
end
|
| 2464 |
|
|
else
|
| 2465 |
|
|
tmp_bank = bank_id;
|
| 2466 |
|
|
str = PrintBank(tmp_bank);
|
| 2467 |
|
|
//difftime = $realtime - $bitstoreal(TRAS_PP[tmp_bank]);
|
| 2468 |
|
|
case(tmp_bank)//TRAS_PP
|
| 2469 |
|
|
'd0: difftime = $realtime-TRAS_PP0;
|
| 2470 |
|
|
'd1: difftime = $realtime-TRAS_PP1;
|
| 2471 |
|
|
'd2: difftime = $realtime-TRAS_PP2;
|
| 2472 |
|
|
'd3: difftime = $realtime-TRAS_PP3;
|
| 2473 |
|
|
endcase//TRAS_PP
|
| 2474 |
|
|
if(difftime < `tRASmin-`MARGIN)
|
| 2475 |
|
|
begin
|
| 2476 |
|
|
`ifdef M64G3_M128_M256
|
| 2477 |
|
|
//auto_flagx <= `TRUE; // KyW ... 0624 : rev 3.3
|
| 2478 |
|
|
//auto_flagx <= #(`tRASmin-difftime) `FALSE; // KyW ... 0624 : rev 3.3
|
| 2479 |
|
|
prev_bank <= #(`tRASmin-difftime) tmp_bank;
|
| 2480 |
|
|
rd_reautoprecharge <= #(`tRASmin-difftime) `TRUE;
|
| 2481 |
|
|
tmp_reauto = `TRUE;
|
| 2482 |
|
|
`ifdef v $display(" Info: Staring Auto precharge (%s) delayed by tRASmin violation at %t", str, $time);
|
| 2483 |
|
|
`endif
|
| 2484 |
|
|
// #0 disable rd_autoprech_op;
|
| 2485 |
|
|
`else
|
| 2486 |
|
|
rd_reautoprecharge = `FALSE;
|
| 2487 |
|
|
$display("Warning: tRASmin violation at %t", $realtime);
|
| 2488 |
|
|
disable rd_autoprech_op;
|
| 2489 |
|
|
`endif
|
| 2490 |
|
|
end
|
| 2491 |
|
|
if(difftime > `tRASmax+`MARGIN)
|
| 2492 |
|
|
begin
|
| 2493 |
|
|
$display("Warning: tRASmax violation at %t", $realtime);
|
| 2494 |
|
|
end
|
| 2495 |
|
|
|
| 2496 |
|
|
`ifdef M16G4_M64G3
|
| 2497 |
|
|
if (tmp_reauto == `FALSE) begin
|
| 2498 |
|
|
`endif
|
| 2499 |
|
|
`ifdef v $display(">> auto precharge ( %0s) at %t", str, $realtime);
|
| 2500 |
|
|
`endif
|
| 2501 |
|
|
Mode[tmp_bank] = 0;
|
| 2502 |
|
|
|
| 2503 |
|
|
precharge_flag[tmp_bank] = `TRUE;
|
| 2504 |
|
|
rd_kill_bank = tmp_bank;
|
| 2505 |
|
|
->rd_precharge_flag_kill;
|
| 2506 |
|
|
//TPRE_P[tmp_bank] = $realtobits($realtime);
|
| 2507 |
|
|
case(tmp_bank)//TPRE_P
|
| 2508 |
|
|
'd0: TPRE_P0 = $realtime;
|
| 2509 |
|
|
'd1: TPRE_P1 = $realtime;
|
| 2510 |
|
|
'd2: TPRE_P2 = $realtime;
|
| 2511 |
|
|
'd3: TPRE_P3 = $realtime;
|
| 2512 |
|
|
endcase//TPRE_P
|
| 2513 |
|
|
`ifdef M16G4_M64G3
|
| 2514 |
|
|
end
|
| 2515 |
|
|
`endif
|
| 2516 |
|
|
end
|
| 2517 |
|
|
|
| 2518 |
|
|
/*
|
| 2519 |
|
|
*-----------------------------------------------------
|
| 2520 |
|
|
* WRITE AUTO PRECHARGE command
|
| 2521 |
|
|
*-----------------------------------------------------
|
| 2522 |
|
|
*/
|
| 2523 |
|
|
|
| 2524 |
|
|
always @(wr_autoprecharge or posedge wr_reautoprecharge)
|
| 2525 |
|
|
begin : wr_autoprech_op
|
| 2526 |
|
|
real difftime;
|
| 2527 |
|
|
integer bank_id;
|
| 2528 |
|
|
reg [8*8:1] str;
|
| 2529 |
|
|
reg tmp_reauto;
|
| 2530 |
|
|
integer prev_bank;
|
| 2531 |
|
|
integer tmp_bank;
|
| 2532 |
|
|
|
| 2533 |
|
|
tmp_reauto = `FALSE;
|
| 2534 |
|
|
bank_id = BankSelect(wr_autoprech_reg);
|
| 2535 |
|
|
if (wr_reautoprecharge == `TRUE) begin
|
| 2536 |
|
|
wr_reautoprecharge = `FALSE;
|
| 2537 |
|
|
tmp_bank = prev_bank;
|
| 2538 |
|
|
end
|
| 2539 |
|
|
else
|
| 2540 |
|
|
tmp_bank = bank_id;
|
| 2541 |
|
|
str = PrintBank(tmp_bank);
|
| 2542 |
|
|
//difftime = $realtime - $bitstoreal(TRAS_PP[tmp_bank]);
|
| 2543 |
|
|
case(tmp_bank)//TRAS_PP
|
| 2544 |
|
|
'd0: difftime = $realtime-TRAS_PP0;
|
| 2545 |
|
|
'd1: difftime = $realtime-TRAS_PP1;
|
| 2546 |
|
|
'd2: difftime = $realtime-TRAS_PP2;
|
| 2547 |
|
|
'd3: difftime = $realtime-TRAS_PP3;
|
| 2548 |
|
|
endcase//TRAS_PP
|
| 2549 |
|
|
if(difftime < `tRASmin-`MARGIN)
|
| 2550 |
|
|
begin
|
| 2551 |
|
|
`ifdef M64G3_M128_M256
|
| 2552 |
|
|
//auto_flagx <= `TRUE; // KyW ... 0624 : rev 3.3
|
| 2553 |
|
|
//auto_flagx <= #(`tRASmin-difftime) `FALSE; // KyW ... 0624 : rev 3.3
|
| 2554 |
|
|
prev_bank <= #(`tRASmin-difftime) tmp_bank;
|
| 2555 |
|
|
wr_reautoprecharge <= #(`tRASmin-difftime) `TRUE;
|
| 2556 |
|
|
tmp_reauto = `TRUE;
|
| 2557 |
|
|
`ifdef v $display(" Info: Staring Auto precharge (%s) delayed by tRASmin violation at %t", str, $time);
|
| 2558 |
|
|
`endif
|
| 2559 |
|
|
// #0 disable wr_autoprech_op;
|
| 2560 |
|
|
`else
|
| 2561 |
|
|
wr_reautoprecharge = `FALSE;
|
| 2562 |
|
|
$display("Warning: tRASmin violation at %t", $realtime);
|
| 2563 |
|
|
disable wr_autoprech_op;
|
| 2564 |
|
|
`endif
|
| 2565 |
|
|
end
|
| 2566 |
|
|
if(difftime > `tRASmax+`MARGIN)
|
| 2567 |
|
|
begin
|
| 2568 |
|
|
$display("Warning: tRASmax violation at %t", $realtime);
|
| 2569 |
|
|
end
|
| 2570 |
|
|
|
| 2571 |
|
|
`ifdef M16G4_M64G3
|
| 2572 |
|
|
if (tmp_reauto == `FALSE) begin
|
| 2573 |
|
|
`endif
|
| 2574 |
|
|
`ifdef v $display(">> auto precharge ( %0s) at %t", str, $realtime);
|
| 2575 |
|
|
`endif
|
| 2576 |
|
|
Mode[tmp_bank] = 0;
|
| 2577 |
|
|
|
| 2578 |
|
|
precharge_flag[tmp_bank] = `TRUE;
|
| 2579 |
|
|
wr_kill_bank = tmp_bank;
|
| 2580 |
|
|
->wr_precharge_flag_kill;
|
| 2581 |
|
|
//TPRE_P[tmp_bank] = $realtobits($realtime);
|
| 2582 |
|
|
case(tmp_bank)//TPRE_P
|
| 2583 |
|
|
'd0: TPRE_P0 = $realtime;
|
| 2584 |
|
|
'd1: TPRE_P1 = $realtime;
|
| 2585 |
|
|
'd2: TPRE_P2 = $realtime;
|
| 2586 |
|
|
'd3: TPRE_P3 = $realtime;
|
| 2587 |
|
|
endcase//TPRE_P
|
| 2588 |
|
|
`ifdef M16G4_M64G3
|
| 2589 |
|
|
end
|
| 2590 |
|
|
`endif
|
| 2591 |
|
|
end
|
| 2592 |
|
|
|
| 2593 |
|
|
/*
|
| 2594 |
|
|
*-----------------------------------------------------
|
| 2595 |
|
|
*/
|
| 2596 |
|
|
|
| 2597 |
|
|
always @(autostart)
|
| 2598 |
|
|
begin
|
| 2599 |
|
|
if( READ_MODE )
|
| 2600 |
|
|
begin
|
| 2601 |
|
|
auto_flagx = repeat (BL) @(negedge pclk) `FALSE;
|
| 2602 |
|
|
end
|
| 2603 |
|
|
else if( WRITE_MODE )
|
| 2604 |
|
|
begin
|
| 2605 |
|
|
auto_flagx = repeat (WBL) @(negedge pclk) `FALSE;
|
| 2606 |
|
|
end
|
| 2607 |
|
|
end
|
| 2608 |
|
|
/*
|
| 2609 |
|
|
*-----------------------------------------------------
|
| 2610 |
|
|
* DEEP POWER DOWN
|
| 2611 |
|
|
*-----------------------------------------------------
|
| 2612 |
|
|
*/
|
| 2613 |
|
|
`ifdef DPD
|
| 2614 |
|
|
always @(deeppowerdown)
|
| 2615 |
|
|
begin : d_powerdown
|
| 2616 |
|
|
if (|Mode == 1'b0) begin
|
| 2617 |
|
|
D_POWERDOWN = `TRUE;
|
| 2618 |
|
|
`ifdef v
|
| 2619 |
|
|
$display(">> Deep power down enter at %t",CUR_TIME);
|
| 2620 |
|
|
`endif
|
| 2621 |
|
|
end
|
| 2622 |
|
|
else begin
|
| 2623 |
|
|
$display("Warning: Illegal deep power down command at %t",CUR_TIME);
|
| 2624 |
|
|
disable d_powerdown;
|
| 2625 |
|
|
end
|
| 2626 |
|
|
end
|
| 2627 |
|
|
|
| 2628 |
|
|
always @(d_pdown_exit) begin
|
| 2629 |
|
|
D_POWERDOWN <= #(`tDPDEXIT-`MARGIN) `FALSE;
|
| 2630 |
|
|
D_PDOWN_EXIT <= #(`tDPDEXIT-`MARGIN) `TRUE;
|
| 2631 |
|
|
end
|
| 2632 |
|
|
`endif
|
| 2633 |
|
|
|
| 2634 |
|
|
/*
|
| 2635 |
|
|
*-----------------------------------------------------
|
| 2636 |
|
|
* move memory data to dout register
|
| 2637 |
|
|
* by sequential counter
|
| 2638 |
|
|
*-----------------------------------------------------
|
| 2639 |
|
|
*/
|
| 2640 |
|
|
|
| 2641 |
|
|
// This task models behavior of increment counter
|
| 2642 |
|
|
// Simply, address is increased by one and one.
|
| 2643 |
|
|
|
| 2644 |
|
|
task increment_read;
|
| 2645 |
|
|
begin:ir
|
| 2646 |
|
|
integer j,s,t;
|
| 2647 |
|
|
integer bank;
|
| 2648 |
|
|
reg [`BIT_T] maddr;
|
| 2649 |
|
|
reg [`BIT_C] check_111;
|
| 2650 |
|
|
|
| 2651 |
|
|
bank = BankSelect(c_bank_addr);
|
| 2652 |
|
|
|
| 2653 |
|
|
maddr = m_addr;
|
| 2654 |
|
|
for(j=0; j<= BL-1; j=j+1) begin
|
| 2655 |
|
|
|
| 2656 |
|
|
case(bank)
|
| 2657 |
|
|
'd0: begin
|
| 2658 |
|
|
`ifdef DYMEM
|
| 2659 |
|
|
$damem_read("mem_a", maddr, dout_reg[j]);
|
| 2660 |
|
|
$damem_read("mem_a", maddr, din_rega[j]);
|
| 2661 |
|
|
`else
|
| 2662 |
|
|
dout_reg[j] = mem_a[maddr];
|
| 2663 |
|
|
din_rega[j] = mem_a[maddr];
|
| 2664 |
|
|
`endif
|
| 2665 |
|
|
end
|
| 2666 |
|
|
'd1: begin
|
| 2667 |
|
|
`ifdef DYMEM
|
| 2668 |
|
|
`ifdef MOBILE
|
| 2669 |
|
|
if (REF1BANK == `TRUE) dout_reg[j] = `B'bx;
|
| 2670 |
|
|
else
|
| 2671 |
|
|
$damem_read("mem_b", maddr, dout_reg[j]);
|
| 2672 |
|
|
`else
|
| 2673 |
|
|
$damem_read("mem_b", maddr, dout_reg[j]);
|
| 2674 |
|
|
`endif
|
| 2675 |
|
|
$damem_read("mem_b", maddr, din_regb[j]);
|
| 2676 |
|
|
`else
|
| 2677 |
|
|
`ifdef MOBILE
|
| 2678 |
|
|
if (REF1BANK == `TRUE) dout_reg[j] = `B'bx;
|
| 2679 |
|
|
else
|
| 2680 |
|
|
dout_reg[j] = mem_b[maddr];
|
| 2681 |
|
|
`else
|
| 2682 |
|
|
dout_reg[j] = mem_b[maddr];
|
| 2683 |
|
|
`endif
|
| 2684 |
|
|
din_regb[j] = mem_b[maddr];
|
| 2685 |
|
|
`endif
|
| 2686 |
|
|
end
|
| 2687 |
|
|
`ifdef NBANK4
|
| 2688 |
|
|
'd2: begin
|
| 2689 |
|
|
`ifdef DYMEM
|
| 2690 |
|
|
`ifdef MOBILE
|
| 2691 |
|
|
if (REF4BANK == `FALSE) dout_reg[j] = `B'bx;
|
| 2692 |
|
|
else
|
| 2693 |
|
|
$damem_read("mem_c", maddr, dout_reg[j]);
|
| 2694 |
|
|
`else
|
| 2695 |
|
|
$damem_read("mem_c", maddr, dout_reg[j]);
|
| 2696 |
|
|
`endif
|
| 2697 |
|
|
$damem_read("mem_c", maddr, din_regc[j]);
|
| 2698 |
|
|
`else
|
| 2699 |
|
|
`ifdef MOBILE
|
| 2700 |
|
|
if (REF4BANK == `FALSE) dout_reg[j] = `B'bx;
|
| 2701 |
|
|
else
|
| 2702 |
|
|
dout_reg[j] = mem_c[maddr];
|
| 2703 |
|
|
`else
|
| 2704 |
|
|
dout_reg[j] = mem_c[maddr];
|
| 2705 |
|
|
`endif
|
| 2706 |
|
|
din_regc[j] = mem_c[maddr];
|
| 2707 |
|
|
`endif
|
| 2708 |
|
|
end
|
| 2709 |
|
|
'd3: begin
|
| 2710 |
|
|
`ifdef DYMEM
|
| 2711 |
|
|
`ifdef MOBILE
|
| 2712 |
|
|
if (REF4BANK == `FALSE) dout_reg[j] = `B'bx;
|
| 2713 |
|
|
else
|
| 2714 |
|
|
$damem_read("mem_d", maddr, dout_reg[j]);
|
| 2715 |
|
|
`else
|
| 2716 |
|
|
$damem_read("mem_d", maddr, dout_reg[j]);
|
| 2717 |
|
|
`endif
|
| 2718 |
|
|
$damem_read("mem_d", maddr, din_regd[j]);
|
| 2719 |
|
|
`else
|
| 2720 |
|
|
`ifdef MOBILE
|
| 2721 |
|
|
if (REF4BANK == `FALSE) dout_reg[j] = `B'bx;
|
| 2722 |
|
|
else
|
| 2723 |
|
|
dout_reg[j] = mem_d[maddr];
|
| 2724 |
|
|
`else
|
| 2725 |
|
|
dout_reg[j] = mem_d[maddr];
|
| 2726 |
|
|
`endif
|
| 2727 |
|
|
din_regd[j] = mem_d[maddr];
|
| 2728 |
|
|
`endif
|
| 2729 |
|
|
end
|
| 2730 |
|
|
`endif
|
| 2731 |
|
|
endcase
|
| 2732 |
|
|
|
| 2733 |
|
|
case(BL)
|
| 2734 |
|
|
'd1: begin
|
| 2735 |
|
|
end
|
| 2736 |
|
|
'd2: maddr[0] = ~maddr[0];
|
| 2737 |
|
|
'd4: begin
|
| 2738 |
|
|
check_111 = m_addr + j+1;
|
| 2739 |
|
|
maddr[1:0] = check_111[1:0];
|
| 2740 |
|
|
end
|
| 2741 |
|
|
'd8: begin
|
| 2742 |
|
|
check_111 = m_addr + j+1;
|
| 2743 |
|
|
maddr[2:0] = check_111[2:0];
|
| 2744 |
|
|
end
|
| 2745 |
|
|
`PAGEDEPTH: begin // case 256
|
| 2746 |
|
|
check_111 = m_addr + j+1;
|
| 2747 |
|
|
maddr[`BIT_C] = check_111[`BIT_C];
|
| 2748 |
|
|
end
|
| 2749 |
|
|
default: begin
|
| 2750 |
|
|
$display("Warning: burst length is out of spec");
|
| 2751 |
|
|
disable increment_read;
|
| 2752 |
|
|
end
|
| 2753 |
|
|
endcase
|
| 2754 |
|
|
end // end of for loop
|
| 2755 |
|
|
|
| 2756 |
|
|
end
|
| 2757 |
|
|
endtask
|
| 2758 |
|
|
|
| 2759 |
|
|
/*
|
| 2760 |
|
|
*-----------------------------------------------------
|
| 2761 |
|
|
* move memory data to dout register
|
| 2762 |
|
|
* by interleave counter
|
| 2763 |
|
|
*-----------------------------------------------------
|
| 2764 |
|
|
*/
|
| 2765 |
|
|
|
| 2766 |
|
|
// Interleave counting mechanism is different from
|
| 2767 |
|
|
// sequential method. Counting step could be varied with
|
| 2768 |
|
|
// initial address.(refer to data sheet)
|
| 2769 |
|
|
|
| 2770 |
|
|
task interleave_read;
|
| 2771 |
|
|
begin:ir1
|
| 2772 |
|
|
integer j;
|
| 2773 |
|
|
integer bank;
|
| 2774 |
|
|
reg [`BIT_T] maddr;
|
| 2775 |
|
|
|
| 2776 |
|
|
bank = BankSelect(c_bank_addr);
|
| 2777 |
|
|
maddr = m_addr;
|
| 2778 |
|
|
for(j=0; j<=BL-1; j=j+1) begin
|
| 2779 |
|
|
case(bank)
|
| 2780 |
|
|
'd0: begin
|
| 2781 |
|
|
`ifdef DYMEM
|
| 2782 |
|
|
$damem_read("mem_a", maddr, dout_reg[j]);
|
| 2783 |
|
|
$damem_read("mem_a", maddr, din_rega[j]);
|
| 2784 |
|
|
`else
|
| 2785 |
|
|
dout_reg[j] = mem_a[maddr];
|
| 2786 |
|
|
din_rega[j] = mem_a[maddr];
|
| 2787 |
|
|
`endif
|
| 2788 |
|
|
end
|
| 2789 |
|
|
'd1: begin
|
| 2790 |
|
|
`ifdef DYMEM
|
| 2791 |
|
|
`ifdef MOBILE
|
| 2792 |
|
|
if (REF1BANK == `TRUE) dout_reg[j] = `B'bx;
|
| 2793 |
|
|
else
|
| 2794 |
|
|
$damem_read("mem_b", maddr, dout_reg[j]);
|
| 2795 |
|
|
`else
|
| 2796 |
|
|
$damem_read("mem_b", maddr, dout_reg[j]);
|
| 2797 |
|
|
`endif
|
| 2798 |
|
|
$damem_read("mem_b", maddr, din_regb[j]);
|
| 2799 |
|
|
`else
|
| 2800 |
|
|
`ifdef MOBILE
|
| 2801 |
|
|
if (REF1BANK == `TRUE) dout_reg[j] = `B'bx;
|
| 2802 |
|
|
else
|
| 2803 |
|
|
dout_reg[j] = mem_b[maddr];
|
| 2804 |
|
|
`else
|
| 2805 |
|
|
dout_reg[j] = mem_b[maddr];
|
| 2806 |
|
|
`endif
|
| 2807 |
|
|
din_regb[j] = mem_b[maddr];
|
| 2808 |
|
|
`endif
|
| 2809 |
|
|
end
|
| 2810 |
|
|
`ifdef NBANK4
|
| 2811 |
|
|
'd2: begin
|
| 2812 |
|
|
`ifdef DYMEM
|
| 2813 |
|
|
`ifdef MOBILE
|
| 2814 |
|
|
if (REF4BANK == `FALSE) dout_reg[j] = `B'bx;
|
| 2815 |
|
|
else
|
| 2816 |
|
|
$damem_read("mem_c", maddr, dout_reg[j]);
|
| 2817 |
|
|
`else
|
| 2818 |
|
|
$damem_read("mem_c", maddr, dout_reg[j]);
|
| 2819 |
|
|
`endif
|
| 2820 |
|
|
$damem_read("mem_c", maddr, din_regc[j]);
|
| 2821 |
|
|
`else
|
| 2822 |
|
|
`ifdef MOBILE
|
| 2823 |
|
|
if (REF4BANK == `FALSE) dout_reg[j] = `B'bx;
|
| 2824 |
|
|
else
|
| 2825 |
|
|
dout_reg[j] = mem_c[maddr];
|
| 2826 |
|
|
`else
|
| 2827 |
|
|
dout_reg[j] = mem_c[maddr];
|
| 2828 |
|
|
`endif
|
| 2829 |
|
|
din_regc[j] = mem_c[maddr];
|
| 2830 |
|
|
`endif
|
| 2831 |
|
|
end
|
| 2832 |
|
|
'd3: begin
|
| 2833 |
|
|
`ifdef DYMEM
|
| 2834 |
|
|
`ifdef MOBILE
|
| 2835 |
|
|
if (REF4BANK == `FALSE) dout_reg[j] = `B'bx;
|
| 2836 |
|
|
else
|
| 2837 |
|
|
$damem_read("mem_d", maddr, dout_reg[j]);
|
| 2838 |
|
|
`else
|
| 2839 |
|
|
$damem_read("mem_d", maddr, dout_reg[j]);
|
| 2840 |
|
|
`endif
|
| 2841 |
|
|
$damem_read("mem_d", maddr, din_regd[j]);
|
| 2842 |
|
|
`else
|
| 2843 |
|
|
`ifdef MOBILE
|
| 2844 |
|
|
if (REF4BANK == `FALSE) dout_reg[j] = `B'bx;
|
| 2845 |
|
|
else
|
| 2846 |
|
|
dout_reg[j] = mem_d[maddr];
|
| 2847 |
|
|
`else
|
| 2848 |
|
|
dout_reg[j] = mem_d[maddr];
|
| 2849 |
|
|
`endif
|
| 2850 |
|
|
din_regd[j] = mem_d[maddr];
|
| 2851 |
|
|
`endif
|
| 2852 |
|
|
end
|
| 2853 |
|
|
`endif
|
| 2854 |
|
|
endcase
|
| 2855 |
|
|
|
| 2856 |
|
|
case(BL)
|
| 2857 |
|
|
'd1:begin
|
| 2858 |
|
|
end
|
| 2859 |
|
|
'd2:
|
| 2860 |
|
|
maddr[0] = ~maddr[0];
|
| 2861 |
|
|
'd4: begin
|
| 2862 |
|
|
if( j == 0 || j == 2)
|
| 2863 |
|
|
maddr[0] = ~maddr[0];
|
| 2864 |
|
|
else
|
| 2865 |
|
|
maddr[1:0] = ~maddr[1:0];
|
| 2866 |
|
|
end
|
| 2867 |
|
|
'd8: begin
|
| 2868 |
|
|
if(j == 0 || j == 2 || j == 4 || j==6)
|
| 2869 |
|
|
maddr[0] = ~maddr[0];
|
| 2870 |
|
|
else if(j == 1 || j == 5)
|
| 2871 |
|
|
maddr[1:0] = ~maddr[1:0];
|
| 2872 |
|
|
else
|
| 2873 |
|
|
maddr[2:0] = ~maddr[2:0];
|
| 2874 |
|
|
end
|
| 2875 |
|
|
default: $display("Warning: burst length is out of spec.");
|
| 2876 |
|
|
endcase
|
| 2877 |
|
|
end
|
| 2878 |
|
|
end
|
| 2879 |
|
|
endtask
|
| 2880 |
|
|
|
| 2881 |
|
|
/*
|
| 2882 |
|
|
*-----------------------------------------------------
|
| 2883 |
|
|
* move memory data to din register array
|
| 2884 |
|
|
* by sequential counter
|
| 2885 |
|
|
*-----------------------------------------------------
|
| 2886 |
|
|
*/
|
| 2887 |
|
|
|
| 2888 |
|
|
task increment_write;
|
| 2889 |
|
|
begin:iw
|
| 2890 |
|
|
integer j,s,t;
|
| 2891 |
|
|
reg [`BIT_T] maddr;
|
| 2892 |
|
|
reg [`BIT_C] check_111;
|
| 2893 |
|
|
integer bank;
|
| 2894 |
|
|
|
| 2895 |
|
|
bank = BankSelect(c_bank_addr);
|
| 2896 |
|
|
maddr = m_addr;
|
| 2897 |
|
|
for(j=0; j<=WBL-1; j=j+1) begin
|
| 2898 |
|
|
case(bank)
|
| 2899 |
|
|
'd0:
|
| 2900 |
|
|
`ifdef DYMEM
|
| 2901 |
|
|
$damem_write("mem_a", maddr, din_rega[j]);
|
| 2902 |
|
|
`else
|
| 2903 |
|
|
mem_a[maddr] = din_rega[j];
|
| 2904 |
|
|
`endif
|
| 2905 |
|
|
'd1:
|
| 2906 |
|
|
`ifdef DYMEM
|
| 2907 |
|
|
$damem_write("mem_b", maddr, din_regb[j]);
|
| 2908 |
|
|
`else
|
| 2909 |
|
|
mem_b[maddr] = din_regb[j];
|
| 2910 |
|
|
`endif
|
| 2911 |
|
|
`ifdef NBANK4
|
| 2912 |
|
|
'd2:
|
| 2913 |
|
|
`ifdef DYMEM
|
| 2914 |
|
|
$damem_write("mem_c", maddr, din_regc[j]);
|
| 2915 |
|
|
`else
|
| 2916 |
|
|
mem_c[maddr] = din_regc[j];
|
| 2917 |
|
|
`endif
|
| 2918 |
|
|
'd3:
|
| 2919 |
|
|
`ifdef DYMEM
|
| 2920 |
|
|
$damem_write("mem_d", maddr, din_regd[j]);
|
| 2921 |
|
|
`else
|
| 2922 |
|
|
mem_d[maddr] = din_regd[j];
|
| 2923 |
|
|
`endif
|
| 2924 |
|
|
`endif
|
| 2925 |
|
|
endcase
|
| 2926 |
|
|
case(WBL)
|
| 2927 |
|
|
'd1: begin
|
| 2928 |
|
|
end
|
| 2929 |
|
|
'd2:
|
| 2930 |
|
|
maddr[0] = ~maddr[0];
|
| 2931 |
|
|
'd4: begin
|
| 2932 |
|
|
check_111 = m_addr +j+1;
|
| 2933 |
|
|
maddr[1:0] = check_111[1:0];
|
| 2934 |
|
|
end
|
| 2935 |
|
|
'd8: begin
|
| 2936 |
|
|
check_111 = m_addr +j+1;
|
| 2937 |
|
|
maddr[2:0] = check_111[2:0];
|
| 2938 |
|
|
end
|
| 2939 |
|
|
`PAGEDEPTH: begin
|
| 2940 |
|
|
check_111 = m_addr +j+1;
|
| 2941 |
|
|
maddr[`BIT_C] = check_111[`BIT_C];
|
| 2942 |
|
|
end
|
| 2943 |
|
|
default: begin
|
| 2944 |
|
|
$display("Warning: burst length is out of spec");
|
| 2945 |
|
|
disable increment_write;
|
| 2946 |
|
|
end
|
| 2947 |
|
|
endcase
|
| 2948 |
|
|
end
|
| 2949 |
|
|
end
|
| 2950 |
|
|
endtask
|
| 2951 |
|
|
|
| 2952 |
|
|
/*
|
| 2953 |
|
|
*-----------------------------------------------------
|
| 2954 |
|
|
* move memory data to din register array
|
| 2955 |
|
|
* by interleave counter
|
| 2956 |
|
|
*-----------------------------------------------------
|
| 2957 |
|
|
*/
|
| 2958 |
|
|
|
| 2959 |
|
|
task interleave_write;
|
| 2960 |
|
|
begin:iw1
|
| 2961 |
|
|
integer j;
|
| 2962 |
|
|
integer bank;
|
| 2963 |
|
|
reg [`BIT_T] maddr;
|
| 2964 |
|
|
|
| 2965 |
|
|
bank = BankSelect(c_bank_addr);
|
| 2966 |
|
|
maddr = m_addr;
|
| 2967 |
|
|
for(j=0; j <= WBL-1; j=j+1) begin
|
| 2968 |
|
|
case(bank)
|
| 2969 |
|
|
'd0:
|
| 2970 |
|
|
`ifdef DYMEM
|
| 2971 |
|
|
$damem_write("mem_a", maddr, din_rega[j]);
|
| 2972 |
|
|
`else
|
| 2973 |
|
|
mem_a[maddr] = din_rega[j];
|
| 2974 |
|
|
`endif
|
| 2975 |
|
|
'd1:
|
| 2976 |
|
|
`ifdef DYMEM
|
| 2977 |
|
|
$damem_write("mem_b", maddr, din_regb[j]);
|
| 2978 |
|
|
`else
|
| 2979 |
|
|
mem_b[maddr] = din_regb[j];
|
| 2980 |
|
|
`endif
|
| 2981 |
|
|
`ifdef NBANK4
|
| 2982 |
|
|
'd2:
|
| 2983 |
|
|
`ifdef DYMEM
|
| 2984 |
|
|
$damem_write("mem_c", maddr, din_regc[j]);
|
| 2985 |
|
|
`else
|
| 2986 |
|
|
mem_c[maddr] = din_regc[j];
|
| 2987 |
|
|
`endif
|
| 2988 |
|
|
'd3:
|
| 2989 |
|
|
`ifdef DYMEM
|
| 2990 |
|
|
$damem_write("mem_d", maddr, din_regd[j]);
|
| 2991 |
|
|
`else
|
| 2992 |
|
|
mem_d[maddr] = din_regd[j];
|
| 2993 |
|
|
`endif
|
| 2994 |
|
|
`endif
|
| 2995 |
|
|
endcase
|
| 2996 |
|
|
case(WBL)
|
| 2997 |
|
|
'd1:begin
|
| 2998 |
|
|
end
|
| 2999 |
|
|
'd2:
|
| 3000 |
|
|
maddr[0] = ~maddr[0];
|
| 3001 |
|
|
'd4: begin
|
| 3002 |
|
|
if((j % 2) == 0)
|
| 3003 |
|
|
maddr[0] = ~maddr[0];
|
| 3004 |
|
|
else
|
| 3005 |
|
|
maddr[1:0] = ~maddr[1:0];
|
| 3006 |
|
|
end
|
| 3007 |
|
|
'd8: begin
|
| 3008 |
|
|
if((j % 2) == 0)
|
| 3009 |
|
|
maddr[0] = ~maddr[0];
|
| 3010 |
|
|
else if(j == 1 || j == 5)
|
| 3011 |
|
|
maddr[1:0] = ~maddr[1:0];
|
| 3012 |
|
|
else
|
| 3013 |
|
|
maddr[2:0] = ~maddr[2:0];
|
| 3014 |
|
|
end
|
| 3015 |
|
|
default:
|
| 3016 |
|
|
begin
|
| 3017 |
|
|
$display("Warning: burst length is out of spec.");
|
| 3018 |
|
|
end
|
| 3019 |
|
|
endcase
|
| 3020 |
|
|
end
|
| 3021 |
|
|
end
|
| 3022 |
|
|
endtask
|
| 3023 |
|
|
|
| 3024 |
|
|
`protect
|
| 3025 |
|
|
|
| 3026 |
|
|
/*
|
| 3027 |
|
|
*-----------------------------------------------------
|
| 3028 |
|
|
* precharge interrupt
|
| 3029 |
|
|
*-----------------------------------------------------
|
| 3030 |
|
|
*/
|
| 3031 |
|
|
always @(precharge_start)
|
| 3032 |
|
|
begin: pc_start
|
| 3033 |
|
|
integer bank_id;
|
| 3034 |
|
|
reg [8*8:1] str;
|
| 3035 |
|
|
|
| 3036 |
|
|
if( READ_MODE == `TRUE )
|
| 3037 |
|
|
begin
|
| 3038 |
|
|
bank_id = BankSelect(c_bank_addr);
|
| 3039 |
|
|
str = PrintBank(c_bank_addr);
|
| 3040 |
|
|
if(precharge_flag[bank_id])
|
| 3041 |
|
|
begin
|
| 3042 |
|
|
`ifdef v $display("-- read operation interrupted by precharge");
|
| 3043 |
|
|
`endif
|
| 3044 |
|
|
READ_MODE = `FALSE;
|
| 3045 |
|
|
disable read_block;
|
| 3046 |
|
|
end
|
| 3047 |
|
|
end
|
| 3048 |
|
|
if( WRITE_MODE == `TRUE )
|
| 3049 |
|
|
begin
|
| 3050 |
|
|
bank_id = BankSelect(c_bank_addr);
|
| 3051 |
|
|
str = PrintBank(c_bank_addr);
|
| 3052 |
|
|
if(precharge_flag[bank_id])
|
| 3053 |
|
|
begin
|
| 3054 |
|
|
`ifdef v $display("-- write operation interrupted by precharge");
|
| 3055 |
|
|
`endif
|
| 3056 |
|
|
for (i = 0; i < `nDQM; i = i + 1) begin : dqm_high_check
|
| 3057 |
|
|
if(dqm[i] == `FALSE) begin
|
| 3058 |
|
|
`ifdef v $display(" DQM must be high at %t", CUR_TIME);
|
| 3059 |
|
|
`endif
|
| 3060 |
|
|
i = `nDQM;
|
| 3061 |
|
|
end
|
| 3062 |
|
|
end
|
| 3063 |
|
|
WRITE_MODE = `FALSE;
|
| 3064 |
|
|
disable write_block;
|
| 3065 |
|
|
end
|
| 3066 |
|
|
end
|
| 3067 |
|
|
end
|
| 3068 |
|
|
|
| 3069 |
|
|
always @(precharge_flag_kill) begin
|
| 3070 |
|
|
if (prech_reg[0] == `TRUE) begin
|
| 3071 |
|
|
for (i = 0; i < `nBank; i = i+1)
|
| 3072 |
|
|
precharge_flag[i] <= #(`tRP-1) `FALSE;
|
| 3073 |
|
|
end
|
| 3074 |
|
|
else begin
|
| 3075 |
|
|
if( precharge_flag[kill_bank] )
|
| 3076 |
|
|
precharge_flag[kill_bank] <= #(`tRP-1) `FALSE;
|
| 3077 |
|
|
end
|
| 3078 |
|
|
end
|
| 3079 |
|
|
always @(rd_precharge_flag_kill) begin
|
| 3080 |
|
|
if (prech_reg[0] == `TRUE) begin
|
| 3081 |
|
|
for (i = 0; i < `nBank; i = i+1)
|
| 3082 |
|
|
precharge_flag[i] <= #(`tRP-1) `FALSE;
|
| 3083 |
|
|
end
|
| 3084 |
|
|
else begin
|
| 3085 |
|
|
if( precharge_flag[rd_kill_bank] )
|
| 3086 |
|
|
precharge_flag[rd_kill_bank] <= #(`tRP-1) `FALSE;
|
| 3087 |
|
|
end
|
| 3088 |
|
|
end
|
| 3089 |
|
|
always @(wr_precharge_flag_kill) begin
|
| 3090 |
|
|
if (prech_reg[0] == `TRUE) begin
|
| 3091 |
|
|
for (i = 0; i < `nBank; i = i+1)
|
| 3092 |
|
|
precharge_flag[i] <= #(`tRP-1) `FALSE;
|
| 3093 |
|
|
end
|
| 3094 |
|
|
else begin
|
| 3095 |
|
|
if( precharge_flag[wr_kill_bank] )
|
| 3096 |
|
|
precharge_flag[wr_kill_bank] <= #(`tRP-1) `FALSE;
|
| 3097 |
|
|
end
|
| 3098 |
|
|
end
|
| 3099 |
|
|
`endprotect
|
| 3100 |
|
|
|
| 3101 |
|
|
/*
|
| 3102 |
|
|
*-----------------------------------------------------
|
| 3103 |
|
|
* read task
|
| 3104 |
|
|
*-----------------------------------------------------
|
| 3105 |
|
|
*/
|
| 3106 |
|
|
|
| 3107 |
|
|
task read_task;
|
| 3108 |
|
|
|
| 3109 |
|
|
begin
|
| 3110 |
|
|
|
| 3111 |
|
|
begin: read_op
|
| 3112 |
|
|
integer i;
|
| 3113 |
|
|
|
| 3114 |
|
|
for( i=0; i < BL; i=i+1 )
|
| 3115 |
|
|
begin
|
| 3116 |
|
|
t_dqo = dout_reg[i];
|
| 3117 |
|
|
->dqo_event;
|
| 3118 |
|
|
@(posedge pclk);
|
| 3119 |
|
|
`ifdef M16G4_M64G3 // jhkim(8.14)
|
| 3120 |
|
|
if( i == `PAGEDEPTH - 1 )
|
| 3121 |
|
|
i = -1; // full page wrap around
|
| 3122 |
|
|
`endif
|
| 3123 |
|
|
end
|
| 3124 |
|
|
end
|
| 3125 |
|
|
|
| 3126 |
|
|
end
|
| 3127 |
|
|
endtask
|
| 3128 |
|
|
|
| 3129 |
|
|
/*
|
| 3130 |
|
|
*-----------------------------------------------------
|
| 3131 |
|
|
* write task
|
| 3132 |
|
|
*-----------------------------------------------------
|
| 3133 |
|
|
*/
|
| 3134 |
|
|
|
| 3135 |
|
|
task write_task;
|
| 3136 |
|
|
begin
|
| 3137 |
|
|
begin: write_op
|
| 3138 |
|
|
integer i, j, k;
|
| 3139 |
|
|
reg [`BIT] tmp_reg;
|
| 3140 |
|
|
integer bank_id;
|
| 3141 |
|
|
reg [8*8:1] str;
|
| 3142 |
|
|
|
| 3143 |
|
|
if(~burst_type)
|
| 3144 |
|
|
increment_read;
|
| 3145 |
|
|
else
|
| 3146 |
|
|
interleave_read;
|
| 3147 |
|
|
|
| 3148 |
|
|
begin: write_seq
|
| 3149 |
|
|
for(i = 0; i < WBL; i = i+1)
|
| 3150 |
|
|
begin // { for loop
|
| 3151 |
|
|
begin
|
| 3152 |
|
|
bank_id = BankSelect(c_bank_addr);
|
| 3153 |
|
|
str = PrintBank(c_bank_addr);
|
| 3154 |
|
|
if(precharge_flag[bank_id] == `TRUE)
|
| 3155 |
|
|
disable write_seq;
|
| 3156 |
|
|
case (bank_id)
|
| 3157 |
|
|
'd0: tmp_reg = din_rega[i];
|
| 3158 |
|
|
'd1: tmp_reg = din_regb[i];
|
| 3159 |
|
|
`ifdef NBANK4
|
| 3160 |
|
|
'd2: tmp_reg = din_regc[i];
|
| 3161 |
|
|
'd3: tmp_reg = din_regd[i];
|
| 3162 |
|
|
`endif
|
| 3163 |
|
|
endcase
|
| 3164 |
|
|
|
| 3165 |
|
|
|
| 3166 |
|
|
for (k = 0; k < `nDQM; k = k + 1) begin
|
| 3167 |
|
|
if (dqm[k] == 1'b0) begin
|
| 3168 |
|
|
for (j = k*`BYTE; j < (k+1)*`BYTE; j = j + 1) begin
|
| 3169 |
|
|
tmp_reg[j] = (dqi[j] == 1'b1 || dqi[j] == 1'b0)?
|
| 3170 |
|
|
dqi[j]:1'bx;
|
| 3171 |
|
|
end
|
| 3172 |
|
|
end
|
| 3173 |
|
|
end
|
| 3174 |
|
|
|
| 3175 |
|
|
case (bank_id)
|
| 3176 |
|
|
'd0: din_rega[i] = tmp_reg;
|
| 3177 |
|
|
'd1: din_regb[i] = tmp_reg;
|
| 3178 |
|
|
`ifdef NBANK4
|
| 3179 |
|
|
'd2: din_regc[i] = tmp_reg;
|
| 3180 |
|
|
'd3: din_regd[i] = tmp_reg;
|
| 3181 |
|
|
`endif
|
| 3182 |
|
|
endcase
|
| 3183 |
|
|
end
|
| 3184 |
|
|
|
| 3185 |
|
|
m_addr = {r_addr, c_addr};
|
| 3186 |
|
|
#0 ->flush_write;
|
| 3187 |
|
|
|
| 3188 |
|
|
`ifdef M16G4_M64G3 // jhkim(8.14)
|
| 3189 |
|
|
if( i == WBL-1 && WBL !== `PAGEDEPTH )
|
| 3190 |
|
|
disable write_seq;
|
| 3191 |
|
|
`else
|
| 3192 |
|
|
if( i == WBL-1 && i != `PAGEDEPTH )
|
| 3193 |
|
|
disable write_seq;
|
| 3194 |
|
|
`endif
|
| 3195 |
|
|
@(posedge pclk);
|
| 3196 |
|
|
#0.1; //KyW ... 0408 for VCS
|
| 3197 |
|
|
if( |dqm === 1'b0 ) begin // 98.6.26 BYC
|
| 3198 |
|
|
if( CUR_TIME - TDQI < `tSS-`MARGIN )
|
| 3199 |
|
|
$display("Warning: DQi setup violation at %t", CUR_TIME);
|
| 3200 |
|
|
end
|
| 3201 |
|
|
`ifdef M16G4_M64G3 // jhkim(8.14)
|
| 3202 |
|
|
if ( i == `PAGEDEPTH -1)
|
| 3203 |
|
|
i = -1; // full page wrap around
|
| 3204 |
|
|
`endif
|
| 3205 |
|
|
|
| 3206 |
|
|
end // } for loop end
|
| 3207 |
|
|
end // write_seq
|
| 3208 |
|
|
|
| 3209 |
|
|
// m_addr = {r_addr, c_addr};
|
| 3210 |
|
|
// ->flush_write;
|
| 3211 |
|
|
|
| 3212 |
|
|
end
|
| 3213 |
|
|
|
| 3214 |
|
|
end
|
| 3215 |
|
|
|
| 3216 |
|
|
endtask
|
| 3217 |
|
|
|
| 3218 |
|
|
`ifdef NBANK2
|
| 3219 |
|
|
function integer BankSelect;
|
| 3220 |
|
|
input c_addr;
|
| 3221 |
|
|
integer bank;
|
| 3222 |
|
|
begin
|
| 3223 |
|
|
case(c_addr)
|
| 3224 |
|
|
1'b0 :
|
| 3225 |
|
|
bank = 0;
|
| 3226 |
|
|
1'b1 :
|
| 3227 |
|
|
bank = 1;
|
| 3228 |
|
|
default :
|
| 3229 |
|
|
bank = -1;
|
| 3230 |
|
|
endcase
|
| 3231 |
|
|
BankSelect = bank;
|
| 3232 |
|
|
end
|
| 3233 |
|
|
endfunction
|
| 3234 |
|
|
function [8*8 : 1] PrintBank;
|
| 3235 |
|
|
input bs;
|
| 3236 |
|
|
reg [8*8 : 1] s_bank;
|
| 3237 |
|
|
begin
|
| 3238 |
|
|
case(bs)
|
| 3239 |
|
|
1'b0 :
|
| 3240 |
|
|
s_bank = " A Bank";
|
| 3241 |
|
|
1'b1 :
|
| 3242 |
|
|
s_bank = " B Bank";
|
| 3243 |
|
|
default :
|
| 3244 |
|
|
s_bank = "Bad Bank";
|
| 3245 |
|
|
endcase
|
| 3246 |
|
|
PrintBank = s_bank;
|
| 3247 |
|
|
end
|
| 3248 |
|
|
endfunction
|
| 3249 |
|
|
`endif
|
| 3250 |
|
|
|
| 3251 |
|
|
`ifdef NBANK4
|
| 3252 |
|
|
function integer BankSelect;
|
| 3253 |
|
|
input [1:0] c_addr;
|
| 3254 |
|
|
integer bank;
|
| 3255 |
|
|
begin
|
| 3256 |
|
|
case(c_addr)
|
| 3257 |
|
|
2'b00 :
|
| 3258 |
|
|
bank = 0;
|
| 3259 |
|
|
2'b01 :
|
| 3260 |
|
|
bank = 1;
|
| 3261 |
|
|
2'b10 :
|
| 3262 |
|
|
bank = 2;
|
| 3263 |
|
|
2'b11 :
|
| 3264 |
|
|
bank = 3;
|
| 3265 |
|
|
default :
|
| 3266 |
|
|
bank = -1;
|
| 3267 |
|
|
endcase
|
| 3268 |
|
|
BankSelect = bank;
|
| 3269 |
|
|
end
|
| 3270 |
|
|
endfunction
|
| 3271 |
|
|
function [8*8 : 1] PrintBank;
|
| 3272 |
|
|
input [1:0] bs;
|
| 3273 |
|
|
reg [8*8 : 1] s_bank;
|
| 3274 |
|
|
begin
|
| 3275 |
|
|
case(bs)
|
| 3276 |
|
|
2'b00 :
|
| 3277 |
|
|
s_bank = " A Bank";
|
| 3278 |
|
|
2'b01 :
|
| 3279 |
|
|
s_bank = " B Bank";
|
| 3280 |
|
|
2'b10 :
|
| 3281 |
|
|
s_bank = " C Bank";
|
| 3282 |
|
|
2'b11 :
|
| 3283 |
|
|
s_bank = " D Bank";
|
| 3284 |
|
|
default :
|
| 3285 |
|
|
s_bank = "Bad Bank";
|
| 3286 |
|
|
endcase
|
| 3287 |
|
|
PrintBank = s_bank;
|
| 3288 |
|
|
end
|
| 3289 |
|
|
endfunction
|
| 3290 |
|
|
`endif
|
| 3291 |
|
|
|
| 3292 |
|
|
endmodule
|
| 3293 |
|
|
|
| 3294 |
|
|
`ifdef CS2
|
| 3295 |
|
|
`ifdef DPD_PIN
|
| 3296 |
|
|
module sdram(clk, cs0b, cs1b, cke, ba, ad, rasb, casb, web, dqm, dqi, dpdb);
|
| 3297 |
|
|
`else
|
| 3298 |
|
|
module sdram(clk, cs0b, cs1b, cke, ba, ad, rasb, casb, web, dqm, dqi);
|
| 3299 |
|
|
`endif
|
| 3300 |
|
|
|
| 3301 |
|
|
inout [`BIT] dqi;
|
| 3302 |
|
|
input [`nBank/2-1:0] ba;
|
| 3303 |
|
|
input [`ADDRTOP:0] ad;
|
| 3304 |
|
|
input rasb,casb,web;
|
| 3305 |
|
|
input clk,cke,cs0b,cs1b;
|
| 3306 |
|
|
input [`nDQM-1:0] dqm;
|
| 3307 |
|
|
|
| 3308 |
|
|
`ifdef DPD_PIN
|
| 3309 |
|
|
input dpdb;
|
| 3310 |
|
|
`endif
|
| 3311 |
|
|
|
| 3312 |
|
|
`ifdef DPD_PIN
|
| 3313 |
|
|
sdram_cs2 i0(clk, cs0b, cke, ba, ad, rasb, casb, web, dqm, dqi, dpdb);
|
| 3314 |
|
|
sdram_cs2 i1(clk, cs1b, cke, ba, ad, rasb, casb, web, dqm, dqi, dpdb);
|
| 3315 |
|
|
`else
|
| 3316 |
|
|
sdram_cs2 i0(clk, cs0b, cke, ba, ad, rasb, casb, web, dqm, dqi);
|
| 3317 |
|
|
sdram_cs2 i1(clk, cs1b, cke, ba, ad, rasb, casb, web, dqm, dqi);
|
| 3318 |
|
|
`endif
|
| 3319 |
|
|
endmodule
|
| 3320 |
|
|
`endif
|
| 3321 |
|
|
|
| 3322 |
|
|
`ifdef CS2_CKE2
|
| 3323 |
|
|
`ifdef DPD_PIN
|
| 3324 |
|
|
module sdram(clk, cs0b, cs1b, cke0, cke1, ba, ad, rasb, casb, web, dqm, dqi, dpdb);
|
| 3325 |
|
|
`else
|
| 3326 |
|
|
module sdram(clk, cs0b, cs1b, cke0, cke1, ba, ad, rasb, casb, web, dqm, dqi);
|
| 3327 |
|
|
`endif
|
| 3328 |
|
|
|
| 3329 |
|
|
inout [`BIT] dqi;
|
| 3330 |
|
|
input [`nBank/2-1:0] ba;
|
| 3331 |
|
|
input [`ADDRTOP:0] ad;
|
| 3332 |
|
|
input rasb,casb,web;
|
| 3333 |
|
|
input clk,cke0,cke1,cs0b,cs1b;
|
| 3334 |
|
|
input [`nDQM-1:0] dqm;
|
| 3335 |
|
|
|
| 3336 |
|
|
`ifdef DPD_PIN
|
| 3337 |
|
|
input dpdb;
|
| 3338 |
|
|
`endif
|
| 3339 |
|
|
|
| 3340 |
|
|
`ifdef DPD_PIN
|
| 3341 |
|
|
sdram_cs2 i0(clk, cs0b, cke0, ba, ad, rasb, casb, web, dqm, dqi, dpdb);
|
| 3342 |
|
|
sdram_cs2 i1(clk, cs1b, cke1, ba, ad, rasb, casb, web, dqm, dqi, dpdb);
|
| 3343 |
|
|
`else
|
| 3344 |
|
|
sdram_cs2 i0(clk, cs0b, cke0, ba, ad, rasb, casb, web, dqm, dqi);
|
| 3345 |
|
|
sdram_cs2 i1(clk, cs1b, cke1, ba, ad, rasb, casb, web, dqm, dqi);
|
| 3346 |
|
|
`endif
|
| 3347 |
|
|
endmodule
|
| 3348 |
|
|
`endif
|
| 3349 |
|
|
|
