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[/] [eco32/] [trunk/] [fpga/] [experiments/] [memctrl/] [sim/] [memctrl-1/] [ramctrl/] [ramctrl.v] - Blame information for rev 323

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//
// ramctrl.v -- RAM controller
//
 
 
`include "ramctrl/k4s561632e.v"
 
 
`timescale 1ns/10ps
`default_nettype none
 
 
`define MODE            13'h0032        // CL = 3, sequ. burst length = 4
 
`define CMD_MRSET       3'b000          // mode register set
`define CMD_ARFRS       3'b001          // auto refresh
`define CMD_PRCHG       3'b010          // precharge (deactivate row/rows)
`define CMD_ACTV        3'b011          // select bank, activate row
`define CMD_WRITE       3'b100          // select bank & column, start write
`define CMD_READ        3'b101          // select bank & column, start read
`define CMD_BSTOP       3'b110          // burst stop
`define CMD_NOP         3'b111          // no operation
 
//
// Note: The FSM is a registered Mealy machine. Its actions, which
//       are noted here for a specific state, take place in the next
//       clock cycle. This is only a notational problem: the actions
//       should in fact be associated with state transitions.
//
// ST_RESET                             // NOP, CKE=0, CS_N=1, wait 100 us
`define ST_INIT0        5'd0            // NOP, CKE=1, CS_N=0, wait 100 us
`define ST_INIT1        5'd1            // PRECHARGE ALL
`define ST_INIT2        5'd2            // NOP, wait tRP - 1 cycle
`define ST_INIT3        5'd3            // AUTO REFRESH
`define ST_INIT4        5'd4            // NOP, wait tRFC - 1 cycle
`define ST_INIT5        5'd5            // AUTO REFRESH
`define ST_INIT6        5'd6            // NOP, wait tRFC - 1 cycle
`define ST_INIT7        5'd7            // MODE REGISTER SET
`define ST_INIT8        5'd8            // NOP, wait tMRD - 1 cycle
`define ST_IDLE         5'd9            // AUTO REFRESH, ACTIVE, or NOP
`define ST_RFRSH        5'd10           // NOP, wait tRFC - 1 cycle
`define ST_WRDATA0      5'd11           // NOP, wait tRCD - 1 cycle
`define ST_WRDATA1      5'd12           // WRITE, de=1
`define ST_WRDATA2      5'd13           // NOP, wait 3 cycles
`define ST_WRDATA3      5'd14           // NOP, ack=1, de=0
`define ST_WRDATA4      5'd15           // NOP, ack=0, wait 3 cycles
`define ST_RDDATA0      5'd16           // NOP, wait tRCD - 1 cycle
`define ST_RDDATA1      5'd17           // READ
`define ST_RDDATA2      5'd18           // NOP, wait 2 cycles
`define ST_RDDATA3      5'd19           // NOP, ld=1, wait 4 cycles
`define ST_RDDATA4      5'd20           // NOP, ack=1, ld=0
`define ST_RDDATA5      5'd21           // NOP, ack=0, wait 4 cycles
`define ST_RDINST0      5'd22           // NOP, wait tRCD - 1 cycle
`define ST_RDINST1      5'd23           // READ
`define ST_RDINST2      5'd24           // NOP, wait 2 cycles
`define ST_RDINST3      5'd25           // NOP, ld=1, wait 4 cycles
`define ST_RDINST4      5'd26           // NOP, ack=1, ld=0
`define ST_RDINST5      5'd27           // NOP, ack=0, wait 4 cycles
`define ST_ILLDA0       5'd28           // NOP, data_timeout=1
`define ST_ILLDA1       5'd29           // NOP, data_timeout=0
`define ST_ILLIA0       5'd30           // NOP, inst_timeout=1
`define ST_ILLIA1       5'd31           // NOP, inst_timeout=0
 
`define T_INIT0         14'd10000       // min 100 usec with CKE = 0
`define T_INIT1         14'd10000       // min 100 usec with CKE = 1
`define T_RP            14'd3           // min 20 ns row precharge time
`define T_RFC           14'd9           // min 66 ns auto refresh period
`define T_MRD           14'd3           // min load mode register delay
`define T_RCD           14'd3           // min 20 ns active-to-rw delay
 
`define REFCNT          10'd780          // 8192 refresh cycles per 64 ms
 
 
module ramctrl(clk_ok, clk,
               inst_stb, inst_addr,
               inst_dout, inst_ack,
               inst_timeout,
               data_stb, data_we,
               data_addr, data_din,
               data_dout, data_ack,
               data_timeout);
    input clk_ok;
    input clk;
    input inst_stb;
    input [25:0] inst_addr;
    output [63:0] inst_dout;
    output reg inst_ack;
    output reg inst_timeout;
    input data_stb;
    input data_we;
    input [25:0] data_addr;
    input [63:0] data_din;
    output [63:0] data_dout;
    output reg data_ack;
    output reg data_timeout;
 
  wire sdram_clk;
  wire sdram_clk_aux;
  reg sdram_cke;
  reg sdram_cs_n;
  wire sdram_ras_n;
  wire sdram_cas_n;
  wire sdram_we_n;
  reg [1:0] sdram_ba;
  reg [12:0] sdram_a;
  wire [1:0] sdram_dqm;
  wire [15:0] sdram_dq;
 
  reg [1:0] ram_cnt;
  wire [15:0] ram_dout;
  reg ram_de;
  reg [63:0] data;
  reg data_ld;
 
  wire inst_addr_out_of_range;
  wire data_addr_out_of_range;
 
  reg [2:0] ram_cmd;
  reg [1:0] ram_dqm;
  reg [13:0] count;
  reg [4:0] state;
 
  reg [9:0] refcnt;
  reg refflg;
  reg refrst;
 
  //
  // create ram instance
  //
 
  sdram sdram_1(
    .clk(sdram_clk),
    .cke(sdram_cke),
    .csb(sdram_cs_n),
    .rasb(sdram_ras_n),
    .casb(sdram_cas_n),
    .web(sdram_we_n),
    .ba(sdram_ba[1:0]),
    .ad(sdram_a[12:0]),
    .dqm(sdram_dqm[1:0]),
    .dqi(sdram_dq[15:0])
  );
 
  //
  // clock output to ram
  // the necessary phase shift will be accomplished by
  // a DLL if the controller is implemented on an FPGA
  //
 
  not #4 not_1(sdram_clk_aux, clk);
  not #5 not_2(sdram_clk, sdram_clk_aux);
 
  //
  // data output to ram
  //
 
  assign ram_dout[15:0] =
    ~ram_cnt[1] ? (~ram_cnt[0] ? data_din[63:48] : data_din[47:32]) :
                  (~ram_cnt[0] ? data_din[31:16] : data_din[15: 0]);
  assign sdram_dq[15:0] = ram_de ? ram_dout[15:0] : 16'hzzzz;
 
  //
  // data output to cache
  //
 
  always @(posedge clk) begin
    if (data_ld & (ram_cnt[1:0] == 2'b00)) begin
      data[63:48] <= sdram_dq[15:0];
    end
    if (data_ld & (ram_cnt[1:0] == 2'b01)) begin
      data[47:32] <= sdram_dq[15:0];
    end
    if (data_ld & (ram_cnt[1:0] == 2'b10)) begin
      data[31:16] <= sdram_dq[15:0];
    end
    if (data_ld & (ram_cnt[1:0] == 2'b11)) begin
      data[15: 0] <= sdram_dq[15:0];
    end
  end
 
  assign inst_dout[63:0] = data[63:0];
  assign data_dout[63:0] = data[63:0];
 
  //
  // address range check
  //
 
  assign inst_addr_out_of_range = | inst_addr[25:22];
  assign data_addr_out_of_range = | data_addr[25:22];
 
  //
  // ramctrl state machine
  //
 
  assign sdram_ras_n = ram_cmd[2];
  assign sdram_cas_n = ram_cmd[1];
  assign sdram_we_n = ram_cmd[0];
 
  assign sdram_dqm[1] = ram_dqm[1];
  assign sdram_dqm[0] = ram_dqm[0];
 
  always @(posedge clk or negedge clk_ok) begin
    // asynchronous reset
    if (~clk_ok) begin
      inst_ack <= 0;
      inst_timeout <= 0;
      data_ack <= 0;
      data_timeout <= 0;
      sdram_cke <= 0;
      sdram_cs_n <= 1;
      ram_cnt <= 0;
      ram_de <= 0;
      data_ld <= 0;
      ram_cmd <= `CMD_NOP;
      ram_dqm <= 2'b11;
      count <= `T_INIT0 - 1;
      state <= `ST_INIT0;
      refrst <= 0;
    end else begin
      if (|count[13:0]) begin
        // wait until count = 0
        // if count is loaded with N on a state transition, the
        // new state will last for (N+1)/fclk cycles before (!)
        // any action specified in the new state will take place
        count <= count - 1;
        // ram_cnt cycles through the 16-bit half-words in SDRAM
        // during burst read/writes while the main state machine
        // waits, thus it must be incremented here
        ram_cnt <= ram_cnt + 1;
      end else begin
        case (state)
          //----------------------------
          // init
          //----------------------------
          `ST_INIT0:
            begin
              sdram_cke <= 1;
              sdram_cs_n <= 0;
              ram_cmd <= `CMD_NOP;
              count <= `T_INIT1 - 1;
              state <= `ST_INIT1;
            end
          `ST_INIT1:
            begin
              ram_cmd <= `CMD_PRCHG;
              sdram_ba <= 2'b00;        // don't care
              sdram_a <= 13'h0400;      // precharge all
              state <= `ST_INIT2;
            end
          `ST_INIT2:
            begin
              ram_cmd <= `CMD_NOP;
              count <= `T_RP - 2;
              state <= `ST_INIT3;
            end
          `ST_INIT3:
            begin
              ram_cmd <= `CMD_ARFRS;
              state <= `ST_INIT4;
            end
          `ST_INIT4:
            begin
              ram_cmd <= `CMD_NOP;
              count <= `T_RFC - 2;
              state <= `ST_INIT5;
            end
          `ST_INIT5:
            begin
              ram_cmd <= `CMD_ARFRS;
              state <= `ST_INIT6;
            end
          `ST_INIT6:
            begin
              ram_cmd <= `CMD_NOP;
              count <= `T_RFC - 2;
              state <= `ST_INIT7;
            end
          `ST_INIT7:
            begin
              ram_cmd <= `CMD_MRSET;
              sdram_ba <= 2'b00;
              sdram_a <= `MODE;
              state <= `ST_INIT8;
            end
          `ST_INIT8:
            begin
              ram_cmd <= `CMD_NOP;
              ram_dqm <= 2'b00;
              count <= `T_MRD - 2;
              state <= `ST_IDLE;
            end
          //----------------------------
          // idle
          //----------------------------
          `ST_IDLE:
            begin
              if (refflg) begin
                // refresh request
                ram_cmd <= `CMD_ARFRS;
                state <= `ST_RFRSH;
                refrst <= 1;
              end else begin
                if (data_stb) begin
                  if (data_addr_out_of_range) begin
                    // illegal data address
                    ram_cmd <= `CMD_NOP;
                    state <= `ST_ILLDA0;
                  end else begin
                    // data address is ok
                    if (data_we) begin
                      // data write request
                      ram_cmd <= `CMD_ACTV;
                      sdram_ba <= data_addr[21:20];
                      sdram_a <= data_addr[19:7];
                      state <= `ST_WRDATA0;
                    end else begin
                      // data read request
                      ram_cmd <= `CMD_ACTV;
                      sdram_ba <= data_addr[21:20];
                      sdram_a <= data_addr[19:7];
                      state <= `ST_RDDATA0;
                    end
                  end
                end else begin
                  if (inst_stb) begin
                    if (inst_addr_out_of_range) begin
                      // illegal inst address
                      ram_cmd <= `CMD_NOP;
                      state <= `ST_ILLIA0;
                    end else begin
                      // inst address is ok
                      // inst read request
                      ram_cmd <= `CMD_ACTV;
                      sdram_ba <= inst_addr[21:20];
                      sdram_a <= inst_addr[19:7];
                      state <= `ST_RDINST0;
                    end
                  end else begin
                    // no request
                    ram_cmd <= `CMD_NOP;
                    state <= `ST_IDLE;
                  end
                end
              end
            end
          //----------------------------
          // refresh
          //----------------------------
          `ST_RFRSH:
            begin
              ram_cmd <= `CMD_NOP;
              count <= `T_RFC - 2;
              state <= `ST_IDLE;
              refrst <= 0;
            end
          //----------------------------
          // write data
          //----------------------------
          `ST_WRDATA0:
            begin
              ram_cmd <= `CMD_NOP;
              count <= `T_RCD - 2;
              state <= `ST_WRDATA1;
            end
          `ST_WRDATA1:
            begin
              ram_cnt <= 0;
              ram_de <= 1;
              ram_cmd <= `CMD_WRITE;
              sdram_ba <= data_addr[21:20];
              sdram_a <= { 6'b0010, data_addr[6:0], 2'b00 };
              state <= `ST_WRDATA2;
            end
          `ST_WRDATA2:
            begin
              ram_cnt <= ram_cnt + 1;
              ram_cmd <= `CMD_NOP;
              count <= 2;
              state <= `ST_WRDATA3;
            end
          `ST_WRDATA3:
            begin
              data_ack <= 1;
              ram_de <= 0;
              ram_cmd <= `CMD_NOP;
              state <= `ST_WRDATA4;
            end
          `ST_WRDATA4:
            begin
              data_ack <= 0;
              ram_cmd <= `CMD_NOP;
              count <= 2;
              state <= `ST_IDLE;
            end
          //----------------------------
          // read data
          //----------------------------
          `ST_RDDATA0:
            begin
              ram_cmd <= `CMD_NOP;
              count <= `T_RCD - 2;
              state <= `ST_RDDATA1;
            end
          `ST_RDDATA1:
            begin
              ram_cmd <= `CMD_READ;
              sdram_ba <= data_addr[21:20];
              sdram_a <= { 6'b0010, data_addr[6:0], 2'b00 };
              state <= `ST_RDDATA2;
            end
          `ST_RDDATA2:
            begin
              ram_cmd <= `CMD_NOP;
              count <= 1;
              state <= `ST_RDDATA3;
            end
          `ST_RDDATA3:
            begin
              ram_cnt <= 0;
              data_ld <= 1;
              ram_cmd <= `CMD_NOP;
              count <= 3;
              state <= `ST_RDDATA4;
            end
          `ST_RDDATA4:
            begin
              data_ack <= 1;
              data_ld <= 0;
              ram_cmd <= `CMD_NOP;
              state <= `ST_RDDATA5;
            end
          `ST_RDDATA5:
            begin
              data_ack <= 0;
              ram_cmd <= `CMD_NOP;
              count <= 3;
              state <= `ST_IDLE;
            end
          //----------------------------
          // read inst
          //----------------------------
          `ST_RDINST0:
            begin
              ram_cmd <= `CMD_NOP;
              count <= `T_RCD - 2;
              state <= `ST_RDINST1;
            end
          `ST_RDINST1:
            begin
              ram_cmd <= `CMD_READ;
              sdram_ba <= inst_addr[21:20];
              sdram_a <= { 6'b0010, inst_addr[6:0], 2'b00 };
              state <= `ST_RDINST2;
            end
          `ST_RDINST2:
            begin
              ram_cmd <= `CMD_NOP;
              count <= 1;
              state <= `ST_RDINST3;
            end
          `ST_RDINST3:
            begin
              ram_cnt <= 0;
              data_ld <= 1;
              ram_cmd <= `CMD_NOP;
              count <= 3;
              state <= `ST_RDINST4;
            end
          `ST_RDINST4:
            begin
              inst_ack <= 1;
              data_ld <= 0;
              ram_cmd <= `CMD_NOP;
              state <= `ST_RDINST5;
            end
          `ST_RDINST5:
            begin
              inst_ack <= 0;
              ram_cmd <= `CMD_NOP;
              count <= 3;
              state <= `ST_IDLE;
            end
          //----------------------------
          // illegal data address
          //----------------------------
          `ST_ILLDA0:
            begin
              data_timeout <= 1;
              ram_cmd <= `CMD_NOP;
              state <= `ST_ILLDA1;
            end
          `ST_ILLDA1:
            begin
              data_timeout <= 0;
              ram_cmd <= `CMD_NOP;
              state <= `ST_IDLE;
            end
          //----------------------------
          // illegal inst address
          //----------------------------
          `ST_ILLIA0:
            begin
              inst_timeout <= 1;
              ram_cmd <= `CMD_NOP;
              state <= `ST_ILLIA1;
            end
          `ST_ILLIA1:
            begin
              inst_timeout <= 0;
              ram_cmd <= `CMD_NOP;
              state <= `ST_IDLE;
            end
          //----------------------------
          // not used
          //----------------------------
          default:
            begin
              inst_ack <= 0;
              inst_timeout <= 0;
              data_ack <= 0;
              data_timeout <= 0;
              sdram_cke <= 0;
              sdram_cs_n <= 1;
              ram_cnt <= 0;
              ram_de <= 0;
              data_ld <= 0;
              ram_cmd <= `CMD_NOP;
              ram_dqm <= 2'b11;
              count <= `T_INIT0 - 1;
              state <= `ST_INIT0;
              refrst <= 0;
            end
        endcase
      end
    end
  end
 
  //
  // refresh counter
  //
 
  always @(posedge clk or negedge clk_ok) begin
    if (~clk_ok) begin
      refcnt <= 10'd0;
    end else begin
      if (refcnt == 10'd0) begin
        refcnt <= `REFCNT;
        refflg <= 1;
      end else begin
        refcnt <= refcnt - 1;
        if (refrst) begin
          refflg <= 0;
        end
      end
    end
  end
 
endmodule

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[/] [eco32/] [trunk/] [fpga/] [experiments/] [memctrl/] [sim/] [memctrl-1/] [ramctrl/] [ramctrl.v] - Blame information for rev 323

Line No.	Rev	Author	Line
1	313	hellwig	`//`
2			`// ramctrl.v -- RAM controller`
3			`//`
4
5
6			`include "ramctrl/k4s561632e.v"
7
8
9			`timescale 1ns/10ps
10			`default_nettype none
11
12
13			`define MODE 13'h0032 // CL = 3, sequ. burst length = 4
14
15			`define CMD_MRSET 3'b000 // mode register set
16			`define CMD_ARFRS 3'b001 // auto refresh
17			`define CMD_PRCHG 3'b010 // precharge (deactivate row/rows)
18			`define CMD_ACTV 3'b011 // select bank, activate row
19			`define CMD_WRITE 3'b100 // select bank & column, start write
20			`define CMD_READ 3'b101 // select bank & column, start read
21			`define CMD_BSTOP 3'b110 // burst stop
22			`define CMD_NOP 3'b111 // no operation
23
24			`//`
25			`// Note: The FSM is a registered Mealy machine. Its actions, which`
26			`// are noted here for a specific state, take place in the next`
27			`// clock cycle. This is only a notational problem: the actions`
28			`// should in fact be associated with state transitions.`
29			`//`
30			`// ST_RESET // NOP, CKE=0, CS_N=1, wait 100 us`
31			`define ST_INIT0 5'd0 // NOP, CKE=1, CS_N=0, wait 100 us
32			`define ST_INIT1 5'd1 // PRECHARGE ALL
33			`define ST_INIT2 5'd2 // NOP, wait tRP - 1 cycle
34			`define ST_INIT3 5'd3 // AUTO REFRESH
35			`define ST_INIT4 5'd4 // NOP, wait tRFC - 1 cycle
36			`define ST_INIT5 5'd5 // AUTO REFRESH
37			`define ST_INIT6 5'd6 // NOP, wait tRFC - 1 cycle
38			`define ST_INIT7 5'd7 // MODE REGISTER SET
39			`define ST_INIT8 5'd8 // NOP, wait tMRD - 1 cycle
40			`define ST_IDLE 5'd9 // AUTO REFRESH, ACTIVE, or NOP
41			`define ST_RFRSH 5'd10 // NOP, wait tRFC - 1 cycle
42			`define ST_WRDATA0 5'd11 // NOP, wait tRCD - 1 cycle
43			`define ST_WRDATA1 5'd12 // WRITE, de=1
44			`define ST_WRDATA2 5'd13 // NOP, wait 3 cycles
45			`define ST_WRDATA3 5'd14 // NOP, ack=1, de=0
46			`define ST_WRDATA4 5'd15 // NOP, ack=0, wait 3 cycles
47			`define ST_RDDATA0 5'd16 // NOP, wait tRCD - 1 cycle
48			`define ST_RDDATA1 5'd17 // READ
49			`define ST_RDDATA2 5'd18 // NOP, wait 2 cycles
50			`define ST_RDDATA3 5'd19 // NOP, ld=1, wait 4 cycles
51			`define ST_RDDATA4 5'd20 // NOP, ack=1, ld=0
52			`define ST_RDDATA5 5'd21 // NOP, ack=0, wait 4 cycles
53			`define ST_RDINST0 5'd22 // NOP, wait tRCD - 1 cycle
54			`define ST_RDINST1 5'd23 // READ
55			`define ST_RDINST2 5'd24 // NOP, wait 2 cycles
56			`define ST_RDINST3 5'd25 // NOP, ld=1, wait 4 cycles
57			`define ST_RDINST4 5'd26 // NOP, ack=1, ld=0
58			`define ST_RDINST5 5'd27 // NOP, ack=0, wait 4 cycles
59			`define ST_ILLDA0 5'd28 // NOP, data_timeout=1
60			`define ST_ILLDA1 5'd29 // NOP, data_timeout=0
61			`define ST_ILLIA0 5'd30 // NOP, inst_timeout=1
62			`define ST_ILLIA1 5'd31 // NOP, inst_timeout=0
63
64			`define T_INIT0 14'd10000 // min 100 usec with CKE = 0
65			`define T_INIT1 14'd10000 // min 100 usec with CKE = 1
66			`define T_RP 14'd3 // min 20 ns row precharge time
67			`define T_RFC 14'd9 // min 66 ns auto refresh period
68			`define T_MRD 14'd3 // min load mode register delay
69			`define T_RCD 14'd3 // min 20 ns active-to-rw delay
70
71			`define REFCNT 10'd780 // 8192 refresh cycles per 64 ms
72
73
74			`module ramctrl(clk_ok, clk,`
75			`inst_stb, inst_addr,`
76			`inst_dout, inst_ack,`
77			`inst_timeout,`
78			`data_stb, data_we,`
79			`data_addr, data_din,`
80			`data_dout, data_ack,`
81			`data_timeout);`
82			`input clk_ok;`
83			`input clk;`
84			`input inst_stb;`
85			`input [25:0] inst_addr;`
86			`output [63:0] inst_dout;`
87			`output reg inst_ack;`
88			`output reg inst_timeout;`
89			`input data_stb;`
90			`input data_we;`
91			`input [25:0] data_addr;`
92			`input [63:0] data_din;`
93			`output [63:0] data_dout;`
94			`output reg data_ack;`
95			`output reg data_timeout;`
96
97			`wire sdram_clk;`
98			`wire sdram_clk_aux;`
99			`reg sdram_cke;`
100			`reg sdram_cs_n;`
101			`wire sdram_ras_n;`
102			`wire sdram_cas_n;`
103			`wire sdram_we_n;`
104			`reg [1:0] sdram_ba;`
105			`reg [12:0] sdram_a;`
106			`wire [1:0] sdram_dqm;`
107			`wire [15:0] sdram_dq;`
108
109			`reg [1:0] ram_cnt;`
110			`wire [15:0] ram_dout;`
111			`reg ram_de;`
112			`reg [63:0] data;`
113			`reg data_ld;`
114
115			`wire inst_addr_out_of_range;`
116			`wire data_addr_out_of_range;`
117
118			`reg [2:0] ram_cmd;`
119			`reg [1:0] ram_dqm;`
120			`reg [13:0] count;`
121			`reg [4:0] state;`
122
123			`reg [9:0] refcnt;`
124			`reg refflg;`
125			`reg refrst;`
126
127			`//`
128			`// create ram instance`
129			`//`
130
131			`sdram sdram_1(`
132			`.clk(sdram_clk),`
133			`.cke(sdram_cke),`
134			`.csb(sdram_cs_n),`
135			`.rasb(sdram_ras_n),`
136			`.casb(sdram_cas_n),`
137			`.web(sdram_we_n),`
138			`.ba(sdram_ba[1:0]),`
139			`.ad(sdram_a[12:0]),`
140			`.dqm(sdram_dqm[1:0]),`
141			`.dqi(sdram_dq[15:0])`
142			`);`
143
144			`//`
145			`// clock output to ram`
146			`// the necessary phase shift will be accomplished by`
147			`// a DLL if the controller is implemented on an FPGA`
148			`//`
149
150			`not #4 not_1(sdram_clk_aux, clk);`
151			`not #5 not_2(sdram_clk, sdram_clk_aux);`
152
153			`//`
154			`// data output to ram`
155			`//`
156
157			`assign ram_dout[15:0] =`
158			`~ram_cnt[1] ? (~ram_cnt[0] ? data_din[63:48] : data_din[47:32]) :`
159			`(~ram_cnt[0] ? data_din[31:16] : data_din[15: 0]);`
160			`assign sdram_dq[15:0] = ram_de ? ram_dout[15:0] : 16'hzzzz;`
161
162			`//`
163			`// data output to cache`
164			`//`
165
166			`always @(posedge clk) begin`
167			`if (data_ld & (ram_cnt[1:0] == 2'b00)) begin`
168			`data[63:48] <= sdram_dq[15:0];`
169			`end`
170			`if (data_ld & (ram_cnt[1:0] == 2'b01)) begin`
171			`data[47:32] <= sdram_dq[15:0];`
172			`end`
173			`if (data_ld & (ram_cnt[1:0] == 2'b10)) begin`
174			`data[31:16] <= sdram_dq[15:0];`
175			`end`
176			`if (data_ld & (ram_cnt[1:0] == 2'b11)) begin`
177			`data[15: 0] <= sdram_dq[15:0];`
178			`end`
179			`end`
180
181			`assign inst_dout[63:0] = data[63:0];`
182			`assign data_dout[63:0] = data[63:0];`
183
184			`//`
185			`// address range check`
186			`//`
187
188			`assign inst_addr_out_of_range = \| inst_addr[25:22];`
189			`assign data_addr_out_of_range = \| data_addr[25:22];`
190
191			`//`
192			`// ramctrl state machine`
193			`//`
194
195			`assign sdram_ras_n = ram_cmd[2];`
196			`assign sdram_cas_n = ram_cmd[1];`
197			`assign sdram_we_n = ram_cmd[0];`
198
199			`assign sdram_dqm[1] = ram_dqm[1];`
200			`assign sdram_dqm[0] = ram_dqm[0];`
201
202			`always @(posedge clk or negedge clk_ok) begin`
203			`// asynchronous reset`
204			`if (~clk_ok) begin`
205			`inst_ack <= 0;`
206			`inst_timeout <= 0;`
207			`data_ack <= 0;`
208			`data_timeout <= 0;`
209			`sdram_cke <= 0;`
210			`sdram_cs_n <= 1;`
211			`ram_cnt <= 0;`
212			`ram_de <= 0;`
213			`data_ld <= 0;`
214			ram_cmd <= `CMD_NOP;
215			`ram_dqm <= 2'b11;`
216			count <= `T_INIT0 - 1;
217			state <= `ST_INIT0;
218			`refrst <= 0;`
219			`end else begin`
220			`if (\|count[13:0]) begin`
221			`// wait until count = 0`
222			`// if count is loaded with N on a state transition, the`
223			`// new state will last for (N+1)/fclk cycles before (!)`
224			`// any action specified in the new state will take place`
225			`count <= count - 1;`
226			`// ram_cnt cycles through the 16-bit half-words in SDRAM`
227			`// during burst read/writes while the main state machine`
228			`// waits, thus it must be incremented here`
229			`ram_cnt <= ram_cnt + 1;`
230			`end else begin`
231			`case (state)`
232			`//----------------------------`
233			`// init`
234			`//----------------------------`
235			`ST_INIT0:
236			`begin`
237			`sdram_cke <= 1;`
238			`sdram_cs_n <= 0;`
239			ram_cmd <= `CMD_NOP;
240			count <= `T_INIT1 - 1;
241			state <= `ST_INIT1;
242			`end`
243			`ST_INIT1:
244			`begin`
245			ram_cmd <= `CMD_PRCHG;
246			`sdram_ba <= 2'b00; // don't care`
247			`sdram_a <= 13'h0400; // precharge all`
248			state <= `ST_INIT2;
249			`end`
250			`ST_INIT2:
251			`begin`
252			ram_cmd <= `CMD_NOP;
253			count <= `T_RP - 2;
254			state <= `ST_INIT3;
255			`end`
256			`ST_INIT3:
257			`begin`
258			ram_cmd <= `CMD_ARFRS;
259			state <= `ST_INIT4;
260			`end`
261			`ST_INIT4:
262			`begin`
263			ram_cmd <= `CMD_NOP;
264			count <= `T_RFC - 2;
265			state <= `ST_INIT5;
266			`end`
267			`ST_INIT5:
268			`begin`
269			ram_cmd <= `CMD_ARFRS;
270			state <= `ST_INIT6;
271			`end`
272			`ST_INIT6:
273			`begin`
274			ram_cmd <= `CMD_NOP;
275			count <= `T_RFC - 2;
276			state <= `ST_INIT7;
277			`end`
278			`ST_INIT7:
279			`begin`
280			ram_cmd <= `CMD_MRSET;
281			`sdram_ba <= 2'b00;`
282			sdram_a <= `MODE;
283			state <= `ST_INIT8;
284			`end`
285			`ST_INIT8:
286			`begin`
287			ram_cmd <= `CMD_NOP;
288			`ram_dqm <= 2'b00;`
289			count <= `T_MRD - 2;
290			state <= `ST_IDLE;
291			`end`
292			`//----------------------------`
293			`// idle`
294			`//----------------------------`
295			`ST_IDLE:
296			`begin`
297			`if (refflg) begin`
298			`// refresh request`
299			ram_cmd <= `CMD_ARFRS;
300			state <= `ST_RFRSH;
301			`refrst <= 1;`
302			`end else begin`
303			`if (data_stb) begin`
304			`if (data_addr_out_of_range) begin`
305			`// illegal data address`
306			ram_cmd <= `CMD_NOP;
307			state <= `ST_ILLDA0;
308			`end else begin`
309			`// data address is ok`
310			`if (data_we) begin`
311			`// data write request`
312			ram_cmd <= `CMD_ACTV;
313			`sdram_ba <= data_addr[21:20];`
314			`sdram_a <= data_addr[19:7];`
315			state <= `ST_WRDATA0;
316			`end else begin`
317			`// data read request`
318			ram_cmd <= `CMD_ACTV;
319			`sdram_ba <= data_addr[21:20];`
320			`sdram_a <= data_addr[19:7];`
321			state <= `ST_RDDATA0;
322			`end`
323			`end`
324			`end else begin`
325			`if (inst_stb) begin`
326			`if (inst_addr_out_of_range) begin`
327			`// illegal inst address`
328			ram_cmd <= `CMD_NOP;
329			state <= `ST_ILLIA0;
330			`end else begin`
331			`// inst address is ok`
332			`// inst read request`
333			ram_cmd <= `CMD_ACTV;
334			`sdram_ba <= inst_addr[21:20];`
335			`sdram_a <= inst_addr[19:7];`
336			state <= `ST_RDINST0;
337			`end`
338			`end else begin`
339			`// no request`
340			ram_cmd <= `CMD_NOP;
341			state <= `ST_IDLE;
342			`end`
343			`end`
344			`end`
345			`end`
346			`//----------------------------`
347			`// refresh`
348			`//----------------------------`
349			`ST_RFRSH:
350			`begin`
351			ram_cmd <= `CMD_NOP;
352			count <= `T_RFC - 2;
353			state <= `ST_IDLE;
354			`refrst <= 0;`
355			`end`
356			`//----------------------------`
357			`// write data`
358			`//----------------------------`
359			`ST_WRDATA0:
360			`begin`
361			ram_cmd <= `CMD_NOP;
362			count <= `T_RCD - 2;
363			state <= `ST_WRDATA1;
364			`end`
365			`ST_WRDATA1:
366			`begin`
367			`ram_cnt <= 0;`
368			`ram_de <= 1;`
369			ram_cmd <= `CMD_WRITE;
370			`sdram_ba <= data_addr[21:20];`
371			`sdram_a <= { 6'b0010, data_addr[6:0], 2'b00 };`
372			state <= `ST_WRDATA2;
373			`end`
374			`ST_WRDATA2:
375			`begin`
376			`ram_cnt <= ram_cnt + 1;`
377			ram_cmd <= `CMD_NOP;
378			`count <= 2;`
379			state <= `ST_WRDATA3;
380			`end`
381			`ST_WRDATA3:
382			`begin`
383			`data_ack <= 1;`
384			`ram_de <= 0;`
385			ram_cmd <= `CMD_NOP;
386			state <= `ST_WRDATA4;
387			`end`
388			`ST_WRDATA4:
389			`begin`
390			`data_ack <= 0;`
391			ram_cmd <= `CMD_NOP;
392			`count <= 2;`
393			state <= `ST_IDLE;
394			`end`
395			`//----------------------------`
396			`// read data`
397			`//----------------------------`
398			`ST_RDDATA0:
399			`begin`
400			ram_cmd <= `CMD_NOP;
401			count <= `T_RCD - 2;
402			state <= `ST_RDDATA1;
403			`end`
404			`ST_RDDATA1:
405			`begin`
406			ram_cmd <= `CMD_READ;
407			`sdram_ba <= data_addr[21:20];`
408			`sdram_a <= { 6'b0010, data_addr[6:0], 2'b00 };`
409			state <= `ST_RDDATA2;
410			`end`
411			`ST_RDDATA2:
412			`begin`
413			ram_cmd <= `CMD_NOP;
414			`count <= 1;`
415			state <= `ST_RDDATA3;
416			`end`
417			`ST_RDDATA3:
418			`begin`
419			`ram_cnt <= 0;`
420			`data_ld <= 1;`
421			ram_cmd <= `CMD_NOP;
422			`count <= 3;`
423			state <= `ST_RDDATA4;
424			`end`
425			`ST_RDDATA4:
426			`begin`
427			`data_ack <= 1;`
428			`data_ld <= 0;`
429			ram_cmd <= `CMD_NOP;
430			state <= `ST_RDDATA5;
431			`end`
432			`ST_RDDATA5:
433			`begin`
434			`data_ack <= 0;`
435			ram_cmd <= `CMD_NOP;
436			`count <= 3;`
437			state <= `ST_IDLE;
438			`end`
439			`//----------------------------`
440			`// read inst`
441			`//----------------------------`
442			`ST_RDINST0:
443			`begin`
444			ram_cmd <= `CMD_NOP;
445			count <= `T_RCD - 2;
446			state <= `ST_RDINST1;
447			`end`
448			`ST_RDINST1:
449			`begin`
450			ram_cmd <= `CMD_READ;
451			`sdram_ba <= inst_addr[21:20];`
452			`sdram_a <= { 6'b0010, inst_addr[6:0], 2'b00 };`
453			state <= `ST_RDINST2;
454			`end`
455			`ST_RDINST2:
456			`begin`
457			ram_cmd <= `CMD_NOP;
458			`count <= 1;`
459			state <= `ST_RDINST3;
460			`end`
461			`ST_RDINST3:
462			`begin`
463			`ram_cnt <= 0;`
464			`data_ld <= 1;`
465			ram_cmd <= `CMD_NOP;
466			`count <= 3;`
467			state <= `ST_RDINST4;
468			`end`
469			`ST_RDINST4:
470			`begin`
471			`inst_ack <= 1;`
472			`data_ld <= 0;`
473			ram_cmd <= `CMD_NOP;
474			state <= `ST_RDINST5;
475			`end`
476			`ST_RDINST5:
477			`begin`
478			`inst_ack <= 0;`
479			ram_cmd <= `CMD_NOP;
480			`count <= 3;`
481			state <= `ST_IDLE;
482			`end`
483			`//----------------------------`
484			`// illegal data address`
485			`//----------------------------`
486			`ST_ILLDA0:
487			`begin`
488			`data_timeout <= 1;`
489			ram_cmd <= `CMD_NOP;
490			state <= `ST_ILLDA1;
491			`end`
492			`ST_ILLDA1:
493			`begin`
494			`data_timeout <= 0;`
495			ram_cmd <= `CMD_NOP;
496			state <= `ST_IDLE;
497			`end`
498			`//----------------------------`
499			`// illegal inst address`
500			`//----------------------------`
501			`ST_ILLIA0:
502			`begin`
503			`inst_timeout <= 1;`
504			ram_cmd <= `CMD_NOP;
505			state <= `ST_ILLIA1;
506			`end`
507			`ST_ILLIA1:
508			`begin`
509			`inst_timeout <= 0;`
510			ram_cmd <= `CMD_NOP;
511			state <= `ST_IDLE;
512			`end`
513			`//----------------------------`
514			`// not used`
515			`//----------------------------`
516			`default:`
517			`begin`
518			`inst_ack <= 0;`
519			`inst_timeout <= 0;`
520			`data_ack <= 0;`
521			`data_timeout <= 0;`
522			`sdram_cke <= 0;`
523			`sdram_cs_n <= 1;`
524			`ram_cnt <= 0;`
525			`ram_de <= 0;`
526			`data_ld <= 0;`
527			ram_cmd <= `CMD_NOP;
528			`ram_dqm <= 2'b11;`
529			count <= `T_INIT0 - 1;
530			state <= `ST_INIT0;
531			`refrst <= 0;`
532			`end`
533			`endcase`
534			`end`
535			`end`
536			`end`
537
538			`//`
539			`// refresh counter`
540			`//`
541
542			`always @(posedge clk or negedge clk_ok) begin`
543			`if (~clk_ok) begin`
544			`refcnt <= 10'd0;`
545			`end else begin`
546			`if (refcnt == 10'd0) begin`
547			refcnt <= `REFCNT;
548			`refflg <= 1;`
549			`end else begin`
550			`refcnt <= refcnt - 1;`
551			`if (refrst) begin`
552			`refflg <= 0;`
553			`end`
554			`end`
555			`end`
556			`end`
557
558			`endmodule`