OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [fpga/] [experiments/] [memctrl/] [sim/] [memctrl-1/] [ramtest/] [ramtest.v] - Blame information for rev 313

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 313 hellwig
//
2
// ramtest.v -- RAM test generator
3
//
4
 
5
 
6
`timescale 1ns/10ps
7
`default_nettype none
8
 
9
 
10
`define SIMULATE
11
`define VERBOSE
12
 
13
`define INST_PERIOD     31
14
`define INST_PHASE      19
15
`define DATA_PERIOD     17
16
`define DATA_PHASE      7
17
 
18
 
19
//
20
// memory test generator
21
//
22
// Algorithm: Three independent address/data generators
23
// produce exactly the same sequence of address/data pairs,
24
// although at different times: data write, data read, and
25
// instruction read. Three out of four data cycles are writes,
26
// one is a read. Instruction reads are also less frequent
27
// than data writes: 1/31 < 1/17 * 3/4. The writing process
28
// is therefore always ahead of the reading processes, with
29
// an increasing gap in between.
30
//
31
 
32
module ramtest(clk, rst,
33
               inst_stb, inst_addr,
34
               inst_din, inst_ack,
35
               data_stb, data_we, data_addr,
36
               data_dout, data_din, data_ack,
37
               test_ended, test_error);
38
    input clk;
39
    input rst;
40
    output reg inst_stb;
41
    output [25:0] inst_addr;
42
    input [63:0] inst_din;
43
    input inst_ack;
44
    output reg data_stb;
45
    output reg data_we;
46
    output [25:0] data_addr;
47
    output [63:0] data_dout;
48
    input [63:0] data_din;
49
    input data_ack;
50
    output test_ended;
51
    output test_error;
52
 
53
  reg [4:0] inst_timer;
54
  reg [4:0] data_timer;
55
  reg [9:0] data_counter;
56
 
57
  wire ir_next;
58
  wire [21:0] ir_a;
59
  wire [63:0] ir_d;
60
 
61
  wire dw_next;
62
  wire [21:0] dw_a;
63
  wire [63:0] dw_d;
64
 
65
  wire dr_next;
66
  wire [21:0] dr_a;
67
  wire [63:0] dr_d;
68
 
69
`ifdef SIMULATE
70
  reg error_1;
71
  reg error_3;
72
`endif
73
  reg error_2;
74
  reg error_4;
75
 
76
  always @(posedge clk) begin
77
    if (rst) begin
78
      inst_timer <= 0;
79
      inst_stb <= 0;
80
`ifdef SIMULATE
81
      error_1 <= 0;
82
`endif
83
      error_2 <= 0;
84
    end else begin
85
      if (~test_ended) begin
86
        if (~inst_stb) begin
87
          if (inst_timer == `INST_PERIOD - 1) begin
88
            inst_timer <= 0;
89
          end else begin
90
            inst_timer <= inst_timer + 1;
91
          end
92
          if (inst_timer == `INST_PHASE) begin
93
            inst_stb <= 1;
94
          end
95
        end else begin
96
          if (inst_ack) begin
97
            inst_stb <= 0;
98
`ifdef SIMULATE
99
`ifdef VERBOSE
100
            $display("%t: inst read  @ 0x%h", $realtime, ir_a);
101
            $display("                   value = 0x%h", inst_din);
102
`endif
103
            if (^inst_din[63:0] === 1'bx) begin
104
              $display("Warning: Input data has don't cares at %t",
105
                       $realtime);
106
              error_1 <= 1;
107
            end
108
`endif
109
            if (inst_din[63:0] != ir_d[63:0]) begin
110
              error_2 <= 1;
111
            end
112
          end
113
        end
114
      end
115
    end
116
  end
117
 
118
  adgen adgen_ir(
119
    .clk(clk),
120
    .rst(rst),
121
    .next(ir_next),
122
    .addr(ir_a),
123
    .data(ir_d)
124
  );
125
 
126
  assign ir_next = inst_ack;
127
  assign inst_addr[25:0] = { 4'h0, ir_a[21:0] };
128
 
129
  always @(posedge clk) begin
130
    if (rst) begin
131
      data_timer <= 0;
132
      data_stb <= 0;
133
      data_we <= 0;
134
      data_counter <= 0;
135
`ifdef SIMULATE
136
      error_3 <= 0;
137
`endif
138
      error_4 <= 0;
139
    end else begin
140
      if (~test_ended) begin
141
        if (~data_stb) begin
142
          if (data_timer == `DATA_PERIOD - 1) begin
143
            data_timer <= 0;
144
          end else begin
145
            data_timer <= data_timer + 1;
146
          end
147
          if (data_timer == `DATA_PHASE) begin
148
            data_stb <= 1;
149
            data_we <= ~&data_counter[1:0];
150
          end
151
        end else begin
152
          if (data_ack) begin
153
            data_stb <= 0;
154
            data_we <= 0;
155
            data_counter <= data_counter + 1;
156
`ifdef SIMULATE
157
`ifdef VERBOSE
158
            if (data_we == 1) begin
159
              $display("%t: data write @ 0x%h", $realtime, dw_a);
160
              $display("                   value = 0x%h", dw_d);
161
            end else begin
162
              $display("%t: data read  @ 0x%h", $realtime, dr_a);
163
              $display("                   value = 0x%h", data_din);
164
            end
165
`endif
166
            if (data_we == 0 &&
167
                ^data_din[63:0] === 1'bx) begin
168
              $display("Warning: Input data has don't cares at %t",
169
                       $realtime);
170
              error_3 <= 1;
171
            end
172
`endif
173
            if (data_we == 0 &&
174
                data_din[63:0] != dr_d[63:0]) begin
175
              error_4 <= 1;
176
            end
177
          end
178
        end
179
      end
180
    end
181
  end
182
 
183
  adgen adgen_dw(
184
    .clk(clk),
185
    .rst(rst),
186
    .next(dw_next),
187
    .addr(dw_a),
188
    .data(dw_d)
189
  );
190
 
191
  adgen adgen_dr(
192
    .clk(clk),
193
    .rst(rst),
194
    .next(dr_next),
195
    .addr(dr_a),
196
    .data(dr_d)
197
  );
198
 
199
  assign dw_next = data_ack & data_we;
200
  assign dr_next = data_ack & ~data_we;
201
  assign data_addr[25:0] = { 4'h0, data_we ? dw_a[21:0] : dr_a[21:0] };
202
  assign data_dout[63:0] = dw_d[63:0];
203
 
204
  assign test_ended = &data_counter[9:0];
205
 
206
`ifdef SIMULATE
207
  assign test_error = error_1 | error_2 | error_3 | error_4;
208
`else
209
  assign test_error = error_2 | error_4;
210
`endif
211
 
212
endmodule
213
 
214
 
215
//
216
// address & data generator
217
//
218
// compute pseudo-random 32-bit address
219
// and 64-bit data on request
220
//
221
 
222
module adgen(clk, rst,
223
             next, addr, data);
224
    input clk;
225
    input rst;
226
    input next;
227
    output [21:0] addr;
228
    output [63:0] data;
229
 
230
  reg [31:0] a;
231
  reg [63:0] d;
232
 
233
  always @(posedge clk) begin
234
    if (rst) begin
235
      a[31: 0] <= 32'hC70337DB;
236
      d[63:32] <= 32'h7F4D514F;
237
      d[31: 0] <= 32'h75377599;
238
    end else begin
239
      if (next) begin
240
        if (a[0] == 0) begin
241
          a[31:0] <= a[31:0] >> 1;
242
        end else begin
243
          a[31:0] <= (a[31:0] >> 1) ^ 32'hD0000001;
244
        end
245
        if (d[32] == 0) begin
246
          d[63:32] <= d[63:32] >> 1;
247
        end else begin
248
          d[63:32] <= (d[63:32] >> 1) ^ 32'hD0000001;
249
        end
250
        if (d[0] == 0) begin
251
          d[31:0] <= d[31:0] >> 1;
252
        end else begin
253
          d[31:0] <= (d[31:0] >> 1) ^ 32'hD0000001;
254
        end
255
      end
256
    end
257
  end
258
 
259
  assign addr[21:0] = a[21:0];
260
  assign data[63:0] = d[63:0];
261
 
262
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.