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[/] [eco32/] [trunk/] [fpga/] [experiments/] [memdelay/] [memdelay.v] - Blame information for rev 302

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Line No. Rev Author Line
1 297 hellwig 
//
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// memdelay.v -- test memory delay
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//
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`timescale 1ns/10ps
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`default_nettype none
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module memdelay;
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  reg clk;
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  reg rst_in;
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  reg rst;
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  reg stb;
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  reg we;
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  wire [22:0] addr;
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  wire [31:0] data_in;
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  wire [31:0] data_out;
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  wire ack;
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  reg [5:0] state;
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  reg [5:0] next_state;
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  initial begin
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    #0     $dumpfile("dump.vcd");
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           $dumpvars(0, memdelay);
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           clk = 1;
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           rst_in = 1;
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    #25    rst_in = 0;
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    #1000  $finish;
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  end
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  always begin
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    #10 clk = ~ clk;
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  end
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  always @(posedge clk) begin
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    rst <= rst_in;
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  end
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  assign addr[22:0] = 23'h123456;
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  assign data_in[31:0] = 32'h12345678;
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  ram ram_1(
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    .clk(clk),
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    .rst(rst),
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    .stb(stb),
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    .we(we),
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    .addr(addr[22:0]),
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    .data_in(data_in[31:0]),
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    .data_out(data_out[31:0]),
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    .ack(ack)
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  );
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  always @(posedge clk) begin
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    if (rst) begin
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      state <= 0;
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    end else begin
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      state <= next_state;
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    end
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  end
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  always @(*) begin
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    case (state[5:0])
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      6'h0:
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        begin
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          stb = 0;
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          we = 0;
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          next_state = 6'h1;
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        end
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      6'h1:
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        begin
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          stb = 0;
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          we = 0;
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          next_state = 6'h2;
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        end
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      6'h2:
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        begin
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          stb = 1;
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          we = 0;
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          if (ack) begin
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            next_state = 6'h3;
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          end else begin
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            next_state = 6'h2;
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          end
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        end
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      6'h3:
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        begin
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          stb = 0;
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          we = 0;
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          next_state = 6'h4;
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        end
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      6'h4:
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        begin
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          stb = 0;
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          we = 0;
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          next_state = 6'h5;
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        end
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      6'h5:
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        begin
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          stb = 1;
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          we = 1;
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          if (ack) begin
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            next_state = 6'h6;
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          end else begin
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            next_state = 6'h5;
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          end
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        end
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      6'h6:
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        begin
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          stb = 0;
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          we = 0;
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          next_state = 6'h6;
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        end
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      default:
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        begin
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          stb = 0;
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          we = 0;
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          next_state = 6'h0;
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        end
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    endcase
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  end
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endmodule

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