Subversion Repositories eco32

Purpose

-------

This test circuit allows speed measurements of the old

memory controller (written by Dave Vanden Bout), driving

the on-board SDRAM of the XESS board. To do timing

measurements of reads or writes, wire the "we" signal

to 0 or 1, respectively. It is also possible to get a

mix of reads and writes if the "we" signal is a function

of (some bits of) the counter "count". Note that only

32-bit accesses are performed. The clock rate is 50 MHz.

Read

----

41.8 s

41.9 s

41.7 s

average:

41.8 s / 2^27 read cycles = 311.4 ns / read cycle

which means 15.6 clock cycles per read

(the corresponding data rate is 12.8 MB/s)

Write

-----

19.6 s

19.7 s

19.6 s

average:

19.6 s / 2^27 write cycles = 146.0 ns / write cycle

which means 7.3 clock cycles per write

(the corresponding data rate is 27.4 MB/s)

Mix (75% read, 25% write)

-------------------------

36.2 s

36.1 s

36.2 s

average:

36.2 s / 2^27 operations = 269.7 ns / operation

which means 13.5 clock cycles per operation

Conclusions

-----------

1) The weighted average from read and write operations

   (0.75*15.6 + 0.25*7.3) is a very good approximation

   for the value measured in the "mixed" case. This

   confirms the different values for the "read" and

   "write" cases.

2) The test circuit needs one clock cycle to recover

   from a read or write operation before the next one

   is started. The recommended number of clock cycles

   for a memory simulation are therefore

       read   : 14 clock cycles

       write  :  6 clock cycles

   measured from start of the operation (leading edge

   of signal stb) to end of the operation (trailing

   edge of signal ack).