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[/] [eco32/] [trunk/] [fpga/] [experiments/] [memspeed-1/] [src/] [memspeed.v] - Blame information for rev 296

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1 296 hellwig
//
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// memspeed.v -- toplevel for memory speedometer
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//
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`timescale 1ns/10ps
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`default_nettype none
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module memspeed(clk_in,
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                rst_inout_n,
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                sdram_clk,
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                sdram_fb,
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                sdram_cke,
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                sdram_cs_n,
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                sdram_ras_n,
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                sdram_cas_n,
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                sdram_we_n,
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                sdram_ba,
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                sdram_a,
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                sdram_udqm,
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                sdram_ldqm,
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                sdram_dq,
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                ssl
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               );
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    // clock and reset
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    input clk_in;
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    inout rst_inout_n;
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    // SDRAM
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    output sdram_clk;
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    input sdram_fb;
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    output sdram_cke;
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    output sdram_cs_n;
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    output sdram_ras_n;
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    output sdram_cas_n;
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    output sdram_we_n;
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    output [1:0] sdram_ba;
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    output [12:0] sdram_a;
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    output sdram_udqm;
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    output sdram_ldqm;
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    inout [15:0] sdram_dq;
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    // 7 segment LED output
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    output [6:0] ssl;
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  // clk_rst
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  wire clk;
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  wire clk_ok;
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  wire rst;
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  // ram
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  reg stb;
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  wire we;
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  wire [22:0] addr;
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  wire [31:0] data_in;
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  wire [31:0] data_out;
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  wire ack;
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  // control
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  reg [27:0] count;
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  reg next_count;
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  reg [1:0] state;
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  reg [1:0] next_state;
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  clk_rst clk_rst_1(
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    .clk_in(clk_in),
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    .rst_inout_n(rst_inout_n),
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    .sdram_clk(sdram_clk),
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    .sdram_fb(sdram_fb),
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    .clk(clk),
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    .clk_ok(clk_ok),
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    .rst(rst)
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  );
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  ram ram_1(
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    .clk(clk),
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    .clk_ok(clk_ok),
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    .rst(rst),
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    .stb(stb),
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    .we(we),
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    .addr(addr[22:0]),
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    .data_in(data_in[31:0]),
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    .data_out(data_out[31:0]),
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    .ack(ack),
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    .sdram_cke(sdram_cke),
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    .sdram_cs_n(sdram_cs_n),
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    .sdram_ras_n(sdram_ras_n),
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    .sdram_cas_n(sdram_cas_n),
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    .sdram_we_n(sdram_we_n),
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    .sdram_ba(sdram_ba),
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    .sdram_a(sdram_a),
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    .sdram_udqm(sdram_udqm),
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    .sdram_ldqm(sdram_ldqm),
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    .sdram_dq(sdram_dq)
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  );
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  assign we = count[1] & count[0];
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  assign addr[22:0] = count[22:0];
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  assign data_in[31:0] = { count[15:0], count[15:0] };
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  always @(posedge clk) begin
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    if (rst) begin
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      count <= 0;
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    end else begin
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      if (next_count) begin
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        count <= count + 1;
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      end
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    end
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  end
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  always @(posedge clk) begin
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    if (rst) begin
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      state <= 0;
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    end else begin
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      state <= next_state;
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    end
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  end
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  always @(*) begin
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    case (state)
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      2'd0:
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        begin
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          stb = 0;
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          next_count = 0;
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          next_state = 1;
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        end
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      2'd1:
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        begin
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          stb = 1;
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          next_count = 0;
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          if (ack) begin
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            next_state = 2;
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          end else begin
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            next_state = 1;
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          end
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        end
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      2'd2:
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        begin
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          stb = 0;
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          next_count = 1;
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          if (count[27]) begin
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            next_state = 3;
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          end else begin
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            next_state = 1;
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          end
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        end
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      2'd3:
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        begin
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          stb = 0;
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          next_count = 0;
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          next_state = 3;
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        end
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    endcase
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  end
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  assign ssl[0] = 0;
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  assign ssl[1] = | state[1:0];
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  assign ssl[2] = & state[1:0];
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  assign ssl[3] = 0;
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  assign ssl[4] = 0;
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  assign ssl[5] = 0;
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  assign ssl[6] = ^ data_out[31:0];
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endmodule

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