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hellwig |
--------------------------------------------------------------------
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-- Company : XESS Corp.
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-- Engineer : Dave Vanden Bout
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-- Creation Date : 05/17/2005
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-- Copyright : 2005, XESS Corp
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-- Tool Versions : WebPACK 6.3.03i
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--
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-- Description:
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-- SDRAM controller
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--
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-- Revision:
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-- n.a. (because of hacking by Hellwig Geisse)
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--
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-- Additional Comments:
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-- 1.4.0:
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-- Added generic parameter to enable/disable independent active rows in each bank.
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-- 1.3.0:
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-- Modified to allow independently active rows in each bank.
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-- 1.2.0:
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-- Modified to allow pipelining of read/write operations.
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-- 1.1.0:
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-- Initial release.
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--
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-- License:
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-- This code can be freely distributed and modified as long as
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-- this header is not removed.
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--------------------------------------------------------------------
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library IEEE, UNISIM;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.numeric_std.all;
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entity sdramCntl is
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port(
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-- host side
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clk : in std_logic; -- master clock
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clk_ok : in std_logic; -- true if clock is stable
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rd : in std_logic; -- initiate read operation
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wr : in std_logic; -- initiate write operation
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done : out std_logic; -- read or write operation is done
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hAddr : in std_logic_vector(23 downto 0); -- address from host to SDRAM
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hDIn : in std_logic_vector(15 downto 0); -- data from host to SDRAM
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hDOut : out std_logic_vector(15 downto 0); -- data from SDRAM to host
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-- SDRAM side
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cke : out std_logic; -- clock-enable to SDRAM
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ce_n : out std_logic; -- chip-select to SDRAM
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ras_n : out std_logic; -- SDRAM row address strobe
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cas_n : out std_logic; -- SDRAM column address strobe
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we_n : out std_logic; -- SDRAM write enable
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ba : out std_logic_vector(1 downto 0); -- SDRAM bank address
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sAddr : out std_logic_vector(12 downto 0); -- SDRAM row/column address
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sDIn : in std_logic_vector(15 downto 0); -- data from SDRAM
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sDOut : out std_logic_vector(15 downto 0); -- data to SDRAM
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sDOutEn : out std_logic; -- true if data is output to SDRAM on sDOut
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dqmh : out std_logic; -- enable upper-byte of SDRAM databus if true
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dqml : out std_logic -- enable lower-byte of SDRAM databus if true
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);
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end sdramCntl;
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architecture arch of sdramCntl is
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constant YES : std_logic := '1';
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constant NO : std_logic := '0';
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-- select one of two integers based on a Boolean
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function int_select(s : in boolean; a : in integer; b : in integer) return integer is
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begin
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if s then
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return a;
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else
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return b;
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end if;
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return a;
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end function int_select;
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constant OUTPUT : std_logic := '1'; -- direction of dataflow w.r.t. this controller
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constant INPUT : std_logic := '0';
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constant NOP : std_logic := '0'; -- no operation
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constant READ : std_logic := '1'; -- read operation
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constant WRITE : std_logic := '1'; -- write operation
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-- SDRAM timing parameters
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constant Tinit : natural := 200; -- min initialization interval (us)
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constant Tras : natural := 45; -- min interval between active to precharge commands (ns)
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constant Trcd : natural := 20; -- min interval between active and R/W commands (ns)
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constant Tref : natural := 64_000_000; -- maximum refresh interval (ns)
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constant Trfc : natural := 66; -- duration of refresh operation (ns)
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constant Trp : natural := 20; -- min precharge command duration (ns)
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constant Twr : natural := 15; -- write recovery time (ns)
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constant Txsr : natural := 75; -- exit self-refresh time (ns)
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-- SDRAM timing parameters converted into clock cycles (based on FREQ = 50_000)
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constant NORM : natural := 1_000_000; -- normalize ns * KHz
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constant INIT_CYCLES : natural := 1+((Tinit*50_000)/1000); -- SDRAM power-on initialization interval
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constant RAS_CYCLES : natural := 1+((Tras*50_000)/NORM); -- active-to-precharge interval
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constant RCD_CYCLES : natural := 1+((Trcd*50_000)/NORM); -- active-to-R/W interval
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constant REF_CYCLES : natural := 1+(((Tref/8192)*50_000)/NORM); -- interval between row refreshes
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constant RFC_CYCLES : natural := 1+((Trfc*50_000)/NORM); -- refresh operation interval
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constant RP_CYCLES : natural := 1+((Trp*50_000)/NORM); -- precharge operation interval
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constant WR_CYCLES : natural := 1+((Twr*50_000)/NORM); -- write recovery time
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constant XSR_CYCLES : natural := 1+((Txsr*50_000)/NORM); -- exit self-refresh time
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constant MODE_CYCLES : natural := 2; -- mode register setup time
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constant CAS_CYCLES : natural := 3; -- CAS latency
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constant RFSH_OPS : natural := 8; -- number of refresh operations needed to init SDRAM
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-- timer registers that count down times for various SDRAM operations
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signal timer_r, timer_x : natural range 0 to INIT_CYCLES; -- current SDRAM op time
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signal rasTimer_r, rasTimer_x : natural range 0 to RAS_CYCLES; -- active-to-precharge time
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signal wrTimer_r, wrTimer_x : natural range 0 to WR_CYCLES; -- write-to-precharge time
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signal refTimer_r, refTimer_x : natural range 0 to REF_CYCLES; -- time between row refreshes
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signal rfshCntr_r, rfshCntr_x : natural range 0 to 8192; -- counts refreshes that are neede
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signal nopCntr_r, nopCntr_x : natural range 0 to 10000; -- counts consecutive NOP operations
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signal doSelfRfsh : std_logic; -- active when the NOP counter hits zero and self-refresh can start
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-- states of the SDRAM controller state machine
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type cntlState is (
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INITWAIT, -- initialization - waiting for power-on initialization to complete
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INITPCHG, -- initialization - initial precharge of SDRAM banks
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INITSETMODE, -- initialization - set SDRAM mode
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INITRFSH, -- initialization - do initial refreshes
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RW, -- read/write/refresh the SDRAM
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ACTIVATE, -- open a row of the SDRAM for reading/writing
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REFRESHROW, -- refresh a row of the SDRAM
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SELFREFRESH -- keep SDRAM in self-refresh mode with CKE low
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);
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signal state_r, state_x : cntlState; -- state register and next state
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-- commands that are sent to the SDRAM to make it perform certain operations
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-- commands use these SDRAM input pins (ce_n,ras_n,cas_n,we_n,dqmh,dqml)
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subtype sdramCmd is unsigned(5 downto 0);
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constant NOP_CMD : sdramCmd := "011100";
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constant ACTIVE_CMD : sdramCmd := "001100";
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constant READ_CMD : sdramCmd := "010100";
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constant WRITE_CMD : sdramCmd := "010000";
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constant PCHG_CMD : sdramCmd := "001011";
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constant MODE_CMD : sdramCmd := "000011";
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constant RFSH_CMD : sdramCmd := "000111";
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-- SDRAM mode register
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-- the SDRAM is placed in a non-burst mode (burst length = 1) with a 3-cycle CAS
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subtype sdramMode is std_logic_vector(12 downto 0);
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constant MODE : sdramMode := "000" & "0" & "00" & "011" & "0" & "000";
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-- the host address is decomposed into these sets of SDRAM address components
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constant ROW_LEN : natural := 13; -- number of row address bits
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constant COL_LEN : natural := 9; -- number of column address bits
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signal bank : std_logic_vector(ba'range); -- bank address bits
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signal row : std_logic_vector(ROW_LEN - 1 downto 0); -- row address within bank
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signal col : std_logic_vector(sAddr'range); -- column address within row
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-- registers that store the currently active row in each bank of the SDRAM
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constant NUM_ACTIVE_ROWS : integer := 1;
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type activeRowType is array(0 to NUM_ACTIVE_ROWS-1) of std_logic_vector(row'range);
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signal activeRow_r, activeRow_x : activeRowType;
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signal activeFlag_r, activeFlag_x : std_logic_vector(0 to NUM_ACTIVE_ROWS-1); -- indicates that some row in a bank is active
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signal bankIndex : natural range 0 to NUM_ACTIVE_ROWS-1; -- bank address bits
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signal activeBank_r, activeBank_x : std_logic_vector(ba'range); -- indicates the bank with the active row
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signal doActivate : std_logic; -- indicates when a new row in a bank needs to be activated
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-- there is a command bit embedded within the SDRAM column address
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constant CMDBIT_POS : natural := 10; -- position of command bit
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constant AUTO_PCHG_ON : std_logic := '1'; -- CMDBIT value to auto-precharge the bank
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constant AUTO_PCHG_OFF : std_logic := '0'; -- CMDBIT value to disable auto-precharge
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constant ONE_BANK : std_logic := '0'; -- CMDBIT value to select one bank
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constant ALL_BANKS : std_logic := '1'; -- CMDBIT value to select all banks
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-- status signals that indicate when certain operations are in progress
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signal wrInProgress : std_logic; -- write operation in progress
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signal rdInProgress : std_logic; -- read operation in progress
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signal activateInProgress : std_logic; -- row activation is in progress
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-- these registers track the progress of read and write operations
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signal rdPipeline_r, rdPipeline_x : std_logic_vector(CAS_CYCLES+1 downto 0); -- pipeline of read ops in progress
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signal wrPipeline_r, wrPipeline_x : std_logic_vector(0 downto 0); -- pipeline of write ops (only need 1 cycle)
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-- registered outputs to host
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signal hDOut_r, hDOut_x : std_logic_vector(hDOut'range); -- holds data read from SDRAM and sent to the host
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-- registered outputs to SDRAM
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signal cke_r, cke_x : std_logic; -- clock enable
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signal cmd_r, cmd_x : sdramCmd; -- SDRAM command bits
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signal ba_r, ba_x : std_logic_vector(ba'range); -- SDRAM bank address bits
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signal sAddr_r, sAddr_x : std_logic_vector(sAddr'range); -- SDRAM row/column address
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signal sData_r, sData_x : std_logic_vector(sDOut'range); -- SDRAM out databus
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signal sDataDir_r, sDataDir_x : std_logic; -- SDRAM databus direction control bit
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begin
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-----------------------------------------------------------
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-- attach some internal signals to the I/O ports
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-----------------------------------------------------------
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-- attach registered SDRAM control signals to SDRAM input pins
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(ce_n, ras_n, cas_n, we_n, dqmh, dqml) <= cmd_r; -- SDRAM operation control bits
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cke <= cke_r; -- SDRAM clock enable
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ba <= ba_r; -- SDRAM bank address
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sAddr <= sAddr_r; -- SDRAM address
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sDOut <= sData_r; -- SDRAM output data bus
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sDOutEn <= YES when sDataDir_r = OUTPUT else NO; -- output databus enable
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-- attach some port signals
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hDOut <= hDOut_r; -- data back to host
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-----------------------------------------------------------
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-- compute the next state and outputs
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-----------------------------------------------------------
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combinatorial : process(rd, wr, hAddr, hDIn, hDOut_r, sDIn, state_r,
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activeFlag_r, activeRow_r, activeBank_r,
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rdPipeline_r, wrPipeline_r,
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nopCntr_r, rfshCntr_r, timer_r, rasTimer_r,
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wrTimer_r, refTimer_r, cmd_r, cke_r)
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begin
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-----------------------------------------------------------
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-- setup default values for signals
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-----------------------------------------------------------
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cke_x <= YES; -- enable SDRAM clock
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cmd_x <= NOP_CMD; -- set SDRAM command to no-operation
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sDataDir_x <= INPUT; -- accept data from the SDRAM
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sData_x <= hDIn(sData_x'range); -- output data from host to SDRAM
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state_x <= state_r; -- reload these registers and flags
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activeFlag_x <= activeFlag_r; -- with their existing values
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activeRow_x <= activeRow_r;
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activeBank_x <= activeBank_r;
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rfshCntr_x <= rfshCntr_r;
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-----------------------------------------------------------
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-- setup default value for the SDRAM address
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-----------------------------------------------------------
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-- extract bank field from host address
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ba_x <= hAddr(ba'length + ROW_LEN + COL_LEN - 1 downto ROW_LEN + COL_LEN);
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bank <= ba_x;
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bankIndex <= 0;
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-- extract row, column fields from host address
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row <= hAddr(ROW_LEN + COL_LEN - 1 downto COL_LEN);
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-- extend column (if needed) until it is as large as the (SDRAM address bus - 1)
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col <= (others => '0'); -- set it to all zeroes
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col(COL_LEN-1 downto 0) <= hAddr(COL_LEN-1 downto 0);
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-- by default, set SDRAM address to the column address with interspersed
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-- command bit set to disable auto-precharge
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sAddr_x <= col(col'high-1 downto CMDBIT_POS) & AUTO_PCHG_OFF
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& col(CMDBIT_POS-1 downto 0);
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-----------------------------------------------------------
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-- manage the read and write operation pipelines
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-----------------------------------------------------------
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-- determine if read operations are in progress by the presence of
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-- READ flags in the read pipeline
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if rdPipeline_r(rdPipeline_r'high downto 1) /= 0 then
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rdInProgress <= YES;
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else
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rdInProgress <= NO;
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end if;
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-- enter NOPs into the read and write pipeline shift registers by default
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rdPipeline_x <= NOP & rdPipeline_r(rdPipeline_r'high downto 1);
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wrPipeline_x(0) <= NOP;
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-- transfer data from SDRAM to the host data register if a read flag has exited the pipeline
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-- (the transfer occurs 1 cycle before we tell the host the read operation is done)
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if rdPipeline_r(1) = READ then
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-- get the SDRAM data for the host directly from the SDRAM if the controller and SDRAM are in-phase
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hDOut_x <= sDIn(hDOut'range);
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else
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-- retain contents of host data registers if no data from the SDRAM has arrived yet
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hDOut_x <= hDOut_r;
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end if;
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done <= rdPipeline_r(0) or wrPipeline_r(0); -- a read or write operation is done
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-----------------------------------------------------------
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-- manage row activation
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-----------------------------------------------------------
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-- request a row activation operation if the row of the current address
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-- does not match the currently active row in the bank, or if no row
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-- in the bank is currently active
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if (bank /= activeBank_r) or (row /= activeRow_r(bankIndex)) or (activeFlag_r(bankIndex) = NO) then
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doActivate <= YES;
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else
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doActivate <= NO;
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end if;
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-----------------------------------------------------------
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-- manage self-refresh
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-----------------------------------------------------------
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-- enter self-refresh if neither a read or write is requested for 10000 consecutive cycles.
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if (rd = YES) or (wr = YES) then
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-- any read or write resets NOP counter and exits self-refresh state
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nopCntr_x <= 0;
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doSelfRfsh <= NO;
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elsif nopCntr_r /= 10000 then
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-- increment NOP counter whenever there is no read or write operation
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|
|
nopCntr_x <= nopCntr_r + 1;
|
305 |
|
|
doSelfRfsh <= NO;
|
306 |
|
|
else
|
307 |
|
|
-- start self-refresh when counter hits maximum NOP count and leave counter unchanged
|
308 |
|
|
nopCntr_x <= nopCntr_r;
|
309 |
|
|
doSelfRfsh <= YES;
|
310 |
|
|
end if;
|
311 |
|
|
|
312 |
|
|
-----------------------------------------------------------
|
313 |
|
|
-- update the timers
|
314 |
|
|
-----------------------------------------------------------
|
315 |
|
|
|
316 |
|
|
-- row activation timer
|
317 |
|
|
if rasTimer_r /= 0 then
|
318 |
|
|
-- decrement a non-zero timer and set the flag
|
319 |
|
|
-- to indicate the row activation is still inprogress
|
320 |
|
|
rasTimer_x <= rasTimer_r - 1;
|
321 |
|
|
activateInProgress <= YES;
|
322 |
|
|
else
|
323 |
|
|
-- on timeout, keep the timer at zero and reset the flag
|
324 |
|
|
-- to indicate the row activation operation is done
|
325 |
|
|
rasTimer_x <= rasTimer_r;
|
326 |
|
|
activateInProgress <= NO;
|
327 |
|
|
end if;
|
328 |
|
|
|
329 |
|
|
-- write operation timer
|
330 |
|
|
if wrTimer_r /= 0 then
|
331 |
|
|
-- decrement a non-zero timer and set the flag
|
332 |
|
|
-- to indicate the write operation is still inprogress
|
333 |
|
|
wrTimer_x <= wrTimer_r - 1;
|
334 |
|
|
wrInPRogress <= YES;
|
335 |
|
|
else
|
336 |
|
|
-- on timeout, keep the timer at zero and reset the flag that
|
337 |
|
|
-- indicates a write operation is in progress
|
338 |
|
|
wrTimer_x <= wrTimer_r;
|
339 |
|
|
wrInPRogress <= NO;
|
340 |
|
|
end if;
|
341 |
|
|
|
342 |
|
|
-- refresh timer
|
343 |
|
|
if refTimer_r /= 0 then
|
344 |
|
|
refTimer_x <= refTimer_r - 1;
|
345 |
|
|
else
|
346 |
|
|
-- on timeout, reload the timer with the interval between row refreshes
|
347 |
|
|
-- and increment the counter for the number of row refreshes that are needed
|
348 |
|
|
refTimer_x <= REF_CYCLES;
|
349 |
|
|
rfshCntr_x <= rfshCntr_r + 1;
|
350 |
|
|
end if;
|
351 |
|
|
|
352 |
|
|
-- main timer for sequencing SDRAM operations
|
353 |
|
|
if timer_r /= 0 then
|
354 |
|
|
-- decrement the timer and do nothing else since the previous operation has not completed yet.
|
355 |
|
|
timer_x <= timer_r - 1;
|
356 |
|
|
else
|
357 |
|
|
-- the previous operation has completed once the timer hits zero
|
358 |
|
|
timer_x <= timer_r; -- by default, leave the timer at zero
|
359 |
|
|
|
360 |
|
|
-----------------------------------------------------------
|
361 |
|
|
-- compute the next state and outputs
|
362 |
|
|
-----------------------------------------------------------
|
363 |
|
|
case state_r is
|
364 |
|
|
|
365 |
|
|
-----------------------------------------------------------
|
366 |
|
|
-- let clock stabilize and then wait for the SDRAM to initialize
|
367 |
|
|
-----------------------------------------------------------
|
368 |
|
|
when INITWAIT =>
|
369 |
|
|
-- wait for SDRAM power-on initialization once the clock is stable
|
370 |
|
|
timer_x <= INIT_CYCLES; -- set timer for initialization duration
|
371 |
|
|
state_x <= INITPCHG;
|
372 |
|
|
|
373 |
|
|
-----------------------------------------------------------
|
374 |
|
|
-- precharge all SDRAM banks after power-on initialization
|
375 |
|
|
-----------------------------------------------------------
|
376 |
|
|
when INITPCHG =>
|
377 |
|
|
cmd_x <= PCHG_CMD;
|
378 |
|
|
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks
|
379 |
|
|
timer_x <= RP_CYCLES; -- set timer for precharge operation duration
|
380 |
|
|
rfshCntr_x <= RFSH_OPS; -- set counter for refresh ops needed after precharge
|
381 |
|
|
state_x <= INITRFSH;
|
382 |
|
|
|
383 |
|
|
-----------------------------------------------------------
|
384 |
|
|
-- refresh the SDRAM a number of times after initial precharge
|
385 |
|
|
-----------------------------------------------------------
|
386 |
|
|
when INITRFSH =>
|
387 |
|
|
cmd_x <= RFSH_CMD;
|
388 |
|
|
timer_x <= RFC_CYCLES; -- set timer to refresh operation duration
|
389 |
|
|
rfshCntr_x <= rfshCntr_r - 1; -- decrement refresh operation counter
|
390 |
|
|
if rfshCntr_r = 1 then
|
391 |
|
|
state_x <= INITSETMODE; -- set the SDRAM mode once all refresh ops are done
|
392 |
|
|
end if;
|
393 |
|
|
|
394 |
|
|
-----------------------------------------------------------
|
395 |
|
|
-- set the mode register of the SDRAM
|
396 |
|
|
-----------------------------------------------------------
|
397 |
|
|
when INITSETMODE =>
|
398 |
|
|
cmd_x <= MODE_CMD;
|
399 |
|
|
sAddr_x <= MODE; -- output mode register bits on the SDRAM address bits
|
400 |
|
|
timer_x <= MODE_CYCLES; -- set timer for mode setting operation duration
|
401 |
|
|
state_x <= RW;
|
402 |
|
|
|
403 |
|
|
-----------------------------------------------------------
|
404 |
|
|
-- process read/write/refresh operations after initialization is done
|
405 |
|
|
-----------------------------------------------------------
|
406 |
|
|
when RW =>
|
407 |
|
|
-----------------------------------------------------------
|
408 |
|
|
-- highest priority operation: row refresh
|
409 |
|
|
-- do a refresh operation if the refresh counter is non-zero
|
410 |
|
|
-----------------------------------------------------------
|
411 |
|
|
if rfshCntr_r /= 0 then
|
412 |
|
|
-- wait for any row activations, writes or reads to finish before doing a precharge
|
413 |
|
|
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
|
414 |
|
|
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
|
415 |
|
|
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks
|
416 |
|
|
timer_x <= RP_CYCLES; -- set timer for this operation
|
417 |
|
|
activeFlag_x <= (others => NO); -- all rows are inactive after a precharge operation
|
418 |
|
|
state_x <= REFRESHROW; -- refresh the SDRAM after the precharge
|
419 |
|
|
end if;
|
420 |
|
|
-----------------------------------------------------------
|
421 |
|
|
-- do a host-initiated read operation
|
422 |
|
|
-----------------------------------------------------------
|
423 |
|
|
elsif rd = YES then
|
424 |
|
|
-- Wait one clock cycle if the bank address has just changed and each bank has its own active row.
|
425 |
|
|
-- This gives extra time for the row activation circuitry.
|
426 |
|
|
if (true) then
|
427 |
|
|
-- activate a new row if the current read is outside the active row or bank
|
428 |
|
|
if doActivate = YES then
|
429 |
|
|
-- activate new row only if all previous activations, writes, reads are done
|
430 |
|
|
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
|
431 |
|
|
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
|
432 |
|
|
sAddr_x(CMDBIT_POS) <= ONE_BANK; -- precharge this bank
|
433 |
|
|
timer_x <= RP_CYCLES; -- set timer for this operation
|
434 |
|
|
activeFlag_x(bankIndex) <= NO; -- rows in this bank are inactive after a precharge operation
|
435 |
|
|
state_x <= ACTIVATE; -- activate the new row after the precharge is done
|
436 |
|
|
end if;
|
437 |
|
|
-- read from the currently active row if no previous read operation
|
438 |
|
|
-- is in progress or if pipeline reads are enabled
|
439 |
|
|
-- we can always initiate a read even if a write is already in progress
|
440 |
|
|
elsif (rdInProgress = NO) then
|
441 |
|
|
cmd_x <= READ_CMD; -- initiate a read of the SDRAM
|
442 |
|
|
-- insert a flag into the pipeline shift register that will exit the end
|
443 |
|
|
-- of the shift register when the data from the SDRAM is available
|
444 |
|
|
rdPipeline_x <= READ & rdPipeline_r(rdPipeline_r'high downto 1);
|
445 |
|
|
end if;
|
446 |
|
|
end if;
|
447 |
|
|
-----------------------------------------------------------
|
448 |
|
|
-- do a host-initiated write operation
|
449 |
|
|
-----------------------------------------------------------
|
450 |
|
|
elsif wr = YES then
|
451 |
|
|
-- Wait one clock cycle if the bank address has just changed and each bank has its own active row.
|
452 |
|
|
-- This gives extra time for the row activation circuitry.
|
453 |
|
|
if (true) then
|
454 |
|
|
-- activate a new row if the current write is outside the active row or bank
|
455 |
|
|
if doActivate = YES then
|
456 |
|
|
-- activate new row only if all previous activations, writes, reads are done
|
457 |
|
|
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
|
458 |
|
|
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
|
459 |
|
|
sAddr_x(CMDBIT_POS) <= ONE_BANK; -- precharge this bank
|
460 |
|
|
timer_x <= RP_CYCLES; -- set timer for this operation
|
461 |
|
|
activeFlag_x(bankIndex) <= NO; -- rows in this bank are inactive after a precharge operation
|
462 |
|
|
state_x <= ACTIVATE; -- activate the new row after the precharge is done
|
463 |
|
|
end if;
|
464 |
|
|
-- write to the currently active row if no previous read operations are in progress
|
465 |
|
|
elsif rdInProgress = NO then
|
466 |
|
|
cmd_x <= WRITE_CMD; -- initiate the write operation
|
467 |
|
|
sDataDir_x <= OUTPUT; -- turn on drivers to send data to SDRAM
|
468 |
|
|
-- set timer so precharge doesn't occur too soon after write operation
|
469 |
|
|
wrTimer_x <= WR_CYCLES;
|
470 |
|
|
-- insert a flag into the 1-bit pipeline shift register that will exit on the
|
471 |
|
|
-- next cycle. The write into SDRAM is not actually done by that time, but
|
472 |
|
|
-- this doesn't matter to the host
|
473 |
|
|
wrPipeline_x(0) <= WRITE;
|
474 |
|
|
end if;
|
475 |
|
|
end if;
|
476 |
|
|
-----------------------------------------------------------
|
477 |
|
|
-- do a host-initiated self-refresh operation
|
478 |
|
|
-----------------------------------------------------------
|
479 |
|
|
elsif doSelfRfsh = YES then
|
480 |
|
|
-- wait until all previous activations, writes, reads are done
|
481 |
|
|
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
|
482 |
|
|
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
|
483 |
|
|
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks
|
484 |
|
|
timer_x <= RP_CYCLES; -- set timer for this operation
|
485 |
|
|
activeFlag_x <= (others => NO); -- all rows are inactive after a precharge operation
|
486 |
|
|
state_x <= SELFREFRESH; -- self-refresh the SDRAM after the precharge
|
487 |
|
|
end if;
|
488 |
|
|
-----------------------------------------------------------
|
489 |
|
|
-- no operation
|
490 |
|
|
-----------------------------------------------------------
|
491 |
|
|
else
|
492 |
|
|
state_x <= RW; -- continue to look for SDRAM operations to execute
|
493 |
|
|
end if;
|
494 |
|
|
|
495 |
|
|
-----------------------------------------------------------
|
496 |
|
|
-- activate a row of the SDRAM
|
497 |
|
|
-----------------------------------------------------------
|
498 |
|
|
when ACTIVATE =>
|
499 |
|
|
cmd_x <= ACTIVE_CMD;
|
500 |
|
|
sAddr_x <= (others => '0'); -- output the address for the row to be activated
|
501 |
|
|
sAddr_x(row'range) <= row;
|
502 |
|
|
activeBank_x <= bank;
|
503 |
|
|
activeRow_x(bankIndex) <= row; -- store the new active SDRAM row address
|
504 |
|
|
activeFlag_x(bankIndex) <= YES; -- the SDRAM is now active
|
505 |
|
|
rasTimer_x <= RAS_CYCLES; -- minimum time before another precharge can occur
|
506 |
|
|
timer_x <= RCD_CYCLES; -- minimum time before a read/write operation can occur
|
507 |
|
|
state_x <= RW; -- return to do read/write operation that initiated this activation
|
508 |
|
|
|
509 |
|
|
-----------------------------------------------------------
|
510 |
|
|
-- refresh a row of the SDRAM
|
511 |
|
|
-----------------------------------------------------------
|
512 |
|
|
when REFRESHROW =>
|
513 |
|
|
cmd_x <= RFSH_CMD;
|
514 |
|
|
timer_x <= RFC_CYCLES; -- refresh operation interval
|
515 |
|
|
rfshCntr_x <= rfshCntr_r - 1; -- decrement the number of needed row refreshes
|
516 |
|
|
state_x <= RW; -- process more SDRAM operations after refresh is done
|
517 |
|
|
|
518 |
|
|
-----------------------------------------------------------
|
519 |
|
|
-- place the SDRAM into self-refresh and keep it there until further notice
|
520 |
|
|
-----------------------------------------------------------
|
521 |
|
|
when SELFREFRESH =>
|
522 |
|
|
if (doSelfRfsh = YES) then
|
523 |
|
|
-- keep the SDRAM in self-refresh mode as long as requested and until there is a stable clock
|
524 |
|
|
cmd_x <= RFSH_CMD; -- output the refresh command; this is only needed on the first clock cycle
|
525 |
|
|
cke_x <= NO; -- disable the SDRAM clock
|
526 |
|
|
else
|
527 |
|
|
-- else exit self-refresh mode and start processing read and write operations
|
528 |
|
|
cke_x <= YES; -- restart the SDRAM clock
|
529 |
|
|
rfshCntr_x <= 0; -- no refreshes are needed immediately after leaving self-refresh
|
530 |
|
|
activeFlag_x <= (others => NO); -- self-refresh deactivates all rows
|
531 |
|
|
timer_x <= XSR_CYCLES; -- wait this long until read and write operations can resume
|
532 |
|
|
state_x <= RW;
|
533 |
|
|
end if;
|
534 |
|
|
|
535 |
|
|
-----------------------------------------------------------
|
536 |
|
|
-- unknown state
|
537 |
|
|
-----------------------------------------------------------
|
538 |
|
|
when others =>
|
539 |
|
|
state_x <= INITWAIT; -- reset state if in erroneous state
|
540 |
|
|
|
541 |
|
|
end case;
|
542 |
|
|
end if;
|
543 |
|
|
end process combinatorial;
|
544 |
|
|
|
545 |
|
|
|
546 |
|
|
-----------------------------------------------------------
|
547 |
|
|
-- update registers on the appropriate clock edge
|
548 |
|
|
-----------------------------------------------------------
|
549 |
|
|
|
550 |
|
|
update : process(clk_ok, clk)
|
551 |
|
|
begin
|
552 |
|
|
|
553 |
|
|
if clk_ok = NO then
|
554 |
|
|
-- asynchronous reset
|
555 |
|
|
state_r <= INITWAIT;
|
556 |
|
|
activeFlag_r <= (others => NO);
|
557 |
|
|
rfshCntr_r <= 0;
|
558 |
|
|
timer_r <= 0;
|
559 |
|
|
refTimer_r <= REF_CYCLES;
|
560 |
|
|
rasTimer_r <= 0;
|
561 |
|
|
wrTimer_r <= 0;
|
562 |
|
|
nopCntr_r <= 0;
|
563 |
|
|
rdPipeline_r <= (others => '0');
|
564 |
|
|
wrPipeline_r <= (others => '0');
|
565 |
|
|
cke_r <= NO;
|
566 |
|
|
cmd_r <= NOP_CMD;
|
567 |
|
|
ba_r <= (others => '0');
|
568 |
|
|
sAddr_r <= (others => '0');
|
569 |
|
|
sData_r <= (others => '0');
|
570 |
|
|
sDataDir_r <= INPUT;
|
571 |
|
|
hDOut_r <= (others => '0');
|
572 |
|
|
elsif rising_edge(clk) then
|
573 |
|
|
state_r <= state_x;
|
574 |
|
|
activeBank_r <= activeBank_x;
|
575 |
|
|
activeRow_r <= activeRow_x;
|
576 |
|
|
activeFlag_r <= activeFlag_x;
|
577 |
|
|
rfshCntr_r <= rfshCntr_x;
|
578 |
|
|
timer_r <= timer_x;
|
579 |
|
|
refTimer_r <= refTimer_x;
|
580 |
|
|
rasTimer_r <= rasTimer_x;
|
581 |
|
|
wrTimer_r <= wrTimer_x;
|
582 |
|
|
nopCntr_r <= nopCntr_x;
|
583 |
|
|
rdPipeline_r <= rdPipeline_x;
|
584 |
|
|
wrPipeline_r <= wrPipeline_x;
|
585 |
|
|
cke_r <= cke_x;
|
586 |
|
|
cmd_r <= cmd_x;
|
587 |
|
|
ba_r <= ba_x;
|
588 |
|
|
sAddr_r <= sAddr_x;
|
589 |
|
|
sData_r <= sData_x;
|
590 |
|
|
sDataDir_r <= sDataDir_x;
|
591 |
|
|
hDOut_r <= hDOut_x;
|
592 |
|
|
end if;
|
593 |
|
|
|
594 |
|
|
end process update;
|
595 |
|
|
|
596 |
|
|
end arch;
|